KR20160021549A - A memory system and a method for processing data in a memory - Google Patents

A memory system and a method for processing data in a memory Download PDF

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KR20160021549A
KR20160021549A KR1020140106933A KR20140106933A KR20160021549A KR 20160021549 A KR20160021549 A KR 20160021549A KR 1020140106933 A KR1020140106933 A KR 1020140106933A KR 20140106933 A KR20140106933 A KR 20140106933A KR 20160021549 A KR20160021549 A KR 20160021549A
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data
memory
cell
pilot
voltage value
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KR1020140106933A
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Korean (ko)
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오현오
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주식회사 윌러스표준기술연구소
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Priority to KR1020140106933A priority Critical patent/KR20160021549A/en
Publication of KR20160021549A publication Critical patent/KR20160021549A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits

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Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system and a method for processing data in a memory, and more particularly, to a memory system for efficiently processing data and a method for processing data in the memory.
To this end, the present invention provides a method comprising: programming data into a pilot cell and a data cell in the memory using a voltage of a predetermined nominal value; reading a recorded voltage value of the pilot cell; Setting a threshold voltage value for reading the data cell with reference to a voltage value and reading data in the data cell of the memory based on the set threshold voltage value, Wherein the cell is a cell at a predetermined position corresponding to at least one nominal value used for programming.
In addition, a memory system according to another embodiment of the present invention includes a memory having a plurality of physical blocks, the plurality of physical blocks each including a plurality of pages, and a memory controller configured to control the memory, Wherein the memory controller includes a programming module for writing / erasing data in the memory, a reading module for reading data recorded in the memory, and a control module for controlling the programming module and the reading module, Programming data into a pilot cell and a data cell in the memory using a voltage of a predetermined nominal value, wherein the pilot cell is a cell of a predetermined location corresponding to at least one nominal value used in programming the memory, , And the read module And the control module sets a threshold voltage value for reading the data cell with reference to the voltage value of the read pilot cell, and the read module sets a threshold voltage value for reading the data cell based on the set threshold voltage value, And the data of the data cell of the second cell is read out.

Description

[0001] DESCRIPTION [0002] MEMORY SYSTEM AND METHOD FOR PROCESSING DATA IN A MEMORY [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system and a method for processing data in a memory, and more particularly, to a memory system for efficiently processing data and a method for processing data in the memory.

Memory devices are the most essential microelectronic elements in digital logic design. Such a memory device is roughly divided into a volatile memory device and a nonvolatile memory device. The nonvolatile memory device can store data even when the power is turned off. The data stored in the non-volatile memory may be permanent or reprogrammable depending on the memory fabrication technique. Non-volatile memory devices can be used in applications in a variety of industries.

As a representative example of the nonvolatile memory, there is a flash memory. Flash memory can be used in many media that store data such as smart phones, digital cameras, solid-state drives (SSDs), and black boxes. In particular, an SSD using a NAND flash memory is widely used as a storage medium in laptops, desktops, and servers because it has less power consumption and is smaller in size than a hard disk drive (HDD) and is strong against impact. Furthermore, due to the recent development of smart phones and SSDs, the utilization of NAND flash memories is increasing.

Basically, flash memory cells can write and erase data by filling and emptying electrons in a floating gate.

More specifically, when a voltage is applied to cause a tunnel effect to a control gate in the state of an empty cell, a part of the electrons that have moved from the source to the drain due to the influence of the electric field generated according to the applied voltage Electrons of the floating gate can be filled by passing through the oxide film which is an insulator. Then, when the applied voltage is cut off, the electrons filled in the floating gate covered by the insulator become trapped in the floating gate. Therefore, the electrons can be kept filled with the floating gate even if power is not supplied. The write operation of the flash memory cell can be implemented by the above-described operations.

When a positive voltage is applied to the P layer in a state where electrons are filled in the floating gate, electrons trapped in the floating gate may be discharged to the outside of the floating gate through the insulating layer. Thereby, the cell can be returned to the empty state again. The erase operation of the flash memory cell can be implemented by the above-described operations.

However, NAND flash memory has a disadvantage that it is not allowed to overwrite data in place, unlike DRAM or HDD. That is, in order to overwrite, it is necessary to overwrite the memory cell after deleting the previously recorded portion. In other words, the flash memory must return the data to the initial state or the erased state before writing the data. This is referred to as erase-before-write. Therefore, even if data of 1 byte is changed due to the characteristics of cells which can not be overwritten, there arises a problem that all the pages in the block must be rewritten after erasing the entire block (here, The minimum unit is the page and the minimum unit of deletion is the block).

In addition, since the state change of the memory cell as described above causes the wear of the memory cell, the cell of the flash memory is generally allowed to be overwritten a certain number of times. That is, if a certain number of overwriting times is exceeded, the additional overwrite becomes no longer possible and only read is possible.

Due to the nature of the data stored in the flash memory, the update period may vary depending on the type of data. For example, most of the data files with small capacity are frequently written and deleted (i.e., updated), while most of the data files with large capacity are mostly accessible only for read operations. In addition, metadata may be one of hot data that is updated more frequently than regular data. Therefore, there is a need for a method of increasing the lifetime of the flash memory in consideration of these points.

In addition, the storage capacity of the flash memory is increasing. In addition, the block size and page size in the flash memory are also increasing for effective addressing. However, since the majority of the large number of files are still small in size, there may be inefficiency in using the page in a situation where only one file can be stored in one page.

On the other hand, all software running on the processor must be compiled to fit the target system. Optimization of the compiler can have a significant impact on the performance of the application. The focus is on processing speed and memory utilization to implement these optimizations. The operation of software pipelining and loop invariant code is an example of the optimization of these compilers.

Also, in an embedded or mobile environment, a computing system has problems associated with high power consumption. Some low-power processors are disconnecting power to remove leakage currents in an idle state. However, in this case, there is a disadvantage that system restoration may be ineffective or impossible, since data stored in volatile memory such as volatile registers may be lost.

In order to solve the problems associated with data backup of low power processors, techniques for non-volatile processors may be proposed. Such non-volatile processors may use non-volatile memory to replace conventional CMOS registers. However, due to the physical nature of the non-volatile memory, a non-volatile processor (NVP) paradigm requires new conditions such as an increase in the lifetime of the processor hardware to implement the compiler optimization described above ) May exist.

The present invention has the purpose of efficiently using a memory system.

According to an aspect of the present invention, there is provided a compiling method comprising: detecting data to be allocated to a register from a source code; Generating correlation information indicating a correlation between data stored in each of the one or more registers and the data to be allocated; Determining a target register to which the data to be allocated is to be allocated among the registers based on the correlation information; And allocating the data to be allocated to the determined target register.

The determining step may include determining a least used register as a target register when a target register having a correlation of at least a predetermined correlation with the data to be allocated is not determined.

In addition, the compiling method further comprises determining the least used register as a target register based, at least in part, on the number of uses of the register written by the wear leveling module .

The allocating step may include allocating data to be allocated to the target register without rewriting if the correlation between the data to be allocated and the data stored in the target register is equal to or greater than a predetermined correlation.

The determining step may include determining a register in which data having the highest correlation with the data to be allocated is currently stored, as a target register, based on the correlation information.

The step of generating the correlation information may further include reading values of data currently stored in each of the one or more registers on the virtual processor by configuring a virtual processor; Comparing values of the read data with values of data detected from the source code; And generating the correlation information based on the comparison.

The allocating step may include allocating two or more pieces of data having a correlation greater than or equal to a preset correlation to the same register.

Further, a computer-readable medium according to an embodiment of the present invention is a computer-readable medium having stored thereon instructions for converting a source code into a machine language, the instructions comprising: A command for detecting the command; Instructions for generating correlation information indicative of a correlation between data stored in each of the one or more registers and the data to be allocated; Determining a target register to which the data to be allocated is to be allocated among the registers based on the correlation information; And an instruction to allocate the data to be allocated to the determined target register.

Further, a processor according to an embodiment of the present invention includes: one or more registers to which detected data from a source code can be assigned; And a controller for controlling the processor, wherein the controller generates correlation information indicating a correlation between the data stored in each of the one or more registers and the data to be allocated, and determines, based on the correlation information, A target register to which the data to be allocated is to be allocated, and allocates the data to be allocated to the determined target register.

Meanwhile, a method of processing data in a memory according to an embodiment of the present invention includes: programming data by applying a voltage of a predetermined nominal value to a pilot cell at a predetermined position in the memory; Reading a recorded voltage value of the pilot cell; Correcting a nominal value corresponding to the data based on a voltage value of the read pilot cell; And programming the data into a data cell of the memory using the calibrated nominal value.

In this case, the reading step reads the voltage value of the pilot cell at a higher resolution than the voltage step between each data for programming.

The calibration may further include: calculating a difference value between the voltage value of the read pilot cell and the predetermined nominal value; And adding the calculated difference value to the predetermined nominal value to obtain the corrected nominal value.

The calibration may further include calculating a ratio between the voltage value of the read pilot cell and the predetermined nominal value; And scaling the predetermined nominal value based on the calculated ratio to obtain the corrected nominal value.

Also, the pilot cell is located in the same block or page as the data cell.

The data processing method may further include: obtaining information on the number of times of deletion of the block in which the pilot cell is located or information on the number of times of recording the page; And shifting the position of the pilot cell based on the deletion count information or the recording count information.

Also, the pilot cell includes a plurality of cells each corresponding to a plurality of nominal values used in programming the memory.

Also, a memory system according to an embodiment of the present invention is a memory having a plurality of physical blocks, each of the plurality of physical blocks including a plurality of pages; And a memory controller configured to control the memory, the memory controller including a programming module for writing / erasing data to / from the memory, a reading module for reading data written to the memory, Wherein the programming module programs the data by applying a voltage of a predetermined nominal value to a pilot cell at a predetermined location in the memory, The control module corrects the nominal value corresponding to the data based on the voltage value of the read pilot cell and uses the corrected nominal value to update the data Is programmed.

According to another aspect of the present invention, there is provided a method of processing data in a memory, comprising: programming data in a pilot cell and a data cell in the memory using a voltage of a predetermined nominal value; Reading a recorded voltage value of the pilot cell; Setting a threshold voltage value for reading the data cell with reference to a voltage value of the read pilot cell; And reading data in a data cell of the memory based on the set threshold voltage value, wherein the pilot cell has a predetermined threshold value corresponding to at least one nominal value used in programming the memory, Cell.

In this case, the reading step reads the voltage value of the pilot cell at a higher resolution than the voltage step between each data for programming.

Also, the pilot cell is located in the same block or page as the data cell.

The data processing method may further include: obtaining information on the number of times of deletion of the block in which the pilot cell is located or information on the number of times of recording the page; And shifting the pilot cell based on the number-of-deletion information or the number-of-times-of-recording information.

Also, the pilot cell includes a plurality of cells each corresponding to a plurality of nominal values used in programming the memory.

In addition, the step of setting the threshold voltage value may include obtaining a read voltage value of a plurality of pilot cells programmed using the same nominal value in the memory, wherein the read voltage of the obtained plurality of pilot cells And the threshold voltage value is set based on the average of the values.

According to another embodiment of the present invention, there is provided a memory system including: a memory having a plurality of physical blocks, each of the plurality of physical blocks including a plurality of pages; And a memory controller configured to control the memory, the memory controller including a programming module for writing / erasing data to / from the memory, a reading module for reading data written to the memory, Wherein the programming module is programmed with data of a pilot cell and a data cell in the memory using a voltage of a predetermined nominal value, And the read module reads the recorded voltage value of the pilot cell, and the control module refers to the voltage value of the read pilot cell, A threshold voltage value for reading the threshold voltage, And the reading module reads the data of the data cell of the memory based on the set threshold voltage value.

According to the embodiment of the present invention, the memory system can be efficiently used.

1 is a schematic diagram of a memory system according to an aspect of the present invention.
Figure 2 schematically illustrates a memory system in accordance with an aspect of the present invention.
Figure 3 illustrates a method of file auto save over time in a memory system, in accordance with an embodiment of the present invention.
Figure 4 shows a flowchart of steps for processing data in file auto-save in a memory system, in accordance with an aspect of the present invention.
5 is a flowchart illustrating a method of allocating data to a register according to an embodiment of the present invention.
Figure 6 illustrates an exemplary block of data comprising pilot cells in accordance with an aspect of the present invention.
7 illustrates an exemplary variation of placement of pilot cells according to a programming count and according to an aspect of the present invention.
8 illustrates an exemplary read strategy using pilot cells within a page in accordance with an aspect of the present invention.
Figure 9 illustrates an exemplary change in threshold voltage after data programming.
10 illustrates an exemplary voltage reading mechanism using pilot cells in accordance with an aspect of the present invention.
11 illustrates an exemplary voltage reading technique for a data cell using a switch in accordance with an aspect of the present invention.
Figure 12 illustrates an exemplary data cell readout scheme using a switch in accordance with an aspect of the present invention.
13 illustrates an exemplary change in threshold voltage after data programming.
14 is a flowchart showing a data processing method of a memory according to an aspect of the present invention.
15 is a flowchart showing a data processing method of a memory according to another aspect of the present invention.

Various aspects are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following examples, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It will, however, be evident that these aspects may be practiced without these specific details.

Various aspects of the present disclosure are described below. The descriptions herein may be implemented in a wide variety of forms. It is also evident that any particular structure, functionality, or both, disclosed herein is merely exemplary. Based on the description herein, one of ordinary skill in the art will appreciate that aspects disclosed herein may be implemented independently of any other aspects, and that these aspects It should be appreciated that aspects of two or more of these may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of aspects set forth herein. Also, devices may be implemented or implemented using other structures, functionality, or structure and functionality that differ from or in addition to one or more aspects of the aspects presented herein. In addition, one aspect of the invention may include at least one element of the claims.

1 is a schematic diagram of a memory system 100 in accordance with an aspect of the present invention.

Although the present disclosure describes flash memory by way of example, other memory devices (e.g., volatile memory) other than flash memory (i.e., non-volatile memory) may also be included within the scope of the present invention.

The memory system 100 in FIG. 1 may largely consist of an application 101 (or a host), a file system 102 and an SSD 103. The components in FIG. 1 are exemplary only, and some of the components in FIG. 1 may be omitted, or components other than the components in FIG. 1 may be included in the memory system 100. Additionally, the SSD 103 in FIG. 1 may be replaced by a memory and memory controller capable of performing similar functions.

In one aspect of the invention, applications 1 through N (101) may include any device or program that requires data storage in a flash memory device such as an SSD.

In one aspect of the present invention, the file system 102 may be referred to as a host or application domain with an application 101. This file system 102 can access any data in the SSD via a logical sector address. In this case, the flash translation layer 106 of the SSD controller 104 can map the logical sector address and the physical address by converting the logical sector address into a physical address. In addition, the file system 102 may refer to a virtual sector implemented by the flash translation layer 106. In addition, the file system 102 herein may be used interchangeably with the application 101.

Due to the physical characteristics of the flash memory 105, separate management of read / write / erase operations is required to use the flash memory 105 as a hard disk. The flash translation layer 106 may refer to system software developed for this purpose. The flash conversion layer 106 includes a mapping algorithm for converting a logical address into a physical address, an algorithm for determining a data file size, an algorithm for performing wear leveling, and an algorithm for controlling a voltage to be applied to the flash memory 105 .

In one aspect of the present invention, the flash translation layer 106 of the SSD controller 104 includes an address allocator 108 for mapping logical and physical addresses, a wear-leveler for performing wear- leveler 110 and a garbage collector 109. A data file size analyzer 111 for analyzing and comparing data file sizes and a voltage controller 110 for controlling a voltage to be applied to the flash memory 105. [ (116), and the like. Additionally, the components of flash conversion layer 106 described above are exemplary only, and additional components may be included in flash translation layer 106, or a portion of the components described above may be omitted.

The wear leveler 110 may perform block level, page level and / or bit level wear leveling in order to increase the life of the flash memory 105.

The garbage collector 109 may perform operations such as marking invalid data or obsolete data, copy back operations to other blocks, pages and / or bits, and deletion of the unwanted data at block time Wear leveling can be implemented by performing an operation or the like. Thus, data may be assigned to appropriate physical block locations, page locations, and / or bit positions to implement wear leveling.

In addition, the address allocator 108 may generate a mapping table or the like for mapping the bits to a memory cell (e.g., MLC, TLC, etc.) having a plurality of voltage state levels to appropriate voltage state levels.

The address allocator 108 may implement allocation of logical addresses and physical addresses in block, page or bit (cell) units of memory.

Voltage controller 116 may apply a drive voltage level to the memory cell, for example, to a value that is greater than or equal to the previous in-cell write mode to represent one or more bits. The application of this voltage may be performed based on the mapping table generated by the address allocator 108. The voltage controller 116 may also determine the value of the drive voltage level to be applied to the memory cell by checking the voltage level of the memory cell corresponding to one or more bits written to the previous memory cell. The intra-cell recording mode here may display a value for counting the number of intra-cell recordings in one erase cycle (or erase count).

The data file size analyzer 111 may determine the size of the incoming data file. Through this determination, the data file size analyzer 111 can determine, for example, whether the incoming data file is smaller than the size of the divided subpage.

Although not shown in FIG. 1, the SSD controller 104 may include a programming module (write and erase) and a read module for writing, deleting, and reading data to the flash memory 105.

Thus, the SSD controller 104 can control the overall operation of the SSD. The SSD controller 104 can receive the logical address from the application 101 or the file system 102. [ The flash translation layer 106 of the SSD controller 104 may convert the input logical address into a physical address. The translated physical address may be passed to a memory technology device layer (107) or flash memory (105). The memory technology device layer 107 may refer to an interface layer for supporting various flash memories, RAM, and the like. Additionally, such a memory technology device layer 107 may be an optional configuration.

Flash memory 105 may be comprised of a plurality of memory cells having a string structure, as is well known to those skilled in the art. The set of memory cells is generally referred to as a cell array. The cell array of the flash memory 105 is composed of a plurality of memory blocks. Each memory block 112 consists of a plurality of pages 113. Each page consists of a plurality of memory cells or data cells 114 sharing a word line. Here, single bit data, multi bit data, or triple bit data can be stored in one memory cell or data cell 114. For example, a memory cell in which single bit data can be stored is called a single level cell (SLC), a memory cell in which multi-bit data can be stored is a multi level cell (MLC) , And the memory cell in which the triple bit data can be stored is referred to as a triple level cell (TLC).

Figure 2 schematically illustrates a memory system 200 in accordance with an aspect of the present invention.

As shown in FIG. 2, the memory system 200 may include a memory controller 201 and a flash memory 202.

The memory controller 201 can control the overall operations of the flash memory 202. [ The memory controller 201 includes a control module 203 for performing wear leveling, bit allocation, voltage control and page division, a programming module 204 for performing write and erase operations, a read module And a conversion module 206 for performing an operation of integrating data and integrating the data into another address.

In one aspect of the present invention, when an operation request for the flash memory 202 is received from a host or an application or the like, the control module 203 performs wear leveling based on meta data stored in the meta area, Bit allocation, voltage control, page division, and the like.

In addition, the control module 203 may control the operation of the programming module 204 and the reading module 205.

In an aspect of the present invention, the control module 203 determines whether an in-cell write mode or an in-page write mode, based on the number of data write requests for a memory cell, Can be determined. The control module 203 may determine a drive voltage level value to be applied to express one or more bits in the memory cell based on the determined write mode. In addition, the control module 203 may generate a mapping table or the like in which one or more bits are mapped to a high or the same level state from the low state levels of the state levels of the memory cell according to the recording mode. The generated mapping table may be stored in the flash memory 202 (e.g., a meta area).

The wear leveling according to a further aspect of the present invention may refer to in-page wear leveling or micro-leveling rather than inter-page wear leveling. More specifically, bad blocks are often generated when one or more cells exceed a wear threshold, rather than a group of cells per page. Thus, in order to implement such cell-based (i.e., bit-level) wear leveling, the control module 203 may modify (e.g., shift (or rotate, ) And / or scrambling) or to change (e.g., inversion) the data value that is written to the bit position within the page.

In addition, the control module 203 can determine the type of data to be written and determine the technique for writing each data bit in one page based on the determined type of data. More specifically, the control module 203 can determine the type of data to be recorded (e.g., file type (doc, xls, ppt, txt, pdf, wav, mp3, jpg, zip, The type of data to be recorded is determined, the control module 203 determines whether the type of data to be recorded is determined based on a predetermined algorithm, It is also possible to select an appropriate technique among the techniques (shifting, reversing, scrambling and inverting), determining whether to divide subpages, determining the number of subpages to be partitioned, It is possible to determine the allocation scheme of the bits.

Also, the control module 203 may be implemented as firmware. For example, the wear control module 203 may be included in a Flash Translation Layer (FTL). Here, the flash conversion layer is system software that manages erase / write / read operations to use the flash memory 202 as a hard disk, as described above. The flash translation layer can perform voltage control, mapping information management, bad block management, data integrity management in case of unexpected power failure, and wear management.

According to the control of the control module 203, the programming module 204 can record the data bits to be recorded in one page. More specifically, the programming module 204 may apply a drive voltage level value for representing one or more bits to a memory cell, depending on the voltage value determined by the control module 203. [ In addition, the programming module 204 may write data sequentially to the pages 208 that make up the block 207. Additionally, the programming module 204 may perform an erase operation on the memory cell in response to a subsequent write request if a plurality of state levels of the memory cell are used. In addition, programming module 204 may perform a delete operation on a memory cell in response to a subsequent write request if all sub-pages in the page are used.

In addition, the programming module 204 may write data to or delete data from the user area of the flash memory 202. The programming module 204 may store metadata (e.g., in-cell record information, delete counts, or recording mode counts, etc.) stored in the meta area 206 of the flash memory 202 Can be changed.

According to one aspect of the present invention, the programming module 204 stores difference data corresponding to the difference generated by comparing the data of the previous file with the data of the current file to the file auto save function, which will be described later, 208 to the data of the original file allocated to the original file. Page 208 may also include a spare area 209 and may be assigned to the spare area 209 by the programming module 204. [

In addition, the programming module 204 may compare the data of the current file with the data of the previous file for file auto-save, and if the data corresponding to the difference of the data is no longer found, And inserts and / or adds difference data corresponding to the difference to data of the original file to generate corresponding data, and converts the data of the final file generated by the difference data to the data of the original file into a new address Can be assigned to the designated new page 208. [

In one aspect of the present invention, the read module 205 can read the data recorded in the user area of the flash memory 202. [ The reading module 205 can read the data recorded in the user area based on the mapping information between the logical address and the physical address by referring to the data stored in the meta area. That is, the reading module 205 refers to the recording mode count, the recording mode information, the voltage state level of the memory cell, the mapping information, and / or the count information stored in the meta area, Can be interpreted.

In one aspect of the invention, the meta area may store metadata (or control data) for managing the flash memory 202. Such meta data may include recording mode information, recording mode count information, mapping table, and the like. The meta area may include at least one physical block consisting of a plurality of physical pages having a plurality of memory cells.

The metadata may include difference data indicating a difference between the data of the original file generated by the file auto save function and the data of the current file, the recording mode information, the recording mode count information, and the mapping table . ≪ / RTI >

Additionally, the meta area may be incorporated into the user area. In this case, for example, metadata such as recording mode information and / or count information will be stored in a page or block of the user area.

Additionally, the metadata may be stored in a header (not shown) in a page or block of the user area.

The user area may refer to a data storage of conventional flash memory. This user area may comprise at least one physical block consisting of a plurality of physical pages having a plurality of cells.

In an aspect of the present invention, the page 113 in the block 112 in the flash memory 105 may be composed of a plurality of data cells, and the data may be sequentially stored in the plurality of cells. For example, if the size of one page is 4 KB, and the current size of the original file is 2 KB, the data in sequential order from the next 2 KB data cell in physical order of the memory cells in response to subsequent storage of the same data Can be added.

In one aspect of the invention, one page of the user area of the flash memory 202 may comprise a plurality of memory cells. Each of these memory cells can represent three or more different states, respectively, depending on the value of the driving voltage level. For example, if the memory cell is an MLC, the memory cell may represent four different states. Further, when the memory cell is TLC, the memory cell can represent eight different states.

According to one aspect of the present invention, the read module 205 can read the data stored in the flash memory. In addition, the read module 205 reads the difference data by comparing the data of the previous file sequentially allocated to the page 208 with the data of the current file at the time of file auto save, which will be described later It is possible.

As described above, the programming module 204 generates the final file data for file auto-save by inserting and / or adding the difference data into the original data, The read module 205 may generate not only the data of the original file stored in the page 208 but also the data of the previous file stored in the page 208 in succession The difference data can be read.

The conversion module 206 can generate data of the modification file by the difference data corresponding to the difference between the data of the previous file and the data of the current file and the data of the original file at the time of file auto save, Address into the new page 208 designated by the address.

Specifically, the conversion module 206 may determine and / or determine that the difference data due to the comparison between the data of the previous file and the data of the current file no longer occurs, In order to store corresponding data, it is possible to add and / or insert and edit a plurality of difference data stored in the sequential order in the original file data, and to convert the same into a new address in the flash memory (for example, As well as conversion from 0x2001 to 0x2002).

Alternatively, the transform module 206 may perform the transform operation as shown in FIG. 3 in response to a file close request. For example, at the time of forced termination of the application 101 by the user, the application 101 may request a file close and the conversion module 206 may automatically perform a conversion operation as shown in Fig. 3 Can be performed. Such a conversion operation may be automatically performed not only in response to a file close request but also in accordance with a preset number of times of storage (for example, ten times of storage) and a preset time (e.g., 30 minutes).

Figure 3 illustrates a method of file auto save over time in a memory system, in accordance with an embodiment of the present invention.

The memory system proposed by the present invention shown in FIG. 3 is a memory system in which the data of the original file and / or the data of the previous file are compared with the data of the current file in accordance with file auto save, The present invention proposes a technical feature that data can be stored and / or added sequentially from the next cell of data of the original file physically stored in the same page.

As shown in FIG. 3, the file auto save method in the existing memory system is a method in which, in accordance with a predetermined automatic storage period, a user who uses the application 101 stores data of the original file in the first cycle And converting the entire changed data into a page of a new address in the flash memory to allocate and / or store the modified data. Thereafter, the second to n-th periods are added and / or changed to the page designated by the new address by comparing data that is different from the previous data by the above-described method, and the existing memory system has difficulty in efficiently managing the memory , Thereby increasing the level of wear of a non-volatile memory system (e.g., flash memory) and shortening the life of the memory system. Furthermore, in the case of existing techniques, there may also be the inconvenience that the modified data must be converted to the appropriate location of the new page each time the data is modified.

However, the technical feature of the present invention shown in FIG. 3 is that the original data of the user of the application 101 is compared with the previous data by the modification and / or modification until the modification and / The difference data can be stored within the same page designated by the same address where the data of the original file is allocated and / or stored. Accordingly, the difference data can be edited and converted into the final file data and assigned to a new page designated by a new address.

Referring to FIG. 3, the data of the original file may be stored and / or assigned to a page designated by the address 0x2001 in the flash memory. The user of the application 101 can modify the data of the original file within a predetermined period (for example, 5 seconds) by the file auto save function, Adding work may be required.

For example, the memory system of FIG. 3 differs from the existing memory system that allocates the entire modified file data to a new address. When the user modifies the data of the original file within the first cycle, The data of the file modified in the first cycle is compared with the data of the file modified in the first cycle so that only the first difference data corresponding to the difference of the data is sequentially allocated to the same page of the same address of 0x2001 in which data of the original file is stored And / or stored.

The location in the same page where the data is additionally stored may be the position of a spare area 209 already allocated in the page.

Thereafter, when the user modifies the data of the original file and the first difference data in the second cycle, the memory system updates the data of the original file file and the first difference data, It is possible to sequentially allocate and / or store only the second difference data corresponding to the difference of the data to the same page of the same address of 0x2001 in which the data of the original file and the first difference data are stored .

In the same process, when the third difference data and the fourth difference data shown in FIG. 3 are 20 seconds corresponding to four cycles, the data of the original file and the first difference data The fourth difference data may be sequentially allocated and / or stored on the same page.

If the memory system can not detect the difference data corresponding to the difference between the data of the previous file and the data of the current file according to the file automatic saving cycle, the memory system may terminate the comparison detection operation with the data of the previous file And then inserts and / or converts the first difference data to the fourth difference data into the data of the original file so that the data of the original file thereafter can be matched with the data of the final file to be modified and / or edited Operation can be performed. At the same time or at a later time, the data of the converted final file can be stored in a new page corresponding to the new address 0x2002.

In addition, when the memory system is terminated by the user or the application 101 after a predetermined period has elapsed, the memory system can terminate the comparison detection operation with the data of the previous file, and thereafter, And / or to insert and / or convert the difference data generated during the period into the data of the original file so as to match the data of the edited final file. At the same time or at a later time, the data of the converted final file can be stored in a new page corresponding to the new address.

In a further aspect of the present invention, each of pages 113 in block 112 in flash memory 105 may be comprised of a plurality of sub-pages. For example, when the size of the page 113 is 4 KB, four sub pages in units of 1 KB can be formed in one page 113. [ Therefore, when there are a plurality of subpages, the additional data to be newly stored can be sequentially stored according to the number of the subpage.

Unlike the conventional memory system, the flash memory can be efficiently managed, the new page can not be wasted, and the effect of the leveling of the wear can be achieved, which can ultimately extend the life of the flash memory.

The technical features shown in FIG. 3 will be described later in detail with the step of processing data in file auto save shown in FIG.

Figure 4 shows a flowchart of steps for processing data in file auto-save in a memory system, in accordance with an aspect of the present invention.

The memory system 200 may perform an operation of comparing the previous version of the data file with the current version of the data file in response to the request to automatically save the data file by the application 101 to determine the changed data part (S110) .

When the file is modified and / or changed by the user of the application 101, the file is stored in the flash memory 202 (or the flash memory 202) according to a predetermined time by the file auto save function provided by the memory system 200 The modified and / or modified data of the portion may be stored.

In this case, the memory system 200 may compare the data of the previous version file with the data of the current version file, and may modify and / or change the data of the previous version file and the data of the current version file The data portion can be determined and determined (S120).

According to an aspect of the present invention, the data portion corresponding to the difference may be periodically determined and determined according to a predetermined time for file auto-save, and the file auto-save ) May exist in a plurality of data portions.

The memory system 200 further includes an in-page area 208 in which data of a previous version file is stored after the step of determining the changed data (S110) page) area of the current storage area of the data to be stored next (step S120).

Specifically, in order to store the difference data determined and / or determined for automatic file storage in the same in-page area, the memory system 200 allocates data corresponding to the difference The current storage area to be made can be identified.

Thereafter, the memory system 200 sequentially allocates and / or writes data portions corresponding to data differences between the data of the previous version file and the current version file to the current storage area of the in-page area, (S130).

As shown in FIG. 3, data of an original file corresponding to data of a previous version file is allocated to one page designated by an address of 0x2001. In accordance with the change of the automatic storage time for automatic file storage, The data portion corresponding to the data difference between the data and the current version file is sequentially stored in the same page designated by the address of 0x2001 in the flash memory.

More specifically, the memory system 200 may form first to fourth difference data, for example, when four cycles have elapsed according to a predetermined automatic storage time. The difference data may be sequentially stored in the same page in the flash memory. That is, the memory system 200 inserts the difference data into the original data every period of the automatic storage time and stores the data corresponding to the corrected difference in the same page sequentially .

According to an aspect of the present invention, the memory system 200 may determine and / or determine that the difference data due to the comparison of the data of the previous file with the data of the current file no longer occurs. Alternatively, the memory system 200 may receive a file termination request from an application. Alternatively, the memory system 200 may determine that a predetermined period of time has elapsed or a predetermined number of automatic saves have been made. Accordingly, in order to store data corresponding to the final file in the flash memory, the memory system 200 allocates a new address in the flash memory and inserts the plurality of sequentially stored difference data into an appropriate position of the original file data, The file data can be converted into a final version file (for example, conversion from 0x2001 to 0x2002 as shown in FIG. 3) (S140).

As noted above, the memory system 200 may periodically generate difference data according to a predetermined auto-save time (e.g., 5 seconds) of the file autosave function, A plurality of difference data can be generated.

The file auto save function in the existing flash memory is a feature that, when the data is modified and / or edited by the user using the application 101 due to the characteristics of the flash memory, There is a problem that edit data can not be stored in the same page in the flash memory. Accordingly, every time the file automatic saving function is executed, editing data added and / or added to the previous data is assigned to a new page address in the flash memory Respectively.

However, according to the steps S110 to S140 shown in FIG. 4, the difference data corresponding to the difference between the previous file data and the current file data can be sequentially stored in the page allocated to one address, In the process of forming the final file data, the wear leveling in the memory can be implemented through editing of the difference data and / or conversion to a new address. Accordingly, the life of the flash memory can be increased by efficiently managing the flash memory.

5 is a flowchart illustrating a method of allocating data to a register according to an embodiment of the present invention.

Also, each step of the flowchart shown in Fig. 5 is not essential and some steps may be omitted or added as needed.

As described above, in the nonvolatile processor (NVP) paradigm, the registers constituting the nonvolatile processor may be formed in the form of a nonvolatile memory such as an SSD. For example, in the case of a CPU configured with a nonvolatile processor, since a lot of data is written and overwritten (rewritten) in a register made up of an SSD, if the wear leveling is not properly performed due to the characteristics of the SSD, .

According to an embodiment of the present invention, a compiler (or controller of a processor) may detect data to be allocated to registers located in a processor or a CPU from the source code (S210). The above-described data is merely an example, and the present invention can include all kinds of data that can be allocated to a register in a compiler.

In addition, a general compiler performs compiling and allocates data to a register. A compiler according to an embodiment of the present invention may first detect data to be allocated to a register from the source code so that the compiler can perform efficient compilation have.

According to an embodiment of the present invention, the compiler may generate correlation information indicating a correlation between the data stored in each of the one or more registers and the data to be allocated (S220). More specifically, for example, such correlation information may be generated by reading the values of data currently stored in each of the one or more registers on the virtual processor by constructing a virtual processor, And comparing the values of the data. That is, by the above-described method, it is possible to determine what value is written to a specific register through the previous operation on the source code.

The compiler may determine a target register to which the data to be allocated is to be allocated among the registers based on the correlation information (S230). This correlation can be determined by comparing the data to be allocated with the data stored in the register, and by the number of matched bits. The more bits the data to be allocated and the data stored in the register are stored, the higher the correlation between the data to be allocated and the data stored in the register.

According to an embodiment of the present invention, the compiler may allocate the data to be allocated to the determined target register (S240). Also, the compiler may allocate the data to be allocated to the target register without rewriting if the correlation between the data to be allocated and the data stored in the target register is equal to or greater than a predetermined correlation. That is, when a register storing the same value as the data to be allocated is searched, the compiler can allocate the data to be allocated to the searched register without rewriting. This data allocation allows data to be allocated without affecting the number of register rewrites.

The compiler can allocate the data to the least used register when there is no data stored in a register having a correlation of at least a predetermined correlation with the data to be allocated. Since the registers of non-volatile processors have a limited number of writes, there is a need to uniformly use all the registers. Thus, using the wear leveling module, the number of times the register is used can be recorded, and data can be allocated from the least used register so that the number of uses of all registers is evenly distributed. Thus, the compiler or controller can search for the least used register based at least in part on the number of uses of registers written by the wear leveling module. The compiler or controller may allocate data to the searched register (target register).

Furthermore, according to another embodiment of the present invention, the compiler can detect from the source code the correlation of the data to be allocated to the register. The compiler can allocate two or more pieces of data having the correlation more than a predetermined correlation among the data to the same register. As described with reference to Fig. 8, m in the calculation 1 and n in the calculation 2 may be the data having the correlation. At this time, when the data is allocated to the register, the compiler can allocate the data to the same register. For example, m in computation 1 and n in computation 2 have the same value of 1. Therefore, the compiler can allocate m, n to the register R1. At this time, the correlation with a predetermined correlation or more may mean that both data are the same. The above-described data and registers are only examples, and various data can be assigned to various registers. In addition, the correlation described above is also only an example, and there may be various correlations for efficient compilation. In addition, the correlation means not only the case where the data are the same but also a case where bits equal to or more than a certain level are equal in the data unit.

Figure 6 illustrates an exemplary block of data comprising pilot cells in accordance with an aspect of the present invention.

As discussed above, memories such as flash memory may use arrays of analog memory cells to store data. Each analog memory cell may store an amount of analog values such as a charge amount or a voltage to represent information stored in the cell. For example, each memory cell holds a certain amount of charge. The range of such analog values can generally be divided into specific regions, each of which can correspond to one or more data bit values. For example, the SLC can be divided into two regions, and cells having multiple levels, such as MLC, can be divided into four or more regions.

In a memory such as an SSD, data can be written to an analog memory by writing a nominal analog value corresponding to the required bits. Since these analog values may have varying statistical distributions, the choice of nominal values used to program the different levels can have a significant impact on the performance of the memory cell array.

When the nominal values are adjacent to each other, there is a high probability that an error occurs in the reading of the memory cell. On the other hand, if the nominal values differ from each other, the dynamic range of analog values in the memory cell array can be increased. In this case, more power may be consumed and the programming speed of the memory cell may be slower.

Since the nominal values in each cell have attributes that can be changed temporally and spatially, the use of certain predetermined values for reading and writing may be related to memory performance such as bit error rate (BER) It can have an adverse effect.

Also, in the presence of more voltage level states in one cell, the probability of errors occurring due to the nature of the analog voltage in writing and reading data may be higher.

In this situation, the present invention proposes a programming technique that uses predetermined nominal values in a pilot cell located in a predetermined region of a page. Through this programming technique, the analog voltages read in the pilot cells can be used to compensate for errors, changes in voltages in adjacent data cells, and the like.

6, one page in a block of memory according to an aspect of the present invention may consist of one or more (e.g., four) pilot cells and a plurality (e.g., 32768) of data cells . Although four pilot cells are illustrated by way of example in FIG. 6, more or fewer pilot cells may also be included within the scope of the present invention.

6 illustrates an SSD comprised of MLCs having four nominal values. Four pilot cells labeled A, B, C and D in each page can be preset. For each pilot cell, pilot cell A may be assigned 11, pilot cell B 10, pilot cell C 00, and pilot cell D 01. These pilot cells may each have a unique nominal value (i.e., a reference voltage value).

The nominal values corresponding to the pilot cells A, B, C and D, respectively, may be a fixed value, differently allocated for each page, or may be changed in various ways to implement wear leveling. Further, these pilot cells A to D may be arranged at various positions within the page. For example, the pilot cells may be located at the front, middle, or end of the page. The placement of such pilot cells may be determined based on the type of pages, the programming count, and the random manner.

By using these pilot cells, data can be programmed using predefined nominal values in the pilot cells located at predetermined locations in the page. Next, a read or write operation to the data cell can be performed by referring to the values of the pilot cells.

7 illustrates an exemplary variation of placement of pilot cells according to a programming count and according to an aspect of the present invention.

As shown in FIG. 7, the pilot cells may be placed at various locations based on programming count and / or page. Through placement into these various locations, the pilot cells may represent more useful values in providing a reference to data cells. Additionally, placement in these various locations may also achieve wear leveling effects within the page.

According to one aspect of the present invention, after writing data by applying a voltage value to the pilot cells, the memory controller 201 reads the pilot cells before writing to or reading from the data cells, The voltage value to be used can be determined.

In accordance with an aspect of the invention, memory controller 201 may read analog voltage values for pilot cells after writing values to pilot cells. In this specification, programming in general can include a process of re-reading the voltage for verification.

Instead of a readout process for verification, more accurate voltage values can be read, using a higher resolution than the voltage steps used for programming. For example, when a value of '00' is written in the pilot cell D, it can be written at a voltage of 5V. However, when the corresponding cell is read, it can be read with a voltage of 4.7V. The opposite situation may also arise.

In this situation, at the programming time in the data areas, the write operation can be performed using the calculated nominal values associated with the read voltages in the pilot cells. That is, as described above, in the case where the nominal values in the reading process do not reach the intended reference voltage value (recording 5 V and reading 4.7 V), the difference between the voltage value at the time of writing and the voltage value at the time of reading (E.g., 0.3 V) can be considered in programming the data cell. That is, when programming a data cell, it can be written at a voltage of 5.3V. In this case, a more accurate reading can be made in the case of reading the data cell than when the reference voltage value is 5V.

Conversely, in the case where the nominal values in the readout process exceed the intended reference voltage value (write 5 V and read 5.3 V), a voltage equal to the difference between the voltage value at the time of writing and the voltage value at the time of reading, -0.3 V) may be considered in programming the data cell. That is, when programming a data cell, a voltage of 4.7 V can be written. In this case, a more accurate reading can be made in the case of reading the data cell than when the reference voltage value is 5V.

This technique can be based on the assumption that the sensitivity and responsiveness of the voltages of the cells in one page are similar. That is, other variables that affect the wear level, temperature, and sensitivity of the cells may have similar characteristics in programming within the same page. Thus, due to programming using feedback from these pilot cells, the optimal nominal value can be determined and maintained. Through this process, since the programming process has been programmed to reflect the feedback from the pilot cells, the readout process can be performed simply using a predefined reference voltage value without special calculation operations.

8 illustrates an exemplary read strategy using pilot cells within a page in accordance with an aspect of the present invention.

The memory controller 201 may perform programming for the data area using the predefined nominal values used in the pilot cells without reflecting the feedback referenced in the pilot cells. That is, pages comprising pilot cells and data cells may be programmed using the same nominal values given. Instead, in the read process, the memory controller 201 first reads the pilot cells and calculates the threshold voltage values to be used to read the data cells by referencing the read analog voltage values in the pilot cells.

Figure 8 illustrates, by way of example, a process for determining a read voltage value for data cells by first referencing read voltage values of pilot cells in a read process.

Each of the pilot cells A, B, C, and D may be programmed using a nominal value (reference voltage value) corresponding to '11', '10', '00', '01'. Voltage values that can be read in the programmed cells are indicated by circles in Fig. For example, as shown in FIG. 8, in the case of the pilot cell A in which the value of '11' is recorded, a voltage value lower than the reference voltage value can be read. Further, in the case of the pilot cell B in which the value of '10' is recorded, it can be read as a voltage value higher than the reference voltage value.

The read voltage value for these pilot cells may be used as a new reference voltage for that page. That is, as shown in FIG. 8, the voltage level for reading the value of '10' is different from the reference voltage for reading the pilot cell B which is not the default reference voltage used for writing the value of '10' A measured reference voltage may actually be used as a voltage level value for reading data cells in the page.

Thus, a read process using pilot cells in this manner can result in less read errors than a conventional read process.

In a further aspect of the present invention, a plurality of pilot cells for nominal values within a block are presented herein, but alternatively analog voltage values or nominal values may be averaged and calculated block by block Or may be averaged over time. Further, these analog values can be stored in a temporary memory, such as, for example, a DRAM, thereby enabling faster data access.

Figure 9 illustrates an exemplary change in threshold voltage after data programming.

If an arbitrary time passes after the data is programmed, the distribution of the analog voltage value can be changed as shown in Fig. In such a situation, a method can be considered in which nominal values are adaptively defined for each page. Since this method considers the different response characteristics of the cells, it can have advantages in terms of error occurrence and power consumption.

More specifically, the nominal voltage values may be adaptively selected during programming of the data. Next, these voltage values may be stored as parameters to be used for reading the storage. This should be stored as a different parameter value for each page. However, these parameters can be huge overhead in terms of storage. That is, it is necessary to provide a large space for allocating these parameters.

The technical features according to one aspect of the present invention in connection with FIGS. 7 and 8 above can refer to the analog voltage values for the pilot cells efficiently without requiring a separate space for storing these parameters. Can be read.

Therefore, according to one aspect of the present invention, as shown in FIG. 9, when the pilot voltage level is determined by referring to the pilot cells in advance, even if the voltage level changes after programming of the data, It is possible to find an appropriate threshold voltage value. That is, when pilot cells are used, more robust threshold voltage values can be generated without wasting storage space.

10 illustrates an exemplary voltage reading mechanism using pilot cells in accordance with an aspect of the present invention.

Figure 10 shows a plurality of cell arrays having a plurality of columns and rows of memory cells in one block. The memory cells shown in Figure 10 are connected to each other within a particular array configuration. The array configuration of such memory cells is exemplary and other types of memory cells or other array configurations may also be included within the scope of the present invention.

As described above, the value stored (or written) in the memory cell can be read by measuring the threshold voltage Vt of the cell. This read threshold voltage may indicate the amount of charge stored in the memory cell.

As shown in FIG. 10, for example, one page may include four pilot cells 1401 and 32768 data cells 1402. Each memory cell includes a floating gate transistor. The pilot cells 1401 and data cells 1402 (i.e., the gates of the transistors of the cells) in this single page share the same word line. Also, the sources of the transistors in each column can be connected to each other by bit lines. In the case of NOR cells, the sources can be connected directly to the bit lines, and in the case of NAND cells, the bit lines can be connected to the string of floating gates.

Since the case of MLC is taken as an example in Fig. 10, there may be four different nominal values. These four different nominal values may be used for recording in pilot cells A, B, C and D, respectively.

In an aspect of the present invention, the exemplary data block may further include a switch 1403 and / or a page buffer 1404. [ Such a switch 1403 may be placed in the path from the drains of the pilot cells to the sources of the data cells.

A target page to read can be determined in response to a data read request. The step voltage may be applied to the target page to be read. The memory controller 201 or the read module 205 can read the threshold voltage Vt of a specific memory cell by applying this step voltage to the gate of the cell (i.e., the word line to which the cell is connected). This may be implemented by checking whether the drain current of a particular cell exceeds the threshold voltage Vt. That is, the memory controller 201 or the read module 205 can determine the minimum gate voltage value at which the drain current exceeds the threshold voltage Vt by applying the step voltage to the word line to which the specific cell is connected.

10, the memory controller 201 or the read module 205 may apply a step voltage to the word line of the target page to measure the read threshold voltage value of the pilot cells 1401 in the target page. That is, when the threshold voltage Vt corresponding to the pilot cell (for example, the pilot cell A) in the target page is exceeded, the switch 1403 is closed and current can flow to the data cell 1402 in the page.

11 illustrates an exemplary data cell readout scheme using a switch in accordance with an aspect of the present invention.

The step voltage may be input to the word line for the target page by the memory controller 201 or read module 205, as shown in Fig. When the step voltage passes the threshold voltage Vt corresponding to the pilot cell A, the switch to the control gate can be driven. Thereby, current flows through the bit lines of the data cells, and the data cells can be read according to the adaptive threshold voltage value determined by the pilot cell A.

The pilot cells B, C, and D may also be implemented in the same manner as the pilot cell A scheme through different threshold voltage values at different timings in sequence.

Figure 12 illustrates an exemplary data cell readout scheme using a switch in accordance with an aspect of the present invention.

As shown in Figure 12, the drain voltage of the pilot cell may be directly connected to the data cell by a switch connecting the word line to the data cell. According to an aspect of the invention, when the step voltage passes a threshold voltage (Vt) corresponding to pilot cell A, the switch does not cause current to flow to the control gate, Can be made to flow directly. Thus, changes in nominal values can also be automatically reflected in the data cell.

According to the above-described schemes, a change in the threshold voltage values can be reflected directly to the data cells through the pilot cells. These adaptive implementations do not require additional computation on existing mechanisms.

In a further aspect of the invention, the pilot cells may be grouped and used in order to provide additional robustness of data reading for the data cell. That is, a plurality of pilot cells may be used for each nominal value. A group of such pilot cells may be commonly used for one data block or one page.

13 illustrates an exemplary change in threshold voltage after data programming.

In the case where the threshold voltage level for the data cell is determined by referring to the pilot cells in advance, an appropriate threshold voltage value can be found without grasping the response characteristic of each cell even if the voltage level is changed after programming of the data. That is, when pilot cells are used, more robust threshold voltage values can be generated without wasting storage space.

As shown in Fig. 13, the level distribution of the threshold voltage values at the programming time can change over time as shown in Fig. 13 (a) to Fig. 13 (b). However, the technique according to an aspect of the present invention can find the optimal threshold voltage value for the data cell through the value of the voltage read in the pilot cell, despite the change of these threshold voltage values. That is, according to one aspect of the present invention, the probability of a read error of a data cell due to a change in these threshold voltage values can be reduced.

14 is a flowchart showing a data processing method of a memory according to an aspect of the present invention. It will be apparent to those skilled in the art that additional steps other than those shown in FIG. 14 may be included in the method, and that some of the steps may be omitted.

As shown in Fig. 14, the memory controller programs the data by applying a voltage of a predetermined nominal value to a pilot cell at a predetermined position in the memory (S310). According to an aspect of the invention, the pilot cell is located in the same block or page as the data cell. Also, the pilot cell corresponds to at least one nominal value used for programming the memory, respectively. According to an aspect of the invention, a pilot cell includes a plurality of cells each corresponding to a plurality of nominal values used in memory programming.

Next, the memory controller reads the recorded voltage value of the pilot cell (S320). At this time, the memory controller can read the voltage value of the pilot cell at a higher resolution than the voltage step between each data for programming. For example, if the nominal value of each data for programming has a voltage step of 1V, the memory controller can read the voltage value of the pilot cell at a resolution of 0.2V, which is higher than the 1V interval.

Next, the memory controller corrects the nominal value corresponding to the data of the pilot cell based on the read-out voltage value of the pilot cell (S330). At this time, the memory controller may calculate the difference value between the voltage value of the read-out pilot cell and the predetermined nominal value, and add the calculated difference value to the predetermined nominal value to obtain the corrected nominal value. According to another aspect of the present invention, a memory controller calculates a ratio between the voltage value of the read-out pilot cell and a predetermined nominal value, scales the predetermined nominal value based on the calculated ratio, Can be obtained.

The memory controller programs the data in the data cells of the memory using the calibrated nominal value (S340).

According to an aspect of the present invention, the memory controller can obtain the number of deletion times of the block in which the pilot cell is located or the number of times of recording of the page. The memory controller may shift the position of the pilot cell based on the deletion count information or the write count information.

15 is a flowchart showing a data processing method of a memory according to another aspect of the present invention. It will be apparent to those skilled in the art that additional steps other than those shown in FIG. 15 may be included in the method, and that some of the steps may be omitted.

As shown in Fig. 15, the memory controller programs the data in the pilot cell and the data cell in the memory using a voltage of a predetermined nominal value (S410). As described above, the pilot cell refers to a cell at a predetermined position corresponding to at least one nominal value used for programming the memory, respectively. According to an aspect of the invention, the pilot cell may comprise a plurality of cells each corresponding to a plurality of nominal values used in memory programming. The pilot cell may be located in the same block or the same page as the data cell.

Next, the memory controller reads the recorded voltage value of the pilot cell (S420). At this time, the memory controller can read the voltage value of the pilot cell at a higher resolution than the voltage step between each data for programming.

Next, the memory controller sets a threshold voltage value for reading the data cell with reference to the voltage value of the read pilot cell (S430). The threshold voltage value is used as a read voltage of the data cell. According to an aspect, the threshold voltage value may be set to a value lower than the voltage value of the read pilot cell. According to an aspect of the present invention, a memory controller further includes a memory controller that obtains a read voltage value of a plurality of pilot cells programmed using the same nominal value in the memory, and based on an average of the read voltage values of the obtained plurality of pilot cells The threshold voltage value can be set.

The memory controller reads the data of the data cell of the memory based on the set threshold voltage value (S440).

According to an aspect of the present invention, the memory controller can obtain the number of deletion times of the block in which the pilot cell is located or the number of times of recording of the page. The memory controller may shift the position of the pilot cell based on the deletion count information or the write count information.

Those skilled in the art will appreciate that the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be embodied directly in electronic hardware, (Which may be referred to herein as "software") or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the design constraints imposed on the particular application and the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The various embodiments presented herein may be implemented as a method, apparatus, or article of manufacture using standard programming and / or engineering techniques. The term "article of manufacture" includes a computer program, carrier, or media accessible from any computer-readable device. For example, the computer-readable medium can be a magnetic storage device (e.g., a hard disk, a floppy disk, a magnetic strip, etc.), an optical disk (e.g., CD, DVD, etc.), a smart card, But are not limited to, devices (e. G., EEPROM, cards, sticks, key drives, etc.). The various storage media presented herein also include one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" includes, but is not limited to, a wireless channel and various other media capable of storing, holding, and / or transferring instruction (s) and / or data.

It will be appreciated that the particular order or hierarchy of steps in the presented processes is an example of exemplary approaches. It will be appreciated that, based on design priorities, certain orders or hierarchies of steps in processes may be rearranged within the scope of the present invention. The appended method claims provide elements of the various steps in a sample order, but are not meant to be limited to the specific order or hierarchy presented.

The description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features presented herein.

200: Memory system
201: Memory controller
202: flash memory

Claims (7)

A method of processing data in a memory,
Programming data in a pilot cell and a data cell in the memory using a voltage of a predetermined nominal value;
Reading a recorded voltage value of the pilot cell;
Setting a threshold voltage value for reading the data cell with reference to a voltage value of the read pilot cell; And
Reading data of a data cell of the memory based on the set threshold voltage value;
≪ / RTI >
Wherein the pilot cell is a cell at a predetermined location corresponding to at least one nominal value used in programming the memory,
A method for processing data in a memory. The method according to claim 1,
Wherein said reading comprises:
And reading the voltage value of the pilot cell at a resolution higher than a voltage step between each data for programming,
A method for processing data in a memory. The method according to claim 1,
Wherein the pilot cell is located in the same block or page as the data cell.
A method for processing data in a memory. The method of claim 3,
Obtaining a number of times of deletion of a block in which the pilot cell is located or a number of times of recording of a page; And
And shifting the pilot cell based on the deletion count information or the write count information
A method for processing data in a memory. The method according to claim 1,
Wherein the pilot cell comprises a plurality of cells each corresponding to a plurality of nominal values used in programming of the memory,
A method for processing data in a memory. The method according to claim 1,
Wherein the step of setting the threshold voltage value comprises:
And obtaining a read voltage value of a plurality of pilot cells programmed using the same nominal value in the memory,
And setting the threshold voltage value based on an average of read voltage values of the obtained plurality of pilot cells,
A method for processing data in a memory. A memory system,
A memory having a plurality of physical blocks, each of the plurality of physical blocks including a plurality of pages; And
And a memory controller configured to control the memory,
Wherein the memory controller includes a programming module for writing / erasing data in the memory, a reading module for reading data recorded in the memory, and a control module for controlling the programming module and the reading module,
Wherein the programming module programs data into a pilot cell and a data cell in the memory using a voltage of a predetermined nominal value, wherein the pilot cell comprises a pre-determined pre-memory value corresponding to at least one nominal value A cell at a determined position,
The read module reads the recorded voltage value of the pilot cell,
The control module sets a threshold voltage value for reading the data cell with reference to the voltage value of the read pilot cell,
The read module reads data of a data cell of the memory based on the set threshold voltage value,
Memory system.
KR1020140106933A 2014-08-18 2014-08-18 A memory system and a method for processing data in a memory KR20160021549A (en)

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