KR20160016462A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

According to the present invention, a semiconductor package comprises: a lower substrate; a first electronic device attached to one region on the lower substrate; a second electronic device attached to the other region on the lower substrate; and an upper substrate attached to the lower substrate in a way that the first electronic device is accommodated through a first cavity having an opened upper end, and the second electronic device is accommodated through a second cavity having an opened upper end. Therefore, the semiconductor package simplifies manufacturing processes and lowers costs.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor package,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package suitable for fabricating various semiconductor chips such as an LED die and an active element in a cavity region as a single package, and a manufacturing method thereof.

As is well known, portable devices such as cell phones, smart phones, smart pads, etc. may have semiconductor devices that are physically located close proximity to one another. For example, when an LED die and a photodiode are to be fabricated as a single semiconductor package, it is necessary to optically separate (isolate) between the two elements.

For this purpose, conventionally, two cavities are formed on a ceramic substrate, an LED die is attached to one cavity, a photodiode is attached to another cavity, and a metal lead is attached to the cavity. Respectively.

However, the conventional semiconductor package has a disadvantage that it is difficult to manufacture due to the characteristics of the ceramic substrate and that it is difficult to reduce the cost, and also that a signal line (for example, a via) can not be formed in the metal lead.

Korean Laid-Open Patent Application No. 2013-00122263 (Published on March 11, 2013)

The present invention proposes a new semiconductor package and a manufacturing method thereof that can simplify fabrication and reduce cost by providing a semiconductor package that optically isolates two electronic devices using a multilayer substrate structure having a cavity.

The problems to be solved by the present invention are not limited to those mentioned above, and another problem to be solved by the present invention can be clearly understood by those skilled in the art from the following description will be.

According to one aspect of the present invention, there is provided an electronic device comprising a lower substrate, a first electronic element attached to one side region of the lower substrate, a second electronic element attached to the other side region of the lower substrate, And an upper substrate bonded to the lower substrate in such a manner that the first electronic device is received through the first cavity and the second electronic device is received through a second open cavity of the upper cavity.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: attaching a first electronic device and a second electronic device to one side region and another side region of a lower substrate; The method comprising the steps of: preparing an upper substrate having an open-ended second cavity for accommodating the second electronic element; applying an adhesive to the adhesive region of the lower substrate; And bonding the upper substrate to the bonding region by aligning the second electronic element to be housed in the first cavity and the second electronic element to be housed in the second cavity.

According to a still further aspect of the present invention, there is provided a semiconductor device comprising a lower substrate, a lower storage substrate formed with a first cavity for receiving the first electronic element and bonded on the lower substrate, and a first electronic element An intermediate substrate adhered on the lower accommodating substrate in a form housed in the first cavity, a second electronic element attached to the upper portion of the intermediate substrate, and a second electronic element accommodated in the second cavity through the second cavity An upper storage substrate adhered on the intermediate substrate, and an upper substrate bonded on the upper storage substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a lower storage substrate having a first cavity having both open ends for housing a first electronic device; Preparing a one-layer structure by aligning the first electronic elements so as to be housed in the first cavity and adhering the intermediate substrate to the lower housing substrate to form a one-layer structure; A process of attaching a second electronic device to an upper portion of the intermediate substrate, a process of preparing an upper storage substrate having a second cavity of both ends open for accommodating a second electronic device, A step of attaching an upper substrate to an upper part of the upper housing substrate to form a two-layer structure, a step of positioning the second electronic element in the second cavity, And bonding the two-layer structure to the intermediate substrate by aligning the two-layer structure.

According to another aspect of the present invention, there is provided an electronic device comprising: a lower housing substrate on which a first cavity for housing a first electronic device is formed; and a second housing on which the first electronic device is mounted, A second substrate, a second substrate, a second substrate, a second substrate, a second substrate, a second substrate, and a second substrate, And an upper substrate bonded on the upper storage substrate, wherein the upper storage substrate is bonded to the lower substrate in a form of isolating and storing the third electronic device.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a lower receiving substrate having a first cavity of both open ends for receiving a first electronic device; Aligning the first electronic device so that the first electronic device is housed in the first cavity and adhering the lower housing substrate on the lower substrate to manufacture a one-layer structure; A step of attaching an electronic element and a third electronic element to each other; forming a second cavity of both ends for accommodating the second electronic element and a second cavity of both end openings for accommodating the third electronic element in an isolated form Preparing an upper storage substrate; bonding a top substrate to an upper portion of the upper storage substrate to manufacture a two-layer structure; It is received in the second cavity group and the third electronic component to the alignment position to be received in the third cavity is provided a method of manufacturing a semiconductor package comprising the step of bonding the second layered structure on the lower substrate.

By optically isolating the two electronic devices using a multi-layer substrate structure having cavities, the present invention can simplify the fabrication process of the semiconductor package and realize the cost reduction of the semiconductor package.

Further, according to the present invention, by forming a via in the side wall of the cavity, not only the functional reliability of the semiconductor package can be improved but also the application expandability of the semiconductor package can be secured.

1A is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
1B is a cross-sectional view of a semiconductor package according to a modified embodiment of the first embodiment of the present invention.
FIGS. 2A to 2D are process flow diagrams illustrating a main process for fabricating a semiconductor package according to a first embodiment of the present invention.
3 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.
4A to 4G are process flow diagrams illustrating a main process of manufacturing a semiconductor package according to a second embodiment of the present invention.
5 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.
6A to 6F are process flowcharts showing a main process of manufacturing a semiconductor package according to a third embodiment of the present invention.

First, the advantages and features of the present invention, and how to accomplish them, will be clarified with reference to the embodiments to be described in detail with reference to the accompanying drawings. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. It is to be understood that the following terms are defined in consideration of the functions of the present invention, and may be changed according to intentions or customs of a user, an operator, and the like. Therefore, the definition should be based on the technical idea described throughout this specification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Example 1]

1A is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

1A, the semiconductor package of this embodiment is a package device applicable to a portable device (portable terminal) such as a mobile phone, a smart phone, a smart pad, etc., and includes a lower substrate 102 and an upper substrate 110 . ≪ / RTI > Here, each of the substrates may mean, for example, a PCB substrate.

A first electronic element 104 is attached to one side of the lower substrate 102 and a second electronic element 106 is attached to the other side of the lower substrate 102. The electrode pads of each electronic element and the lower substrate 102 May be physically (electrically) connected through a conductive wire. Here, the first electronic element 104 may be an optical element such as an LED, and the second electronic element 106 may be an element such as a pressure sensor, a gyro sensor, an acceleration sensor, a photodiode,

The upper substrate 110 is bonded to the lower substrate 102 through the adhesive 108. The first cavity 111a and the second electronic device 106, which accommodate the first electronic device 104, A second cavity 111b having a top opening shape is received. Here, as the adhesive 108, for example, a solder paste, an epoxy paste or the like may be used.

Here, the first and second cavities 111a and 111b formed in an isolated form on the upper substrate 110 may be formed through a drilling process using a laser, or may be formed through a drilling process using a router.

Vias 112 for electrically connecting the lower part and the upper part are formed on the sidewalls of the upper substrate 110, that is, the side walls of the first and second cavities 111a and 111b, An electrode array such as a land grid array (LGA) 114 connected to the vias 112 is formed. Here, the LGA 114 can function as an I / O for connection with a main substrate (not shown).

Although the lower substrate 102 and the upper substrate 110 are both a PCB substrate in the present embodiment, the present invention is not limited thereto. Only the lower substrate 102 may be a PCB substrate, It goes without saying that the substrate 110 may be applied as a ceramic substrate.

1B is a cross-sectional view of a semiconductor package according to a modified embodiment of the first embodiment of the present invention.

Referring to FIG. 1B, the semiconductor package of the present modified embodiment differs from the embodiment of FIG. 1A in that an LGA is formed on an upper substrate 110, and a glass substrate (not shown) is formed on the upper substrate 110 without forming an LGA 116) are adhered to each other.

That is, the semiconductor package of this modified embodiment is substantially the same as the corresponding structures shown in Fig. 1A except for the structure in which the glass substrate 116 is adhered on the upper substrate 110. [

1A, both the lower substrate 102 and the upper substrate 110 may be formed as a PCB substrate, or only the lower substrate 102 may be a PCB substrate, as in the embodiment shown in FIG. 1A, And the upper substrate 110 may be used as a ceramic substrate.

In the embodiments of FIGS. 1A and 1B, the electronic devices are mounted on the lower substrate by wire bonding. However, the present invention is not limited thereto. It goes without saying that it may be applied.

Next, a series of processes for fabricating the semiconductor package according to the present embodiment having the above-described structure will be described in detail.

FIGS. 2A to 2D are process flow diagrams illustrating a main process for fabricating a semiconductor package according to a first embodiment of the present invention.

2A, a lower substrate 102 on which a substrate pad and conductive lines are formed is prepared, and a die attach process, a wire bonding process, and the like are performed to form a first The electronic device 104 is attached and the second electronic device 106 is attached to the other area.

The first cavity 111a for accommodating the first electronic element 104 attached to one side region of the lower substrate 102 and the second cavity 111b attached to the other side region of the lower substrate 102 And a second cavity 111b having an open end for accommodating the first cavity 111 and the second cavity 111. Here, the both-end opening type means that the first and second cavities 111a and 111b are opened in such a manner as to penetrate the upper and lower portions of the upper substrate 110.

The adhesive 108 is applied to each of the bonding areas of the lower substrate 102 by applying the adhesive 108, for example, an adhesive 108 such as solder paste, epoxy paste or the like is applied. Here, the adhesive 108 can be selectively applied only to a desired position through a screen printing process or the like.

Subsequently, the first electronic element 104 is housed in the first cavity 111a, the second electronic element 106 is positioned so as to be housed in the second cavity 111b, and then the substrate adhering step is performed, As shown in FIG. 2B, the upper substrate 110 is bonded to the upper portion of the lower substrate 102.

Then, the LGA 114, that is, the LGA 114 connected to the vias 112 is formed on the upper substrate 110, for example, as shown in FIG. 2C. Here, the LGA 114 can function as an I / O for connection to a main substrate (not shown), and the semiconductor package is adhered to the main substrate through the LGA 114, so that two electronic elements, Can be protected from external exposure.

Meanwhile, in the semiconductor package manufacturing method of the present embodiment, the glass substrate may be bonded without forming an LGA on the upper substrate 110. That is, the substrate adhering step may be performed, for example, as shown in FIG. 2D, and the glass substrate 116 may be bonded to the upper substrate 110.

[Example 2]

3 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

3, the semiconductor package of this embodiment is a package device applicable to a portable device (portable terminal) such as a cell phone, a smart phone, a smart pad, etc., and includes a lower substrate 302 vertically and sequentially stacked, A storage substrate 306, an intermediate substrate 310, an upper storage substrate 318, an upper substrate 322, and the like. Here, each of the substrates may mean, for example, a PCB substrate.

A first cavity 307 formed in the lower housing substrate 306 and a first hole 304 for venting the outside are formed on one side of the lower substrate 302. The first hole 304 is formed in a 1 can function as an acoustic hole or as a vent hole depending on the type of the first electronic device 312 housed in the cavity 307. [

A first cavity 307 for accommodating the first electronic device 312 is formed on a lower storage substrate 306 bonded to the lower substrate 302 through an adhesive (not shown) (308) for electrically connecting the lower part and the upper part of the lower housing substrate (306) are formed on the side wall of the lower housing part (307).

Here, the first cavity 307 formed in the lower housing substrate 306 may be formed through a drilling process using a laser, or may be formed through a drilling process using a router.

A first electronic device 312 (see FIG. 3), which is housed in a first cavity 307 formed on a lower storage substrate 306, is provided below the intermediate substrate 310 bonded to the lower storage substrate 306 through an adhesive (not shown) And a second electronic device 314 and a third electronic device 316 are attached to the upper portion of the intermediate substrate 310 so as to be housed together in the second cavity 319. Here, the first electronic component 312 may be, for example, an ASIC die, and the second and third electronic components 314 and 316 may be, for example, various sensors (e.g., LED, pressure sensor, gyro sensor, Sensor, etc.).

Here, it is described that one electronic device is housed in the first cavity 307 and two electronic devices are housed in the second cavity 319. However, this is only an illustrative example, And it is needless to say that the number of the electronic elements housed in the first cavity and the second cavity can be changed to one or more depending on necessity or use.

A second cavity 319 for accommodating the second and third electronic elements 314 and 316 is formed on the upper housing substrate 318 adhered on the intermediate substrate 310 through an adhesive (not shown) And vias 320 for electrically connecting the lower portion and the upper portion of the upper storage substrate 318 are formed on the side walls of the second cavity 319. [

Here, the second cavity 319 formed on the upper storage substrate 318 may be formed through a drilling process using, for example, a laser or through a drilling process using a router.

An upper substrate 322 is bonded on the upper storage substrate 318. A second cavity 319 formed on the upper storage substrate 318 and a second cavity The second hole 324 functions as an acoustic hole depending on the type of the second and the third electronic elements 314 and 316 housed in the second cavity 319. Alternatively, Function.

In the meantime, in the present embodiment, all vertically stacked substrates are described as a PCB substrate, but the present embodiment is not limited thereto. Only the lower substrate, the intermediate substrate, and the upper substrate may be formed as a PCB substrate, It goes without saying that the upper storage substrate may be applied as a ceramic substrate.

Next, a series of processes for fabricating the semiconductor package according to the present embodiment having the above-described structure will be described in detail.

4A to 4G are process flow diagrams illustrating a main process of manufacturing a semiconductor package according to a second embodiment of the present invention.

Referring to FIG. 4A, a lower substrate 302 having a substrate pad, a conductive line, and the like formed therein and having a first hole 304 is prepared, and a first electronic device 312 And a lower receiving substrate 306 having vias 308 formed on the sidewalls of the first cavity 307. The first cavity 307 and the second cavity 307 are formed on the bottom surface of the first cavity 307 and the first cavity 307, respectively. Here, the both-end opening type means that the first cavity 307 is opened through the upper and lower portions of the lower receiving substrate 306.

Again, an intermediate substrate 310 is attached to the bottom of the first electronic component 312 via a conductive bump or the like.

Next, the first electronic element 312 attached to the lower portion of the intermediate substrate 310 is aligned at a target position so as to be housed in the first cavity 307 of the lower housing substrate 306, and then an adhesive (for example, solder paste, epoxy Paste, or the like), a single-layer structure having a shape in which the intermediate substrate 310 is adhered to the lower storage substrate 306 is fabricated as shown in FIG. 4B as an example.

The one-layer structure including the lower storage substrate 306 and the intermediate substrate 310 is aligned with the target position of the lower substrate 302 and then an adhesion process using an adhesive (for example, solder paste, epoxy paste, etc.) Thereby bonding a single-layer structure on the lower substrate 302, as shown in Fig. 4C as an example.

4D, a second electronic device 314 and a third electronic device 316 are disposed at predetermined positions on the intermediate substrate 310, for example, by performing a die attaching process using a conductive bump or the like Respectively.

4E, a second cavity 319 and a second cavity 319 both of which are open at both ends for accommodating a second electronic element 314 and a third electronic element 316 attached on the intermediate substrate 310, And a second hole 324 formed on one side of the upper substrate 322. The upper substrate 322 is provided with a substrate pads and conductive lines or the like on the upper storage substrate 318 having the vias 320 formed on the side walls thereof. Here, the term " both-end open type " means that the second cavity 319 is opened in such a manner as to pass through the upper and lower portions of the upper storage board 318. [

Subsequently, the upper substrate 322 is aligned with the target position of the upper housing substrate 318, and an adhering step using an adhesive (for example, solder paste, epoxy paste, or the like) is performed. As shown in FIG. 4F , A two-layer structure in which the upper substrate 322 is adhered to the upper housing substrate 318 is fabricated.

The second and third electronic elements 314 and 316 attached to the upper portion of the intermediate substrate 310 are aligned at a target position so as to be accommodated in the second cavity 319 of the upper housing substrate 318, , Solder paste, epoxy paste, or the like) is performed to complete the package fabrication by bonding the two-layer structure on the intermediate substrate 310 as shown in Fig. 4G as an example.

[Example 3]

5 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

5, the semiconductor package of this embodiment is a package device applicable to a portable device (portable terminal) such as a mobile phone, a smart phone, a smart pad, etc., and includes a lower storage board 502 stacked vertically and sequentially, A lower substrate 508, an upper storage substrate 516, an upper substrate 520, and the like. Here, each of the substrates may mean, for example, a PCB substrate.

A first cavity 503 for accommodating a first electronic device 510 is formed on a lower storage substrate 502. A lower cavity 503 is formed on a side wall of the first cavity 503, Vias 504 for electrically connecting the liver are formed.

Here, the first cavity 503 formed in the lower housing substrate 502 may be formed through a drilling process using, for example, a laser or through a drilling process using a router.

Further, electrode arrays such as an LGA 506 connected to the vias 504 are formed below the lower housing substrate 502. Here, the LGA 506 can function as an I / O for connection with a main substrate (not shown).

A first electronic device 510 (see FIG. 5), which is housed in a first cavity 503 formed on the lower housing substrate 502, is mounted on a lower portion of the lower substrate 508 to be bonded onto the lower housing substrate 502 through an adhesive (not shown) A second electronic device 512 accommodated in the second cavity 517a and a third electronic device 514 accommodated in the third cavity 517b are attached to the upper portion of the lower substrate 508, . Here, the first electronic element 510 may be, for example, an ASIC die, and the second and third electronic elements 512 and 514 may be, for example, various sensors (e.g., LED, pressure sensor, gyro sensor, Sensor, etc.).

Here, it is described that only one electronic element is housed in each cavity. However, this is only an exemplary illustration, and the present embodiment is not necessarily limited to this. The number of electronic elements housed in each cavity may be one The present invention is not limited thereto.

A second cavity 517a and a third electronic device 514 for accommodating the second electronic device 512 are formed on the upper housing substrate 516 bonded to the lower substrate 508 through an adhesive (not shown) And a third cavity 517b for accommodating the upper and lower cavities 517a and 517b is formed in an isolated shape on the side walls of the second and third cavities 517a and 517b. (518) are formed.

Here, the second and second cavities 517a and 517b formed on the upper housing substrate 516 can be formed through a drilling process using, for example, a laser or through a drilling process using a router.

An upper substrate 520 is adhered on the upper storage substrate 516. A second cavity 517a formed on the upper storage substrate 516 and a second hole And a third cavity 517b formed on the upper storage substrate 516 and a third hole 524 formed on the other side of the upper substrate 520 for ventilation. Each of the second and third holes 522 and 524 may function as an acoustic hole or as a vent hole depending on the type of the second and the second electronic elements 512 and 514 housed in corresponding cavities .

However, the present invention is not limited thereto. Only the lower substrate and the upper substrate may be used as the PCB substrate, and the lower and upper storage substrates may be used as the PCB substrate, May be applied as a ceramic substrate.

Next, a series of processes for fabricating the semiconductor package according to the present embodiment having the above-described structure will be described in detail.

6A to 6F are process flowcharts showing a main process of manufacturing a semiconductor package according to a third embodiment of the present invention.

6A, a first cavity 503 having both ends open to receive a first electronic device 510 to be attached to a lower portion of the lower substrate 508, a via 504 on a side wall of the first cavity 503, And a lower receiving substrate 502 having an LGA 506 formed on the lower side thereof is prepared. Here, the term " both-end open type " means that the first cavity 503 is opened in such a manner as to pass through the upper and lower portions of the lower storage substrate 502.

Again, a lower substrate 508 is attached to the lower portion of the first electronic element 510 via a conductive bump or the like.

Next, a first electronic element 510 attached to a lower portion of the lower substrate 508 is aligned at a target position so as to be housed in a first cavity 503 of the lower housing substrate 502, and then an adhesive (e.g., solder paste, Epoxy paste, or the like), a single-layer structure having a shape in which the lower substrate 508 is bonded onto the lower storage substrate 502 is fabricated as shown in Fig. 6B as an example.

6C, a second electronic element 512 and a third electronic element 514 (see FIG. 6C) are formed on one side and the other side of the lower substrate 508, respectively, by performing a die attaching process using a conductive bump or the like, Respectively.

6D, second and third openings 517a and 517b for isolating and accommodating the second electronic device 512 and the third electronic device 514 attached to the lower substrate 508, respectively, An upper storage substrate 516 having vias 518 formed on the respective side walls of the first and second cavities 517a and 517b is prepared and a second hole 522 is formed on one side thereof with a substrate pad, And a third hole 524 is formed on the other side of the upper substrate 520. Here, the both-end opening type means that the second and third cavities 517a and 517b are opened in such a manner as to penetrate the upper and lower portions of the upper storage board 516. [

Subsequently, the upper substrate 520 is aligned with the target position of the upper housing substrate 516, and an adhering process using an adhesive (for example, solder paste, epoxy paste or the like) is performed. As a result, as shown in FIG. 6E , A two-layer structure in which the upper substrate 520 is adhered to the upper housing substrate 516 is fabricated.

Next, a second electronic element 512 attached to the upper portion of the lower substrate 508 is housed in the second cavity 517a of the upper housing substrate 516, and a third electronic element 514 is housed in the upper housing substrate 6F, an adhesion process using an adhesive (for example, solder paste, epoxy paste or the like) is performed after aligning the first cavity 517a and the second cavity 516b at the target position so as to be housed in the third cavity 517b of the lower substrate 516. [ And the two-layer structure is adhered onto the second substrate 508 to complete the package production.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is easy to see that this is possible. That is, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the present invention.

Therefore, the scope of protection of the present invention should be construed in accordance with the following claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

Claims (28)

A lower substrate,
A first electronic element attached to one side region of the lower substrate,
A second electronic element attached to the other region on the lower substrate,
The first electronic device is received through a first cavity of a top open type and the second electronic device is received through a second cavity of a top open type,
≪ / RTI >
The method according to claim 1,
Wherein one of the first electronic element and the second electronic element comprises:
Photon
Semiconductor package.
The method according to claim 1,
Wherein the lower substrate and the upper substrate, respectively,
PCB substrate
Semiconductor package.
The method according to claim 1,
Wherein the lower substrate is a PCB substrate,
The upper substrate is a ceramic substrate
Semiconductor package.
The method according to claim 1,
Wherein the upper substrate comprises:
Wherein vias are formed in the respective side walls of the first and second cavities
Semiconductor package.
6. The method of claim 5,
Wherein the upper substrate comprises:
And a land grid array (LGA) connected to the vias is formed at an upper portion thereof
Semiconductor package.
6. The method of claim 5,
The package includes:
A glass substrate adhered on the upper substrate
Further comprising:
Attaching a first electronic device and a second electronic device to one side region and the other side region of the lower substrate,
The method comprising the steps of: preparing an upper substrate in which a first cavity having both ends open to receive the first electronic device and a second cavity having both open ends to receive the second electronic device are formed in an isolated form;
Applying an adhesive to an adhesion area of the lower substrate;
A step of bonding the upper substrate to the bonding region by aligning the first electronic element in the first cavity and the second electronic element in the second cavity,
≪ / RTI >
9. The method of claim 8,
Wherein the upper substrate comprises:
A via is formed in each side wall of the first and second cavities,
The method comprises:
A process of forming a land grid array (LGA) functioning as an I / O for connection with the main substrate and connected to the vias on the upper substrate
≪ / RTI >
9. The method of claim 8,
Wherein the upper substrate comprises:
A via is formed in each side wall of the first and second cavities,
The method comprises:
A process of bonding a glass substrate onto the upper substrate
≪ / RTI >
9. The method of claim 8,
Preferably,
Solder paste in
A method of manufacturing a semiconductor package.
9. The method of claim 8,
Preferably,
Epoxy paste
A method of manufacturing a semiconductor package.
A lower substrate,
A lower storage board formed with a first cavity for receiving a first electronic element and bonded on the lower substrate,
An intermediate substrate adhered on the lower storage substrate in a manner that the first electronic device is attached to the lower part and is housed in the first cavity;
A second electronic element attached to the upper portion of the intermediate substrate,
An upper storage board adhered to the intermediate board in a form of receiving the second electronic element through a second cavity,
The upper substrate
≪ / RTI >
14. The method of claim 13,
Wherein the lower substrate comprises:
A hole for venting between the first cavity and the outside is formed
Semiconductor package.
14. The method of claim 13,
Wherein the upper substrate comprises:
A hole for ventilation between the second cavity and the outside is formed
Semiconductor package.
16. The method according to claim 14 or 15,
The hole
Acoustic or ventilated
Semiconductor package.
14. The method of claim 13,
Wherein the lower storage board and the upper storage board are made of an insulating material,
Wherein vias are formed in the respective side walls of the first and second cavities
Semiconductor package.
14. The method of claim 13,
Wherein the lower substrate, the lower storage substrate, the intermediate substrate, the upper storage substrate,
PCB substrate
Semiconductor package.
14. The method of claim 13,
Wherein the lower substrate, the intermediate substrate, and the upper substrate are PCB substrates,
The lower storage board and the upper storage board are made of a ceramic substrate
Semiconductor package.
Preparing a lower receiving substrate on which a first cavity having both open ends for receiving a first electronic device is formed;
Preparing an intermediate substrate to which the first electronic device is attached,
Aligning the first electronic device so that the first electronic device is accommodated in the first cavity and adhering the intermediate substrate to the lower housing substrate to manufacture a one-layer structure;
Bonding the prepared one-layer structure to a prepared lower substrate,
Attaching a second electronic device to an upper portion of the intermediate substrate,
Preparing an upper housing board having a second cavity of both open ends for housing a second electronic element,
Forming a two-layer structure by bonding an upper substrate to an upper portion of the upper storage substrate;
And positioning the second electronic component to be housed in the second cavity to bond the two-layer structure onto the intermediate substrate
≪ / RTI >
A lower housing substrate on which a first cavity for accommodating the first electronic element is formed,
A lower substrate adhered to the lower accommodating substrate in a manner that the first electronic device is attached to the lower portion and housed in the first cavity;
Second and third electronic elements respectively attached to the upper portion of the lower substrate,
An upper storage board adhered on the lower substrate in such a manner that the second electronic element is isolated and housed through a second cavity and the third electronic element is isolated and housed through a third cavity,
The upper substrate
≪ / RTI >
22. The method of claim 21,
Wherein the upper substrate comprises:
A first hole for ventilation between the second cavity and the outside and a second hole for ventilation between the third cavity and the outside are formed
Semiconductor package.
23. The method of claim 22,
Wherein the first and second holes
Acoustic or ventilated
Semiconductor package.
22. The method of claim 21,
Wherein the lower storage board and the upper storage board are made of an insulating material,
A via is formed in each side wall of the first, second and third cavities
Semiconductor package.
25. The method of claim 24,
Wherein the lower substrate comprises:
And a land grid array (LGA) connected to the vias, the I /
Semiconductor package.
22. The method of claim 21,
The lower storage substrate, the lower substrate, the upper storage substrate, and the upper substrate,
PCB substrate
Semiconductor package.
22. The method of claim 21,
Wherein the lower substrate and the upper substrate are PCB substrates,
The lower storage board and the upper storage board are made of a ceramic substrate
Semiconductor package.
Preparing a lower receiving substrate on which a first cavity having both open ends for receiving a first electronic device is formed;
Preparing a lower substrate to which the first electronic device is attached,
Aligning the first electronic device so that the first electronic device is accommodated in the first cavity and adhering the lower housing substrate on the lower substrate to manufacture a one-layer structure;
Attaching a second electronic device and a third electronic device to the upper portion of the lower substrate,
Preparing an upper storage board having a second cavity of both ends for storing the second electronic element and a second cavity of both open ends for storing the third electronic element in an isolated form;
Forming a two-layer structure by bonding an upper substrate to an upper portion of the upper storage substrate;
A step of bonding the two-layer structure to the lower substrate by aligning the second electronic element in the second cavity and the third electronic element in the third cavity
≪ / RTI >

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