KR20160016431A - Semiconducotr device, semiconductor package and metode for manufacturing thereof - Google Patents

Semiconducotr device, semiconductor package and metode for manufacturing thereof Download PDF

Info

Publication number
KR20160016431A
KR20160016431A KR1020140100586A KR20140100586A KR20160016431A KR 20160016431 A KR20160016431 A KR 20160016431A KR 1020140100586 A KR1020140100586 A KR 1020140100586A KR 20140100586 A KR20140100586 A KR 20140100586A KR 20160016431 A KR20160016431 A KR 20160016431A
Authority
KR
South Korea
Prior art keywords
passivation layer
die
semiconductor
conductive bump
passivation
Prior art date
Application number
KR1020140100586A
Other languages
Korean (ko)
Other versions
KR101683975B1 (en
Inventor
유지연
이재웅
김병진
이경연
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020140100586A priority Critical patent/KR101683975B1/en
Publication of KR20160016431A publication Critical patent/KR20160016431A/en
Application granted granted Critical
Publication of KR101683975B1 publication Critical patent/KR101683975B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a semiconductor device, a semiconductor package and a method for manufacturing thereof. According to an embodiment, disclosed is a semiconductor device, comprising: a semiconductor die including a first passivation layer and a plurality of die pads; a plurality of second passivation layers individually formed on an upper portion of the die pad; and a plurality of conductive bumps each of which penetrates through the second passivation layer, and is electrically connected to the die pad. According to the present invention, without changing the length of the conductive bumps, a part of the second passivation layer is omitted in various areas, an interval or space of the semiconductor die and the substrate may be relatively increased than before. As such, by additional space provided through the gap between the second passivation layer, the interval between the semiconductor die and the substrate and the space therebetween are sufficiently secured, and thus the particles consisting of underfill materials can be moved more freely between the semiconductor die and the substrate, thereby forming a more uniform underfill area.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, a semiconductor package, a semiconductor device, and a method of manufacturing a semiconductor package.

The present invention relates to a semiconductor device, a semiconductor package, a semiconductor device, and a method of manufacturing a semiconductor package.

In general, a semiconductor package includes a semiconductor die having a bonding pad formed thereon, a semiconductor substrate on which the semiconductor die is mounted, a conductive bump electrically connecting the semiconductor die and the substrate, A solder ball formed on a lower surface of the substrate, and an under-fill area filled between the semiconductor die and the substrate.

Generally, the underfill region is formed by filling a liquid material composed of a filler such as a resin, an inorganic material, and a curing agent, and then curing, and serves to compensate for different thermal expansion coefficients between the semiconductor die and the substrate.

When filling the liquid material for forming the underfill region, when the size of the particles constituting the filler is larger than the interval between the semiconductor die and the substrate, the particles do not penetrate deeply between the semiconductor die and the substrate, Can be formed non-uniformly.

In addition, when the length of the conductive bump is increased in consideration of the size of the particles constituting the filler, the gap between the semiconductor die and the substrate can be sufficiently secured, but the overall size of the semiconductor package may be increased.

The present invention provides a semiconductor device and a semiconductor package in which an underfill region can be uniformly formed while maintaining a minimized size.

A semiconductor device and a method of manufacturing the semiconductor package as described above are also provided.

A semiconductor device according to an embodiment of the present invention includes: a semiconductor die having a first passivation layer and a plurality of die pads; A plurality of second passivation layers respectively formed on top of the die pad; And a plurality of conductive bumps electrically connected to the die pad through the second passivation layer, respectively.

In addition, the second passivation layers may be spaced apart from each other.

In addition, an empty space may be formed between the adjacent second passivation layers so that a part of the first passivation layer may be exposed to the outside.

In addition, the second passivation layer may be formed to extend in the lateral direction with respect to the conductive bump by 1 to 50 m.

In addition, the conductive bump may include an under bump metal (UBM) electrically connected to the die pad through the second passivation layer; A metal filler formed on the UBM; And a solder cap formed on the upper portion of the metal pillar.

In addition, the conductive bump may include a solder ball.

A semiconductor package according to another embodiment of the present invention includes a first passivation layer, a plurality of die pads, a plurality of second passivation layers formed respectively below the die pads, A semiconductor device including a plurality of electrically conductive bumps, each electrically connected to the semiconductor device; A semiconductor substrate electrically connected to the semiconductor device through the conductive bump; And an underfill region filled between the semiconductor device and the semiconductor substrate.

In addition, the second passivation layers may be spaced apart from each other.

Further, the underfill region may be formed between the conductive bumps and between the second passivation layer.

The first passivation layer may also be in direct contact with the underfill region.

In addition, the second passivation layer may be formed to extend in the lateral direction with respect to the conductive bump by 1 to 50 m.

In addition, the conductive bump may include an under bump metal (UBM) electrically connected to the die pad through the second passivation layer; A metal filler formed on the UBM; And a solder cap formed on the upper portion of the metal pillar.

In addition, the conductive bump may include a solder ball.

A method of manufacturing a semiconductor device according to another embodiment of the present invention includes the steps of: providing a semiconductor die having a first passivation layer and a plurality of die pads; Forming a plurality of second passivation layers each located on top of the die pad; And forming a plurality of conductive bumps each electrically connected to the die pad through the second passivation layer, respectively.

The second passivation layers may be spaced apart from each other.

In addition, the second passivation layer may be formed to extend in the lateral direction of the conductive bump by 1 to 50 m on the basis of the conductive bump.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, including: providing a semiconductor die having a first passivation layer and a plurality of die pads; Forming a second passivation layer on top of the die pad, respectively; Forming a plurality of conductive bumps through each of the second passivation layers and electrically connected to the die pads, respectively; Electrically connecting the semiconductor die with the semiconductor substrate through the conductive bump; And forming an underfill region between the semiconductor die and the semiconductor substrate.

The second passivation layers may be spaced apart from each other.

In addition, the underfill region may be formed between the conductive bumps and between the second passivation layer.

In addition, the second passivation layer may be formed to extend in the lateral direction of the conductive bump by 1 to 50 m on the basis of the conductive bump.

According to the present invention, it is possible to provide a semiconductor device and a semiconductor package in which an underfill region can be uniformly formed while maintaining a minimized size.

Further, the semiconductor device and the method of manufacturing the semiconductor package as described above can be provided.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
3 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.
4A to 4I are views illustrating a manufacturing process of a semiconductor package according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention includes a semiconductor die 110, a plurality of second passivation layers 120, and a plurality of conductive bumps 130.

The semiconductor die 110 may include a plurality of die pads 111 and a first passivation layer 113.

The die pad 111 may be formed on one surface of the semiconductor die 110 and may be electrically connected to a re-wiring layer (not shown) formed in the semiconductor die 110. The die pad 111 may include any one selected from copper, aluminum, gold, silver, and the like.

The first passivation layer 113 may be formed on the surface of the semiconductor die 110 except for the area where the die pad 111 is formed and serves to protect the semiconductor die 110. The first passivation layer 113 may include an oxide, a nitride, or an organic film.

A plurality of second passivation layers 120 may be formed on top of each of the die pads 111. The second passivation layer 120 prevents unnecessary electrical contact with the semiconductor die 110 and the circuit board (not shown) on which the semiconductor die 110 is mounted and prevents the conductive bumps 130 from being held on the semiconductor die 110 . These second passivation layers 120 may be spaced apart from one another on the semiconductor die 110 at a distance. The first passivation layer 113 is exposed to portions of the upper surface of the semiconductor die 110 where the second passivation layer 120 is not formed, for example, between the adjacent second passivation layers 120 .

On the other hand, the second passivation layer 120 may be formed in a substantially disc shape, and may be formed to extend approximately 1 to 50 m in the lateral direction with respect to the UBM 131 of the conductive bump 130. However, since the pitch between the die pad 131 and the pad 131 is already determined, it is preferable to design the UBM 131 (see FIG. 3) rather than considering the maximum size of the area 120a in which the second passivation layer 120 is omitted. The second passivation layer 120 can protect the edge of the first passivation layer 120. [

The plurality of conductive bumps 130 may be electrically connected to the die pad 111 through the plurality of second passivation layers 120, respectively. The conductive bump 130 may include an under bump metal (UBM) 131, a metal filler 133, and a solder cap 135.

The UBM 131 may be electrically connected to the die pad 111 through the second passivation layer 120. The UBM 131 may be made of a material selected from the group consisting of chromium / chromium-copper alloy / copper (Cr / Cr-Cu / Cu), titanium / tungsten / copper (Ti- Cu) or an equivalent thereof, but the material thereof is not limited thereto.

The metal pillar 133 may be formed to have a predetermined height on the UBM 131. The metal filler 133 may include copper or tin, but is not limited thereto.

The solder cap 135 may be formed on the upper portion of the metal pillar 133. The solder cap 135 may be formed using an alloy such as tin (Sn), lead (Pb), silver (Ag), or the like, but the material thereof is not limited thereto.

The conductive bump 130 may include the UBM 131, the metal filler 133, and the solder cap 135 as described above, but may be formed in the form of a solder ball (not shown).

2 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

2, a semiconductor device includes a semiconductor die 210, a semiconductor device having a plurality of second passivation layers 220 and a plurality of conductive bumps 230, a semiconductor substrate 240, and an underfill region 250 do.

The semiconductor device according to another embodiment of the present invention is the same as that of the semiconductor device 100 described above. That is, the semiconductor die 210, the second passivation layer 220, and the conductive bump 230 of the semiconductor device shown in FIG. 2 may be formed using the semiconductor die 110 of the semiconductor device 100, Layer 120, and the conductive bump 130, respectively. Accordingly, the detailed description of the semiconductor device according to another embodiment of the present invention replaces the description of the semiconductor device 100 according to one embodiment.

The semiconductor substrate 240 may be a protection circuit board (PCB), and may include a bonding pad 241, a third passivation layer 243, and a plurality of solder balls 245. The bonding pad 241 may be electrically connected to the solder cap 235 of the semiconductor device. The third passivation layer 243 may be formed on the upper surface of the semiconductor substrate 240 excluding the bonding pads 241 to protect the semiconductor substrate 240. The solder ball 245 may be formed on the lower surface of the semiconductor substrate 240 and electrically connected to an external circuit device such as a main board.

The underfill region 250 may be formed by filling an underfill material composed of a filler such as a resin, an inorganic material, and a curing agent between the semiconductor die 210 and the substrate 240, followed by curing. The underfill region 250 may be formed in the empty space 220a between the adjacent second passivation layers 220, unlike the prior art.

Generally, the distance between the semiconductor die and the substrate or the size of the space may be varied by the second passivation layer. Conventionally, since the second passivation layer is formed over one entire surface of the first passivation layer, the distance between the semiconductor die and the substrate is entirely reduced by the thickness of the second passivation layer. If there are particles in the underfill material that are larger than the distance between the semiconductor die and the substrate, the particles can not move freely between the semiconductor die and the substrate, and the underfill region can be formed nonuniformly.

However, according to another embodiment of the present invention, a portion of the second passivation layer is omitted in various regions, without changing the length of the conductive bump, so that the space or space between the semiconductor die and the substrate can be relatively increased compared to the prior art. As such, the additional space provided between the second passivation layer and the layer ensures sufficient space between the semiconductor die and the substrate and the space therebetween, so that the particles of the underfill material can move more freely between the semiconductor die and the substrate , A more uniform underfill region can be formed.

3 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

Referring to FIG. 3, a method S300 of fabricating a semiconductor package according to another embodiment of the present invention includes a semiconductor die providing step S310, a second passivation layer forming step S320, a conductive bump forming step S330), connecting a semiconductor die and a semiconductor substrate (S340), and forming an underfill region (S350).

4A to 4I are views illustrating a manufacturing process of a semiconductor package according to another embodiment of the present invention.

In the semiconductor die providing step S310, a semiconductor die 410 provided with a plurality of die pads 411 and a first passivation layer 413, as shown in FIG. 4A, is provided.

Here, the die pad 411 may be formed on one surface of the semiconductor die 410 and may be electrically connected to a re-wiring layer (not shown) formed in the semiconductor die 410. The die pad 411 may include any one selected from copper, aluminum, gold, silver, and the like. The first passivation layer 413 may be formed on the surface of the semiconductor die 410 except for the region where the die pad 411 is formed and serves to protect the semiconductor die 410. The first passivation layer 413 may include an oxide, a nitride, or an organic film.

In the second passivation layer forming step S320, a second passivation material layer 420 'is formed on one side of the semiconductor die 410 as shown in FIG. 4B. Then, as shown in FIG. 4C, The second passivation layer 420 is formed by removing the second passivation material layer 420 'in an area except for the die pad 411. [

Meanwhile, the second passivation layer 420 may be formed in a substantially disc shape, and may be formed to extend approximately 1 to 50 m in the lateral direction with respect to the UBM 431 of the conductive bump 430 described later. However, since the pitch between the die pad 431 and the pad 431 is already determined, it is preferable to design the UBM in consideration of the maximum size of the region 420a in which the second passivation layer 420 is omitted, It is desirable to design the second passivation layer 420 considering the minimum size of the second passivation layer 420 that can protect the edge of the first passivation layer 431.

In the conductive bump forming step S330, first, the through holes 421 penetrating the second conductive bumps 420 are formed as shown in FIG. 4D, and then the inner walls of the through holes 421, And the UBM 431 is formed on the top surface of the die pad 411 exposed by the through hole 421. The UBM 431 is formed on the upper surface of the second passivation layer 420, The material of the UBM 431 may be selected from the group consisting of chromium / chromium-copper alloy / copper (Cr / Cr-Cu / Cu), titanium-tungsten alloy / copper / Cu), or their equivalents, but the material is not limited thereto.

Next, as shown in FIG. 4F, a metal pillar 433 having a predetermined height is formed on the UBM 431. Here, the metal filler 433 may include copper or tin, but the material thereof is not limited thereto.

Next, as shown in FIG. 4G, a solder cap 435 may be formed on the metal filler 433. The solder cap 435 may be applied to the upper portion of the metal filler 433 in the form of a liquid and may be formed using an alloy such as tin (Sn), lead (Pb), silver (Ag) However, the material is not limited thereto.

The conductive bump 430 may be composed of the UBM 431, the metal filler 433 and the solder cap 435 as described above, but a solder ball (not shown) may penetrate through the through- ) In direct contact with the substrate.

In this way, a semiconductor device according to another embodiment of the present invention can be completed.

In the step of connecting the semiconductor substrate (S340), the conductive bump 430 of the semiconductor device completed through the above process is placed on the bonding pad 441 of the semiconductor substrate 440 as shown in FIG. 4H, The conductive bump 430 and the bonding pad 441 are bonded through a reflow process at 200 to 300 ° C. The semiconductor device may be electrically connected to the semiconductor substrate 440 while the solder cap 435 of the conductive bump 430 is melted and then cured on the bonding pad 441.

In the underfill region formation step S350, as shown in FIG. 4I, an underfill material composed of a filler such as a resin, an inorganic material, and a curing agent is filled between the semiconductor die 410 and the substrate 440, can do. The underfill region 450 may be formed in the empty space 420a between the adjacent second passivation layers 420, unlike the prior art.

Generally, the distance between the semiconductor die and the substrate or the size of the space may be varied by the second passivation layer. Conventionally, since the second passivation layer is formed over one entire surface of the first passivation layer, the distance between the semiconductor die and the substrate is entirely reduced by the thickness of the second passivation layer. If there are particles in the underfill material that are larger than the distance between the semiconductor die and the substrate, the particles can not move freely between the semiconductor die and the substrate, and the underfill region can be formed nonuniformly.

However, according to another embodiment of the present invention, a portion of the second passivation layer is omitted in various regions, without changing the length of the conductive bump, so that the space or space between the semiconductor die and the substrate can be relatively increased compared to the prior art. As such, the additional space provided between the second passivation layer and the layer ensures sufficient space between the semiconductor die and the substrate and the space therebetween, so that the particles of the underfill material can move more freely between the semiconductor die and the substrate , A more uniform underfill region can be formed.

It is to be understood that the present invention is not limited to the above-described embodiment, but may be modified and changed without departing from the spirit and scope of the present invention. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

100: semiconductor device 110: semiconductor die
111: die pad 113: first passivation layer
120: second passivation layer 130: conductive bump
131: UBN (under bump metal) 133: metal filler
135: solder cap 200: semiconductor package
210: semiconductor die 211: die pad
213: first passivation layer 220: second passivation layer
230: conductive bump 231: UBN
233: metal filler 235: solder cap
240: semiconductor substrate 241: bonding pad
243: Third passivation layer 245: Solder ball
250: underfill area

Claims (20)

A semiconductor die having a first passivation layer and a plurality of die pads;
A plurality of second passivation layers respectively formed on top of the die pad; And
And a plurality of conductive bumps electrically connected to the die pad through the second passivation layer, respectively. The method according to claim 1,
And the second passivation layers are spaced apart from each other. The method according to claim 1,
Wherein a space is formed between the adjacent second passivation layers so that a part of the first passivation layer is exposed to the outside. The method according to claim 1,
And the second passivation layer is formed in a shape extending from the conductive bump toward the side by 1 to 50 占 퐉 with respect to the conductive bump. The method according to claim 1,
The conductive bump may include:
An under bump metal (UBM) electrically connected to the die pad through the second passivation layer;
A metal filler formed on the UBM; And
And a solder cap formed on the upper portion of the metal pillar. The method according to claim 1,
≪ / RTI > wherein the conductive bump comprises a solder ball. A semiconductor device comprising: a semiconductor substrate having a first passivation layer, a plurality of die pads, a plurality of second passivation layers formed respectively under the die pads, and a plurality of conductive bumps electrically connected to the die pads through the second passivation layers, device;
A semiconductor substrate electrically connected to the semiconductor device through the conductive bump; And
And an underfill region filled and formed between the semiconductor device and the semiconductor substrate. 8. The method of claim 7,
And the second passivation layers are spaced apart from each other. 8. The method of claim 7,
And the underfill region is formed between the conductive bumps and the second passivation layer. 8. The method of claim 7,
Wherein the first passivation layer is in direct contact with the underfill region. 8. The method of claim 7,
Wherein the second passivation layer is formed in a shape extending from the conductive bump toward the side by 1 to 50 占 퐉 with respect to the conductive bump. 8. The method of claim 7,
The conductive bump may include:
An under bump metal (UBM) electrically connected to the die pad through the second passivation layer;
A metal filler formed on the UBM; And
And a solder cap formed on an upper portion of the metal pillar. 8. The method of claim 7,
≪ / RTI > wherein the conductive bump comprises a solder ball. Providing a semiconductor die having a first passivation layer and a plurality of die pads;
Forming a plurality of second passivation layers each located on top of the die pad; And
And forming a plurality of electrically conductive bumps electrically connected to the die pad through the second passivation layer, respectively. 15. The method of claim 14,
And the second passivation layers are formed to be spaced apart from each other. 15. The method of claim 14,
Wherein the second passivation layer is formed to extend laterally from the conductive bump by 1 to 50 占 m. Providing a semiconductor die having a first passivation layer and a plurality of die pads;
Forming a second passivation layer on top of the die pad, respectively;
Forming a plurality of conductive bumps through each of the second passivation layers and electrically connected to the die pads, respectively;
Electrically connecting the semiconductor die with the semiconductor substrate through the conductive bump; And
And forming an underfill region between the semiconductor die and the semiconductor substrate. 18. The method of claim 17,
Wherein the second passivation layers are formed to be spaced apart from each other. 18. The method of claim 17,
Wherein the underfill region is formed between the conductive bumps and between the second passivation layer. 18. The method of claim 17,
Wherein the second passivation layer is formed in a shape extending from the conductive bump toward the lateral side by 1 to 50 占 퐉 with respect to the conductive bump.
KR1020140100586A 2014-08-05 2014-08-05 Semiconducotr device, semiconductor package and metode for manufacturing thereof KR101683975B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020140100586A KR101683975B1 (en) 2014-08-05 2014-08-05 Semiconducotr device, semiconductor package and metode for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020140100586A KR101683975B1 (en) 2014-08-05 2014-08-05 Semiconducotr device, semiconductor package and metode for manufacturing thereof

Publications (2)

Publication Number Publication Date
KR20160016431A true KR20160016431A (en) 2016-02-15
KR101683975B1 KR101683975B1 (en) 2016-12-07

Family

ID=55357166

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140100586A KR101683975B1 (en) 2014-08-05 2014-08-05 Semiconducotr device, semiconductor package and metode for manufacturing thereof

Country Status (1)

Country Link
KR (1) KR101683975B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI683407B (en) * 2017-05-23 2020-01-21 矽品精密工業股份有限公司 Substrate structure and method for fabricating the same
KR20210068891A (en) 2019-12-02 2021-06-10 삼성전자주식회사 Interposer and semiconductor package having the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080122086A1 (en) * 2006-11-03 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump structure and method of manufacturing same
KR101059625B1 (en) * 2008-06-09 2011-08-25 삼성전기주식회사 Wafer level chip scale package and its manufacturing method
KR20130135042A (en) * 2012-05-30 2013-12-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Design scheme for connector site spacing and resulting structures
KR20140089283A (en) * 2013-01-04 2014-07-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Metal Routing Architecture for Integrated Circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080122086A1 (en) * 2006-11-03 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump structure and method of manufacturing same
KR101059625B1 (en) * 2008-06-09 2011-08-25 삼성전기주식회사 Wafer level chip scale package and its manufacturing method
KR20130135042A (en) * 2012-05-30 2013-12-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Design scheme for connector site spacing and resulting structures
KR20140089283A (en) * 2013-01-04 2014-07-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Metal Routing Architecture for Integrated Circuits

Also Published As

Publication number Publication date
KR101683975B1 (en) 2016-12-07

Similar Documents

Publication Publication Date Title
KR101905334B1 (en) Method for semiconductor packaging and electronic device
US11031347B2 (en) Semiconductor packages
US10062659B2 (en) System and method for an improved fine pitch joint
TWI581391B (en) Semiconductor package and fabricating method thereof
KR101688698B1 (en) Package and fabricating method thereof
KR101564138B1 (en) Metal Routing Architecture for Integrated Circuits
US7977783B1 (en) Wafer level chip size package having redistribution layers
JP5299458B2 (en) Semiconductor device and semiconductor device unit
KR101579673B1 (en) Method for fabricating semiconductor package and semiconductor package using the same
KR101514137B1 (en) Method for fabricating semiconductor package and semiconductor package using the same
US7863740B2 (en) Semiconductor device having conductive bumps, metallic layers, covering layers and fabrication method thereof
US20190259723A1 (en) Fabrication method of semiconductor structure
US10276531B2 (en) Semiconductor device having a boundary structure, a package on package structure, and a method of making
US10354966B2 (en) Methods of forming microelectronic structures having a patterned surface structure
US20100007015A1 (en) Integrated circuit device with improved underfill coverage
US20160056116A1 (en) Fabricating pillar solder bump
US8895357B2 (en) Integrated circuit and method of manufacturing the same
US20130277828A1 (en) Methods and Apparatus for bump-on-trace Chip Packaging
KR20160103786A (en) Semiconductor Device And Fabricating Method Thereof
US20100155937A1 (en) Wafer structure with conductive bumps and fabrication method thereof
KR101683975B1 (en) Semiconducotr device, semiconductor package and metode for manufacturing thereof
US11810878B2 (en) Wafer-level package including under bump metal layer
US9362245B2 (en) Package structure and fabrication method thereof
US9024439B2 (en) Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same
US9640496B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20191202

Year of fee payment: 4