KR20160012864A - Method of design layout of integrated circuit and computer system performing the same - Google Patents

Abstract

A method of designing the layout of a semiconductor integrated circuit includes a step of configuring a layout pattern for forming the semiconductor integrated circuit, a step of providing a biasing marker to the gate line of the layout pattern, a step of selecting at least one specific transistor among transistors included in the semiconductor integrated circuit, and a step of removing the biasing marker of the gate line of the selected transistor.

Description

[0001] METHOD OF DESIGN LAYOUT OF INTEGRATED CIRCUIT AND COMPUTER SYSTEM PERFORMING THE SAME [0002]

The present invention relates to a method of designing a semiconductor circuit, and more particularly to a method of designing an integrated circuit layout and a computer system for performing the method.

Generally, a schematic circuit is designed by a schematic tool for the design of a semiconductor integrated circuit. A schematic circuit represents a connection relationship between elements and elements included in a semiconductor integrated circuit. Next, each of the elements included in the schematic circuit is designed as a pattern of a material layer such as a conductive layer, a semiconductor layer, and an insulating layer. Thereafter, a layout in which the respective patterns are arranged vertically and horizontally is designed, and then a photomask is generated based on the layout, and the photolithography process is performed. Deposition and patterning of each material layer through photolithography are repeated to produce a semiconductor integrated circuit with a desired function.

In the design of the layout, the basic operating characteristics of the elements are determined by design rules or design rules. The design rule basically defines the items such as the interval between the elements, the minimum line width of the conductive lines, and the extension area or the area. For example, the definition of the gate length of a transistor is mostly determined by a design rule. In addition, if the desired characteristics can not be obtained only by the length of the gate specified in the design rule, an option to adjust the gate length is provided to define the operating characteristics of the various transistors. An operation of finely adjusting the characteristics of a device defined by a design rule will be hereinafter referred to as "biasing".

Semiconductor production processes are being refined at a rapid pace to meet the demand for low cost and high integration. As the process becomes finer, the biasing for adjusting the gate length to obtain desired characteristics is becoming increasingly complicated and difficult. Therefore, there is a need for a layout design method to appropriately utilize the opportunities of limited biasing.

It is an object of the present invention to provide an effective method for defining the gate length of a transistor in a layout design stage of a semiconductor integrated circuit and a computer system for performing the same.

A layout designing method of a semiconductor integrated circuit according to an embodiment of the present invention includes the steps of: constructing a layout pattern for forming the semiconductor integrated circuit; providing a biasing marker to a gate line of the layout pattern; Selecting at least one particular transistor among the transistors included in the selected transistor, and removing the biasing marker of the gate line of the selected transistor.

A computer system for driving a layout designing program for a semiconductor integrated circuit according to another embodiment of the present invention includes an input / output device for receiving biasing information of the semiconductor integrated circuit, a layout determined by the layout designing program or the layout designing program And a central processing unit which executes the layout design program or the verification program with reference to the biasing information provided from the input / output device, wherein the layout design The program includes a step of forming a layout pattern for forming the semiconductor integrated circuit, setting a biasing marker in the gate line of the layout pattern, referring to the biasing information, Selecting at least one of the transistors and emitters, and constitutes a layout of the semiconductor integrated circuit in accordance with the process of removing the biasing marks set in the gate line of the selected transistor.

A method for biasing a semiconductor integrated circuit using a layout design tool according to an embodiment of the present invention includes the steps of: receiving a net list for forming the semiconductor integrated circuit; Configuring a layout pattern, setting biasing data in a gate line pattern of transistors defined in the netlist, and removing biasing data provided in a gate line of at least one of the transistors .

According to the layout design method of the present invention and the computer system using the same, an efficient biasing method for defining the gate length of the transistor in the layout design stage is provided. Therefore, it is possible to shorten the layout design time which requires a lot of cost for pattern design and verification.

Figure 1 is a block diagram illustrating a computer system 100 for performing semiconductor design in accordance with an embodiment of the present invention.
2 is a flowchart showing a method of designing and manufacturing a semiconductor integrated circuit according to the present invention.
FIG. 3 is a flowchart showing the layout designing method of FIG. 2 in detail.
4A and 4B are views illustrating a layout design method of transistors according to an embodiment of the present invention.
FIG. 5 is a view showing a process of forming a layout pattern corresponding to the elements corresponding to FIG. 4B.
FIG. 6 is a table showing the effect on the silicon level obtained by removing the biasing marker according to the present invention.
7A and 7B are views showing a biasing method according to an embodiment of the present invention at a gate level of a circuit.
8 is a table showing an example of adjustment effect of the gate length according to the biasing method of the present invention.
FIGS. 9A and 9B are three-dimensional views schematically showing a form of a FinFET formed with different gate lengths according to the biasing method of the present invention. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. In addition, like reference numerals designate like elements throughout the specification.

Although specific terms are used herein, they are used for the purpose of describing the invention and are not used to limit the scope of the invention as defined in the claims or the meaning of the claims. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / connected " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Figure 1 is a block diagram illustrating a computer system 100 for performing semiconductor design in accordance with an embodiment of the present invention. Referring to FIG. 1, a computer system 100 may include a CPU 110, a working memory 130, an input / output device 150, and a storage device 170. Here, the computer system 100 may be provided as a dedicated device for the layout design of the present invention, but may also use a computer having various design and verification simulation programs as an example.

The CPU 110 executes software (application programs, operating systems, device drivers) to be executed in the computer system 100. The CPU 110 will execute an operating system (OS, not shown) that is loaded into the working memory 130. The CPU 110 may execute various application programs to be operated on an operating system (OS) basis. For example, the CPU 110 may execute the layout design tool 132 loaded in the working memory 130.

An operating system (OS) and application programs are loaded into the working memory 130. An OS image (not shown) stored in the storage device 170 at the boot time of the computer system 100 will be loaded into the working memory 130 based on the boot sequence. All input / output operations of the computer system 100 may be supported by an operating system (OS). Similarly, application programs may be loaded into the working memory 130 for selection by the user or provision of basic services. In particular, the layout design tool 132 for the layout design of the present invention will also be loaded from the storage device 170 into the working memory 130.

The layout design tool 132 has a function of changing the biasing data for setting the characteristics of the selected transistor to be different from those defined by the design rule. The layout design tool 132 may perform a design rule check (DRC) under the changed biasing data condition. The working memory 130 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory such as a PRAM, an MRAM, a ReRAM, a FRAM, and a NOR flash memory.

The layout design tool 132 may perform gate biasing for adjusting the gate length according to an embodiment of the present invention. That is, the layout design tool 132 may change the gate length of the transistors included in the selected semiconductor region or data path to a size different from that of the design rule according to a predetermined procedure. The layout design tool 132 will perform gate biasing by removing the Biasing Marker to adjust the gate length on the selected region or data path.

According to the layout design tool 132, the gates of the transistors in all the regions to be designed are provided with biasing markers so as to conform to the specifications defined in the design rule. And the biasing markers can be removed to have exceptional gate lengths only for the gates of the selected transistors as needed. The layout design tool 132 may perform a Design Rule Check (DRC) on the layout on which the biasing is performed. In addition, the working memory may further include a simulation tool 134 for performing Optical Proximity Correction (OPC) on designed layout data.

The input / output device 150 controls user input and output from the user interface devices. For example, the input / output device 150 may include a keyboard or a monitor to receive information from a designer. By using the input / output device 150, the designer may receive information about semiconductor regions or data paths that require adjusted operating characteristics. The processing and processing results of the simulation tool 134 may be displayed through the input / output device 150.

The storage device 170 is provided as a storage medium of the computer system 100. The storage device 170 may store application programs, an OS image, and various data. The storage device 170 may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.) or a hard disk drive (HDD). The storage device 170 may include a NAND-type flash memory having a large storage capacity. Alternatively, the storage device 170 may include a next generation nonvolatile memory such as PRAM, MRAM, ReRAM, FRAM, or the like, or a NOR flash memory.

The system interconnect 190 is a system bus for providing a network within the computer system 100. The CPU 110, the working memory 130, the input / output device 150, and the storage device 170 are electrically connected through the system interconnect 190 and exchange data with each other. However, the configuration of the system interconnect 190 is not limited to the above description, and may further include arbitration means for efficient management.

According to the above description, the computer system 100 can adjust the gate length in such a manner that the biasing markers are removed with respect to the selected region or data path at the time of designing the layout of the semiconductor integrated circuit. Therefore, it is possible to provide high design efficiency, convenience, and cost reduction in designing a layout of a high-performance and highly integrated circuit in which a line width is shrinked as compared with a method of selectively adding a biasing marker only to a selected region.

2 is a flowchart showing a method of designing and manufacturing a semiconductor integrated circuit according to the present invention. Referring to FIG. 2, layout design, verification, and production can be performed according to the design and manufacturing method of the semiconductor integrated circuit of the present invention. More detailed description is as follows.

In step S110, a high level design of the semiconductor integrated circuit by the computer system 100 may be performed. Higher level design means that the integrated circuit to be designed is described as a higher language of the computer language. For example, it uses the upper language such as C language. Circuits designed by high level design are more specifically represented by register transfer level (RTL) coding or simulation. In addition, the code generated by register transfer level (RTL) coding can be converted to a netlist and synthesized into an entire semiconductor integrated circuit. The synthesized schematic circuit is verified by the simulation tool and the adjustment process can be accompanied by the verification result.

In step S120, a layout design is performed to implement the logically completed semiconductor integrated circuit on the silicon substrate. For example, a layout design can be performed by referring to a schematic circuit synthesized in a high-level design or a corresponding netlist. The layout design may include a routing procedure for placing and connecting various cells provided in a cell library according to prescribed design rules. At the time of layout design, a biasing procedure for finely adjusting the gate length is included. A biasing marker is provided to designate a pattern of a gate line to be biased as a target of biasing. The gate length of a particular transistor can be selectively adjusted by a biasing marker.

According to the layout design method of the present invention, a biasing marker is provided to the gate lines of all the transistors. And selectively removing the biasing markers of the selected transistor, the selected circuit area, and the gate line corresponding to the selected data path. This biasing method further adheres to reduced design rules compared to the way in which a biasing marker is added to a selected transistor, a selected region, or a selected data path.

The cell library for layout design may also include information on the operation, speed, and power consumption of the cell. A cell library for expressing a circuit of a specific gate level in layout is defined in most layout design tools 132. [ Layout is a procedure that defines the shape or size of a pattern to construct transistors or gates that will actually be formed on silicon. For example, in order to actually form an inverter circuit on silicon, a layout pattern such as PMOS, NMOS, N-WELL, and gate line must be drawn. For this purpose, it is possible to search for and select an appropriate one of the inverters already defined in the cell library. In addition, routing for selected and deployed cells will be performed. Of course, most of these processes are performed automatically or manually by the layout design tool 132.

In addition, after routing, verification of the layout can be performed to determine whether there is a part that violates the design rule. The items to be verified are DRC (Design Rule Check) to verify that the layout is in compliance with the design rules, ERC (Electronic Rule Check) to verify that the layout has been properly electrically disconnected, and whether the layout matches the gate- LVS (Layout vs. Schematic).

In step S130, an Optical Proximity Correction (OPC) procedure is performed. Optical proximity correction (OPC) is a technique for correcting a distortion phenomenon of a photolithography process in which a mask constructed through layout design is drawn on a silicon wafer substrate. That is, optical proximity correction (OPC) is a technique for correcting a distortion phenomenon such as a refraction or a process effect caused by a light characteristic at the time of exposure using a layout pattern. By performing the photolithography process, the layout pattern can be formed on the semiconductor substrate. The OPC performing step (S130) may refer to a process of changing the layout by reflecting the error according to the optical proximity effect.

Recently, the wavelength of light used for mask exposure has become longer than the feature size of each chip as the integrated circuit moves to an unprecedentedly fine line width. Optical proximity correction (OPC) selectively distributes the circuit pattern to the wafer more reliably by selectively distorting the shape of the photomask to reduce refraction effects due to the long wavelength of light. Optical proximity correction (OPC) is used where line widths vary on the same chip. Optical proximity correction (OPC) can also be used where there is a shortening of the line end, such as caused by gate overlap on the field oxide.

In step S140, a photomask is produced based on the layout pattern changed by the optical proximity correction (OPC). Generally, a photomask is fabricated in such a manner that a layout pattern is depicted using a chromium thin film coated on a glass substrate.

In step S150, a semiconductor integrated circuit is manufactured using the generated photomask. In the process of manufacturing a semiconductor integrated circuit using a photomask, various exposure and etching procedures are repeated. Through this procedure, patterns of patterns formed at the time of layout design will be sequentially formed on the semiconductor substrate.

In the foregoing, a semiconductor manufacturing process to which the layout designing method of the present invention is applied has been briefly described. According to the layout design method of the present invention, a biasing marker is defined that defines biasing for the gates of all transistors. The adjustment of the gate length can then be performed in a manner that removes the biasing markers only for the transistors corresponding to the selected region or data path. Therefore, a biasing method adapted to a micronized semiconductor layout design can be provided as compared to a procedure of adding a biasing marker to a selected region.

FIG. 3 is a flowchart showing the layout designing method of FIG. 2 in detail. Referring to FIG. 3, the gate biasing according to the present invention is designed such that gate lines of all the transistors are designed to include a biasing marker, and then a biasing marker for the selected transistor, And the like.

In step S121, a layout design for the semiconductor integrated circuit is performed. Here, biasing markers for all the transistors of the semiconductor integrated circuit are collectively applied. That is, a biasing marker for defining the gate length of the transistors may be provided equally to the gate line pattern of all the transistors. For example, it is assumed that the gate length of the transistor processed by the biasing marker is formed to (L + d), and the length of the gate of the transistor from which the biasing marker is removed is formed to (L). Then, at the time of layout design, the gate length of all the transistors is set to the default value (L).

In step S123, a semiconductor region, a data path, or a specific transistor whose gate length is required to be adjusted can be selected. For example, a data path or a circuit area in which the reduction of the low power or the leakage current is given priority can be selected. Alternatively, transistors, element regions, or data paths that require a higher processing speed than other transistors may be selected.

In step S125, the biasing procedure of the present invention is performed on the selected semiconductor region, data path, or specific transistor. The biasing procedure of the present invention can be performed by a removal method instead of an addition method of a biasing marker. That is, the layout design tool 132 (see FIG. 1) alters the biasing markers for the gates of the transistors included in the selected semiconductor region or data path. For example, if the layout design tool 132 has selected transistors that should operate faster than other transistors, the biasing markers of the elements or gates other than the selected transistors will be maintained. On the other hand, if transistors that are slower than other transistors but with a reduction in leakage current are selected, the biasing markers provided to the transistors included in the elements or gates included in the selected region will be removed.

This biasing method is based on the assumption that the gate length is relatively shortened when a biasing marker is provided. However, it will be appreciated that the biasing marker may act in a manner that increases the gate length. In this case, the gate length will be reduced rather than removing the bias marker.

In step S127, a design rule check (DRC) is performed on the biased layout. Whether the line width or inter-device distance changed by biasing is within the range allowed by the design rule or violates the design rule is determined through the DRC. As a result of the DRC, a procedure for adjusting the gate length in addition to the error should be performed. On the other hand, if it is determined that there is no error as a result of the DRC, the overall layout design is completed.

According to the biasing method of the present invention described above, biasing data (or a biasing marker) is provided as a default value in a gate line of all the transistors included in the semiconductor integrated circuit. Followed by the removal of the biasing marker, which is basically provided only for the selected transistors. Therefore, the biasing method of the present invention can provide high efficiency in the layout design of a semiconductor integrated circuit in which high performance operation is required to the extent that the design rule permits. That is, when the number of transistors for which the biasing markers are removed is smaller than the number of transistors for holding the biasing markers, the time and cost required for layout design are expected to be reduced.

4A and 4B are views illustrating a layout design method of transistors according to an embodiment of the present invention. FIG. 4A shows a layout before the biasing of the present invention is performed, and FIG. 4B shows a layout of a transistor in which a biasing marker is removed by the biasing of the present invention.

Referring to FIG. 4A, the layout basic structure 200a of the present invention is applied to a transistor. Polysilicon may be formed on the substrate to form the PMOS transistor and the NMOS transistor. First, an N-well 210 is formed on the top of the substrate. Subsequently, active regions 220 and 230 will be formed inside and outside the N-well 210, respectively. And polysilicon to form gate lines 240 and 245 must be formed. Biasing markers 250 and 255 for gate lines 240 and 245 are provided to all transistors basically. It should be noted that the biasing markers 250 and 255 are data types defined by the layout design tool 132. [ That is, the biasing markers may be set to the type for each gate line, not the pattern layer added to the layout in the illustrated form. In particular, the gate line defined by the bias mark of the present invention includes information on the gate length corresponding to the channel length of the transistor.

4B is a view showing a layout structure 200b to which the biasing method of the present invention is applied. Referring to FIG. 4B, the biasing markers are maintained for the transistors requiring high-speed operation, and the biasing markers of the transistors for which the reduction of the current leakage is prioritized can be eliminated. Illustratively, the biasing marker 250 of the gate line 240 is maintained. In this case, the length of the gate line 240 formed by the exposure process using the photomask will be given as (L). On the other hand, the biasing marker 255 (see FIG. 4A) of the gate line 250 is maintained. In this case, the length of the polysilicon corresponding to the gate line 245 formed by the exposure process using the photomask will be given as (L + d).

FIG. 5 is a view showing a process of forming a layout pattern corresponding to the elements corresponding to FIG. 4B. Referring to FIG. 5, a sequence of a method of biasing performed in the layout designing process of the present invention is shown.

In step (a), an N-well pattern 210 is first provided to form an N-well. The N-well is generally a pattern formed on the substrate to form a PMOS transistor.

In the following step (b), active patterns 220 and 230 are provided. An active pattern 220 for forming a PMOS transistor will be provided inside the N-well pattern 210. [ On the other hand, the active pattern 230 for forming the NMOS transistor will be disposed outside the N-well pattern 210, that is, above the substrate.

In step (c), the gate line patterns 240 and 245 will be provided. The gate lines pattern 240 and 245 do not have a biasing marker for adjusting the gate length.

In step (d), biasing markers 250 and 255 for both the gate line patterns 240 and 245 are provided. Here, the biasing markers 250 and 255 may be provided with tag data of a specific type as marking information for substantially the gate lines.

In step (e), the biasing markers of the selected transistors are removed. In order to provide the specific operation characteristics, the removal procedure of the biasing markers of the transistors other than the selected data path, the selected device, and the selected chip area proceeds. That is, the biasing markers of the transistors for the selected region or for regions other than the selected region may be deducted.

The procedures in the above-described figures are merely illustrations of the procedures that are performed substantially on the data by the layout design tool 132. [ That is, the layout design tool 132 provides the biasing markers to all of the transistors, and the biasing markers for the transistors in the selected region or the non-selected region are removed to obtain the desired operational characteristics of the semiconductor integrated circuit have.

FIG. 6 is a table showing the effect on the silicon level obtained by removing the biasing marker according to the present invention. Referring to FIG. 6, a change in the gate length of the biasing marker (Normal) when the biasing marker is held and a variation of the gate length when the biasing marker is removed (Deducted) are exemplarily described.

When the biasing marker is maintained (Normal), the length of the gate formed by the layout pattern does not change at the time of designing. On the other hand, if the biasing marker is removed, the gate length of the transistor may increase or decrease by d. This is because the data type of the biasing marker defines the increase or decrease of the gate length. If the type of the biasing marker is of the type that increases the width of the selected polysilicon, the opposite effect will appear. In this case, if the biasing marker is maintained, the gate length will increase by d relative to the length L at design time.

7A and 7B are views showing a biasing method according to an embodiment of the present invention at a gate level of a circuit. FIG. 7A shows a case where a biasing marker is provided for all transistors according to an embodiment of the present invention, and FIG. 7B shows a form in which a biasing marker for a selected data path is removed.

7A, it is assumed that there are logic circuits that transfer data from the first flip-flop stage 310, 312, 314, 316 to the second flip-flop stage 380, 382, 384, 386 . Logic gates for forming a plurality of data paths will be selected in the cell library and provided in a layout structure. At this time, in the process of designing the layout structure, the biasing markers will be provided for the transistors constituting all the logic gates. However, the logic gates to operate at high speed and the logic gates to operate at low speed can exist at the same time. Therefore, biasing for providing such characteristics will have to be performed in the layout design stage.

The logic gates 322, 332, 352, and 362 that transfer data from the flip-flop 312 to the flip-flop 382 constitute a data path that must operate at high speed. And logic gates 324, 334, 344, 354, 364, and 374 that transfer data from flip-flop 314 to flip-flop 384 are also data paths that must operate at high speed. A biasing marker will be provided in the gate line of the transistors constituting all the logic gates without distinguishing between the logic gates that will operate at high speed and the logic gates that operate at low speed during layout design. In the circuit diagram shown, all the shaded areas indicate logic gates provided with a biasing marker.

FIG. 7B is a circuit diagram showing a case where the biasing method according to the embodiment of the present invention is applied. According to Fig. 7B, the biasing markers of the data path to be driven at a high speed are maintained, and the biasing markers of the data path are eliminated even if they operate at a low speed. That is, the biasing markers provided to the gate lines of the transistors constituting the logic gates 320, 330, 340, 342, 326 and 336 are removed. On the other hand, the biasing markers of the transistors constituting the logic gates 322, 332, 352 and 362 and the logic gates 324, 334, 344, 354, 364 and 374, which must operate at high speed, do.

The present invention provides an advantage in layout design of a semiconductor integrated circuit in which a relatively short gate length requires a relatively large proportion of a biasing operation than a biasing operation in which a gate length must be maintained. That is, the layout method of the present invention can be usefully applied to a FinFET process in which a ratio of data paths or transistors that need to be high-speed or high-performance is relatively large. In addition, the advantages of the present invention can be provided in a process in which the number of transistors for removing a biasing marker is less than the number of transistors for which a biasing marker is to be held.

8 is a table showing an example of adjustment effect of the gate length according to the biasing method of the present invention. Referring to FIG. 8, the characteristics of the transistor in which the biasing marker is held and the operation characteristics of the transistor in which the biasing marker is removed are shown. Here, it is assumed that the gate length (L + d) of the transistor from which the biasing marker is removed is 16 nm. It is assumed that the gate length d which is reduced when the biasing marker is held is 2 nm. The relative operating speed and the leakage current are calculated based on the transistor from which the biasing marker has been removed.

First, the gate length of the transistor in which the biasing marker is held will be about 14 nm (L). The operating speed of the transistor whose gate length is relatively reduced will be about 1.1 times larger than that of the transistor having the gate length L and the leakage current will be increased about 1.4 times. A transistor in which such a biasing marker is held in a layout design can be set in a transistor, a cell library area, or a data path in which an operation speed is important.

On the other hand, the gate length (L + d) of the transistor from which the biasing marker is removed is formed to be 16 nm. The operating speed of the transistor with the biasing marker removed is about 1 times as fast as the reference speed, and the magnitude of the leakage current is about 1 times as large as the reference leakage current. A transistor in which such a biasing marker is removed at the time of layout design may be set in a transistor or a chip area or a data path in which a reduction in leakage current or a reduction in power is more important than an operation speed.

In the above table, the case where the gate length is defined to be decreased by d when the biasing marker is added has been described as a reference. However, it will be appreciated that the gate length may be defined to increase by d if a biasing marker is added.

FIGS. 9A and 9B are three-dimensional views schematically showing a form of a FinFET formed with different gate lengths according to the biasing method of the present invention. FIG. FIG. 9A shows a finet (FinFET) in which a biasing marker is held and a gate length is reduced, for example. FIG. 9B shows a FinFET having a gate length defined in the design rule as the bias mark is removed.

Referring to FIG. 9A, a pinpet 400, which is formed in an illustrative manner in a bulk form, is illustrated to illustrate the features of the present invention. A silicon fin 410 and an oxide film region 430 are formed on a substrate (not shown). A gate 420 may be formed on the oxide film region 430 and the silicon fin 410. The silicon fin 410 will substantially constitute the source and the drain. These silicon fins 410 are generally arranged repeatedly on the top of the substrate according to a certain rule, and adjacent silicon fins are separated through element isolation regions such as trenches (STI, not shown). The height Hfin and the width Dfin of the silicon fin 410 may be defined by a design rule at the time of layout design.

The silicon fins 410 are formed by etching a certain region of the substrate and thus have a protruding structure, and are defined as both side walls and upper surface. Although not shown, the etched region of the substrate will be filled with the device isolation region as a trench. The gate 420 traverses the silicon fin 410. During layout design, the gate structure of such a FinFET will not be distinguished from a planar MOS transistor. However, the layout of the FinFET and the flat plate structure transistor can be differentiated in terms of the structure for forming the silicon fin.

The gate 420 is formed when the biasing marker is held. The length of the gate 420 by the biasing markers may be reduced to a size smaller than the default value by d. As a result, the length of the channel formed in the silicon fin 410 becomes approximately (L-d).

Referring to FIG. 9B, the pin-pin 500 includes a silicon fin 510 and an oxide film region 530. A gate 520 may be formed on the oxide film region 530 and the silicon fin 510. The silicon fin 510 will substantially constitute the source and the drain. The height (Hfin) and width (Dfin) of the silicon fin 510 may be defined by a design rule at the time of layout design. The gate 520 shows the shape of the gate line formed on the silicon substrate when the biasing marker is removed. The length of the gate 520 by the biasing marker will be formed to have a default value L. [

9A and 9B, the result of the biasing for finely adjusting the gate length of the transistor is schematically explained. When the biasing marker is removed, the width of the gate line decreases. That is, the gate length is reduced for the transistor. In a semiconductor integrated circuit that needs to provide high performance, the circuitry to which such a biasing marker should be provided may be larger than the circuit to remove the biasing marker. Thus, it may be more efficient to provide biasing markers for all transistors and selectively remove them, rather than adding biasing markers to selected circuits in the layout design of such integrated circuits. Particularly, when the biasing method of the present invention is applied to an integrated circuit such as an application processor using a FinFET, it is expected that the time and cost required for layout designing can be drastically reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

100: Computer system
110: CPU
130: Working memory
150: input / output device
170: Storage device
190: System Interconnect

Claims (20)

A layout design method of a semiconductor integrated circuit comprising:
Forming a layout pattern for forming the semiconductor integrated circuit;
Providing a biasing marker to a gate line of the layout pattern;
Selecting at least one specific transistor among the transistors included in the semiconductor integrated circuit; And
And removing a biasing marker of a gate line of the selected transistor. The method according to claim 1,
Wherein the gate length of the gate line set by the biasing marker is shorter than the gate length of the gate line from which the biasing marker is removed. 3. The method of claim 2,
Wherein the selected at least one transistor has a characteristic condition that is slower than that of the transistor whose operation speed is not selected. The method of claim 3,
Wherein the selected at least one transistor has a characteristic condition that a magnitude of a leakage current should be smaller than that of the unselected transistor. The method according to claim 1,
Wherein the gate length of the gate line set by the biasing marker is longer than the gate length of the gate line from which the biasing marker is removed. 6. The method of claim 5,
Wherein the selected at least one transistor has a characteristic condition that an operating speed should be faster than a non-selected transistor. The method according to claim 6,
Wherein the selected at least one transistor has a characteristic condition that the magnitude of the leakage current is greater than that of the unselected transistor. The method according to claim 1,
And performing a design rule check on the semiconductor integrated circuit after removing the biasing markers. A computer system for driving a layout designing program of a semiconductor integrated circuit, comprising:
An input / output device for receiving biasing information of the semiconductor integrated circuit;
A working memory for loading a verification program for performing a design rule check on a layout determined by the layout design program or the layout design program; And
And a central processing unit for executing the layout design program or the verification program with reference to the biasing information provided from the input / output device,
The layout designing program includes:
A bias pattern is formed on the gate line of the layout pattern, and at least one transistor among the transistors included in the semiconductor integrated circuit is referred to as the bias pattern by referring to the biasing information, And removing the biasing markers set in the gate lines of the selected transistors. 10. The method of claim 9,
Wherein the biasing information is selection information for the transistors to be driven at high speed or the transistors for which leakage current should be reduced among the transistors. 10. The method of claim 9,
Wherein a biasing marker is added to a gate line of all the transistors of the semiconductor integrated circuit when setting a biasing marker in the gate line of the layout pattern. 10. The method of claim 9,
Wherein a gate length of the transistor with the biasing marker set is shorter than a gate length of the transistor from which the biasing marker is removed. 10. The method of claim 9,
Wherein a gate length of the transistor in which the biasing marker is set is longer than a gate length of the transistor in which the biasing marker is removed. 10. The method of claim 9,
Wherein the verification program performs a design rule check on the layout after the biasing marker is removed. 10. The method of claim 9,
Wherein the transistors of the semiconductor integrated circuit comprise a FinFET. A method for biasing a semiconductor integrated circuit using a layout design tool, the method comprising:
Receiving a netlist for forming the semiconductor integrated circuit;
Constructing a layout pattern for forming the semiconductor integrated circuit with reference to the netlist;
Setting biasing data in a gate line pattern of transistors defined in the netlist; And
And removing the biasing data provided to the gate line of at least one of the transistors selected. 17. The method of claim 16,
Wherein the width of the gate line from which the biasing data is removed is greater than the width of the gate line from which the biasing data is not removed. 18. The method of claim 17,
Wherein the selected at least one transistor has a slower operating speed than the transistors. 17. The method of claim 16,
Wherein the ratio of the selected transistor to the transistors is less than the ratio of the unselected transistors to the transistors. 20. The method of claim 19,
Wherein the biasing data is data specifying to increase or decrease a width of a corresponding gate line.

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