KR20160007421A - Serial port communication for storage device using single bidirectional serial data line - Google Patents

Abstract

Provided is a method for enabling communication between a controller and a pre-amplifier in a storage device. For example, the method includes a step of materializing a serial port which is configured to transmit digital signals through a single bidirectional serial data line between the controller and the pre-amplifier. The serial port is controlled to selectively transmit the digital signals through the bidirectional serial data line in either a first direction from the controller to the pre-amplifier or a second direction from the pre-amplifier to the controller.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to serial port communication for a storage device using a single bidirectional serial data line,

The field relates generally to data storage devices, and more particularly to communication between components of a data storage device.

BACKGROUND OF THE INVENTION Data storage devices, such as hard disk drives, are being used for non-volatile data storage applications in various data processing systems. In a magnetic disk storage device, the storage disk comprises a substrate composed of a non-magnetic material such as aluminum or glass coated with one or more thin magnetic layers. In operation, data is read from and written to the track of the magnetic storage disk using a magnetic head including a read sensor and a write element. Generally, the storage device is a preamplifier configured to drive the read sensor in the magnetic head to read data from the magnetic storage disk and amplify the read data, as well as to drive the write elements in the magnetic head to write data to the storage disk . Moreover, the storage device includes a recording channel configured to decode the read data received from the preamplifier and to encode the record data to be written to the storage disc. Communication between the preamplifier and the recording channel is performed using, for example, an analog bus and a digital bus. A typical analog bus includes a plurality of analog signal lines, which enable high speed transmission of analog read and write data signals between the write channel and the preamplifier. Each analog line is a dedicated line for transmitting either read data or write data. A typical digital bus also implements a three-wire serial port that includes a clock signal line, a data line, and an enable line, which is a digital control for setup and status monitoring of configuration registers located within the pre- And transmits a signal. Other digital control functions that require a dedicated digital control line and can not tolerate the polling and potential characteristics of the serial port may be implemented on an on a bit-significant basis via an additional dedicated control bus line. Lt; / RTI > This conventional communication scheme is insufficient in terms of the number of signal lines required to transfer data and control signals between the recording channel, the preamplifier, and the controller.

In an embodiment of the present invention, a method is provided for enabling communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port configured to transmit a digital signal between a controller and a preamplifier via a single bidirectional serial data line. The serial port is controlled to selectively transmit a digital signal through a bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

Other embodiments include, without limitation, circuitry, systems, integrated circuit devices, storage devices, storage systems, and computer-readable media.

Figure 1 schematically illustrates a storage device according to an embodiment of the invention.
2 is a schematic diagram illustrating a more detailed embodiment of the storage device of FIG. 1 with control circuitry supporting serial port communication between the controller and the preamplifier using a single bidirectional serial data line, in accordance with an embodiment of the present invention. Respectively.
3 is a flow diagram of a method for implementing serial port communication between a controller and a preamplifier using a single bidirectional serial data line, in accordance with an embodiment of the present invention.
4 is a timing diagram that schematically illustrates a method for controlling a serial port that selectively transmits a digital signal between a controller and a preamplifier using a single bidirectional serial data line, in accordance with an embodiment of the present invention.
5 schematically illustrates an embodiment of a phase locked loop circuit that may be implemented in a preamplifier that supports serial port communication between a controller and a preamplifier using a single bidirectional serial data line, in accordance with an embodiment of the present invention .
6 is a schematic circuit diagram illustrating a reset circuit for resetting a preamplifier, in accordance with an embodiment of the present invention.
7 is a schematic circuit diagram illustrating a reset circuit for resetting a preamplifier, in accordance with another embodiment of the present invention.
8 schematically illustrates a data storage device having control circuitry for supporting serial port communication between a controller and a preamplifier using a signal line of an analog bus as a bidirectional serial data line, in accordance with an embodiment of the present invention.
9 schematically illustrates a data storage device having control circuitry that supports serial port communication between a controller and a preamplifier using a signal line of an analog bus as a bidirectional serial data line, in accordance with another embodiment of the present invention.
10 is a block diagram of a virtual storage system including a plurality of disk-based storage devices in the manner shown in FIG.

1 schematically depicts a storage device 10 according to an embodiment of the present invention. The storage device 10 includes a hard disk controller 102, a host interface controller 104, a motor control circuit 106, a memory controller 108, a write channel circuit 110, a master serial port control circuit 112, On-chip 100 that includes various integrated circuits such as a buffer memory 114. The system- The internal bus 116 enables communication between the hard disk controller 102, the host interface controller 104, the motor control circuit 106, the write channel circuitry 110, and the master serial port control circuitry 112 . The system-on-chip 100 further includes a plurality of interfaces, such as a host interface connector 118, a memory interface 120, and a servo interface 122. The storage device 10 further includes a preamplifier circuit 130, a random access memory 140, and a read / write head and a disk assembly 150. The preamplifier circuit 130 includes a slave serial port control circuit 132. Master and slave serial port control circuits 112 and 132 are collectively referred to in the present invention as master / slave serial port control circuit 112/132 or serial port control circuit 112/132.

The storage device 10 further includes an analog bus 200, a digital bus 202, and bit significant lines 204. In one embodiment of the present invention, analog bus 200, digital bus 202, and mantissa line 204 are connected to preamplifier circuit 130 using a flexible cable or flex-cable comprising a plurality of signal lines, To the circuitry on the system-on-chip 100. In one embodiment of the present invention, each signal line of analog bus 200, digital bus 202, and mantissa line 204 is a different transmission line that supports different signaling using different driver circuits. In another embodiment of the present invention, the signal lines may be implemented using other common transmission lines, such as single-ended transmission lines, suitable for a given application.

The analog bus 200 enables communication between the write channel circuit 110 and the preamplifier circuit 130. In one embodiment of the present invention, the analog bus 200 includes a plurality of unidirectional signal lines for transferring read and write information signals between the write channel circuit 110 and the preamplifier circuit 130. The analog bus 200 includes one or more signal lines that are controlled by a multiplexing circuit that is coupled between the write channel circuitry 110 and the preamplifier circuitry 130, And controls bidirectional transmission of read and write information signals over one or more signal lines.

The digital bus 202 is controlled by the serial port control circuit 112/132. The digital bus 202 and the serial port control circuitry 112/132 are connected between the hard disk controller 102 and the preamplifier circuitry 130 via a serial port configured to transmit digital signals over a single bidirectional serial bus of the digital bus Execute in batch. As described in more detail below, the serial port control circuitry 112/132 operates in a master / slave manner to enable communication between the hard disk controller 102 and the preamplifier circuitry 130. 1, the master serial port control circuitry 112 is coupled to the hard disk controller 102 and the master serial port control circuitry 112. In another embodiment of the present invention, .

The mantissa sub-line 204 allows the hard disk controller 102 to send a digital control signal (based on the mantissa) to the preamplifier circuitry 130 to provide a dedicated digital control line, It is a dedicated signal line that controls the function that can not acquire characteristics. For example, the Write Gate, Mode, and Fault control signals are control signals that can be transmitted over a dedicated line of the mantissa sub-line 204.

In general, the preamplifier circuit 130 is implemented using process techniques that are optimized for transmission of analog signals and / or process processing. For example, in one embodiment of the present invention, the preamplifier circuit 130 is implemented using bipolar and CMOS processing techniques. The master serial port control circuit 112 is implemented using process techniques that are optimized for the transmission and / or processing of digital signals. For example, in one embodiment of the present invention, the master serial port control circuit 112 is implemented using CMOS processing techniques.

The read / write head and disk assembly 150 includes a spindle motor 160, a spindle 165, a storage medium 170, a magnetic head / write head 180 (or simply " Quot; head "), and an actuator motor 190 (or a voice coil motor) with a positioning arm 185 facing the magnetic head 180 at one end. The storage medium 170 has a storage surface coated with one or more magnetic bodies capable of storing data bits in the form of a respective group of media-grains oriented in a common magnetization direction (e.g., up or down) have. The storage medium 170 is mounted on the spindle 165 and the spindle 165 is driven by the spindle motor 160 to rotate the storage medium 170 at high speed. The data is read from the storage medium 170 via the magnetic head 180 mounted on the positioning arm 185 and recorded on the storage medium. The actuator motor 190 includes a permanent magnet and a movable coil motor and controls the magnetic head 180 such that the storage medium 170 is rotated by the operation of the spindle motor 160. The actuator motor 190 includes a permanent magnet and a movable coil motor, Lt; RTI ID = 0.0 > a < / RTI >

Generally, a sequence of flux transitions corresponding to a sequence of digital data is recorded on the magnetic surface of the storage medium 170 using the magnetic head 180. The digital data sequence serves to regulate the current in the write coil of the magnetic head 180. The magnetic surface of the storage medium 170 includes a plurality of concentric tracks, each track being subdivided into a plurality of sectors capable of storing sector data blocks for later retrieval. Moreover, the storage medium 170 further includes a timing pattern formed on its surface, which includes one or more sets of servo address marks (SAMs) or other types of servo marks formed in a particular sector, Here, the servo mark is used to detect the position of the magnetic head 180 with respect to the track recorded on the storage medium 170.

The host interface connector 118 represents a physical connector and associated input / output (I / O) bus wiring that connects the storage device 10 to a host system, device, I / O bus, or other component of a data processing system . I / O data is transferred to and from the storage device 10 via the host interface connector 118 under the control of the host interface controller 104. The host interface controller 104 implements a communication protocol that communicates with the host system or device and controls and manages data I / O operations using one or more well-known interface standards. For example, in one or more alternative embodiments of the present invention, the host interface connector 118 and the host interface controller 104 may be, for example, a small computer interface (SCSI), a serial attached SCSI (SAS) Advanced Technology Attachment) and / or Fiber Channel (FC) interface standards.

The hard disk controller 102 controls the overall operation of writing data to the storage medium 170 and reading the data from the storage medium. In addition, in one embodiment of the present invention, the hard disk controller 102 controls the operation of ECC (Error Correction Code), as well as data flow through the internal bus 116 and read / For example, via a direct memory access (DMA) protocol, in the buffer memory 114. The buffer memory 114 may be a programmable microprocessor or microcontroller. In another embodiment, the hard disk controller 102 may be implemented using other known architectures suitable for controlling hard disk operation and ECC / data flow operations. The recording channel circuit 110 encodes and decodes the data recorded on the storage medium 170 and read from the storage medium using the magnetic head 180. The write channel circuitry 110 includes various types of circuitry typically implemented in a write channel that reads data from and reads data from the storage medium 170, details of which are described herein But are not required for those of ordinary skill in the art to understand the embodiments of the invention as such.

The preamplifier circuit 130 is connected between the write channel circuit 110 and the magnetic head 180. In one embodiment, the preamplifier circuit 130 is placed close to the pivotal position of the actuator motor 190. A flexible printed circuit cable is used to connect the magnetic head 180 to the preamplifier circuit 130. The preamplifier circuit 130 amplifies the analog output output from the magnetic head 180 for input to the write channel circuit 110 and generates a bias voltage for driving the read sensor of the magnetic head 180. [

The motor control circuit 106 is connected to the head / disk assembly 150 via the servo interface 122. It will be appreciated that the servo interface 122 includes various components, such as signal lines, for transmitting motor control signals, and power driver circuitry for driving the spindle motor 160 and the actuator motor 190. Typically, a power driver circuit is implemented in a dedicated integrated circuit chip coupled between the system-on-chip 100 and the head / disk assembly 150. The motor control circuit 106 generally generates a control signal for controlling the spindle motor 160 and the actuator motor 190 that rotates the storage medium 170 and moves the magnetic head 180 to the target position during a read and write operation .

In particular, during typical read operations, a read command signal for performing a read operation is received via the host interface connector 118 and transmitted via the host interface controller 104 via the internal bus 116 to the hard disk controller 102 do. The hard disk controller 102 processes the read command signal for performing the read operation and then transmits the control signal to the motor control circuit 106 to control the actuator motor 190 and the spindle motor 160 for the read operation . The hard disk controller 102 also transmits the processed read signal to the write channel circuitry 110 and the processed read signal is then supplied to the actuator motor 190 via the preamplifier 130 to perform a read operation . The actuator motor 190 places the magnetic head 180 on the target data track on the storage medium 170 in response to the control signal generated by the motor control circuit 106 and the write channel circuitry 110. The motor control circuit 106 also generates a control signal to drive the spindle motor 160 that rotates the storage medium 170 under the direction of the hard disk controller 102. The spindle motor 160 rotates the storage medium 170 at a determined rotational speed. In one embodiment of the invention, the motor control circuit 106 is a circuit component of the hard disk controller 102.

As the magnetic head 180 is positioned adjacent the target data track, a magnetic signal representing the data on the storage medium 170 as the storage medium 170 is rotated by the spindle motor 160, Lt; / RTI > The sensed magnetic signal is provided as a continuous fine analog signal (reverse read signal) representative of magnetic data on the storage medium 170. The analog signal that has been read back is transferred from the magnetic head 180 to the write channel circuit 110 via the preamplifier circuit 130. The preamplifier circuit 130 amplifies the backread read analog signal accessed from the storage medium 170 and the write channel circuit 110 decodes and digitizes the amplified backread read analog signal to produce the original Reproduce the recorded information. The data read from the storage medium 170 is then output to the host system or device via the host interface controller 104 and the host interface connector 118 under the control of the hard disk controller 102.

The write operation is substantially the reverse of the read operation. For example, in one embodiment, write data and command signals for performing a write operation are received via the host interface connector 118, wherein the write signal is a command and / or storage medium 170 that performs a write operation, As shown in FIG. The write signal is transmitted to the hard disk controller 102 via the host interface controller 104. [ The hard disk controller 102 processes a recording signal for performing a recording operation and then transmits a control signal to the motor control circuit 106 to control the actuator motor 190 and the spindle motor 160 to perform a recording operation do. Further, the hard disk controller 102 transmits the processed recording signal (and formatted data) to the recording channel circuit 110, and the formatted data to be recorded in this circuit is encoded. The write signal (control and data) is then transmitted to the head / disk assembly 150 via the preamplifier circuit 130 and the write operation is performed by writing the data to the storage medium 170 via the magnetic head 180 .

1, the random access memory 140, the buffer memory 114, the memory controller 108, and the memory bus 120 typically perform data caching and buffering functions that are performed in the data storage device, It is configured to be able to store and access a firmware sequence that controls the operation of the hard disk controller 102 and other components connected thereto. Random access memory 140 is external memory for system-on-chip 100 and other components of storage device 10, but nevertheless exists within storage device 10. In one embodiment, the random access memory 140 is a double data rate synchronous dynamic random access memory, although various other types of memory may be used in alternative embodiments.

The random access memory 140, the system-on-a-chip 100 and the preamplifier circuit 130 shown in Figure 1 collectively represent one embodiment of a "control circuit" when this term is used herein It will be understood. Numerous alternative embodiments of the "control circuit" include a subset of components 100, 130, and 140 or one or more portions of these components. For example, the system-on-chip 100 may be configured to receive data from a magnetic head 180 and to process data supplied to the magnetic head and to control the positioning of the magnetic head 180 relative to the storage medium 170 Can be regarded as an example of "control circuit ". The predetermined operation of the system-on-chip 100 in the storage device 10 of FIG. 1 may be performed by, for example, a random access memory 140 and / or a hard disk controller (not shown) executing code stored in the buffer memory 114 102, < / RTI > Thus, at least some of the control functions of the storage device 10 may be implemented, at least in part, in the form of software code.

It should also be appreciated that although the embodiment of FIG. 1 illustrates various components of a system-on-chip 100 implemented in a single integrated circuit chip, the system-on-chip 100 may include a random access memory 140 or preamplifier Other integrated circuits, such as circuitry 130, or portions thereof. Further, the hard disk controller 102, the host interface controller 104, the motor control circuit 106, and the master serial port control circuit 112 may be implemented as a microprocessor, a digital signal processor (DSP), an application specific integrated circuit such as an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or other types of integrated circuit architectures.

Although FIG. 1 illustrates an embodiment of the present invention with a single instance of each of storage medium 170, magnetic head 180, and positioning arm 185, in an alternative embodiment of the present invention, It will be appreciated that the device 10 includes multiple instances of one or more of these or other drive components. For example, in an alternate embodiment of the present invention, the storage device 10 may include a plurality of storage disks attached to the same spindle such that each storage disk rotates at the same speed, as well as a plurality of magnetic read / Recording head and an associated positioning arm.

Moreover, it will be appreciated that the read / write head herein can be implemented in the form of a combination of separate read and write heads when this term is commonly used. In particular, the term "read / write ", as used herein, refers to a read / write head in which only one or more read heads, only one or more write heads, a single head used for both read and write, Readable < / RTI > and / or writable so as to include a combination of read and write heads. Such a head may be, for example, a recording head having a wrap-around or side-shielded main pole, or another type of head suitable for reading and / or writing data to a storage disk Head.

Alternatively, the storage device 10 as shown in FIG. 1 may include other components in addition to, or on behalf of, those components specifically shown, including one or more elements of the type normally found in conventional storage devices. . These conventional components and other conventional components that are well understood by those skilled in the art are not described in detail herein. It should also be appreciated that the specific configuration of the components shown in Figure 1 is shown by way of example only. Those of ordinary skill in the art will appreciate that a variety of different storage device configurations may be used to implement embodiments of the present invention.

Figure 2 is a schematic diagram illustrating a more detailed embodiment of the storage device of Figure 1 with control circuitry supporting serial port communication between the controller and the preamplifier using a single bidirectional serial data line, in accordance with an embodiment of the present invention. Respectively. More specifically, FIG. 2 illustrates a write channel circuit 110, a master / slave serial port control circuit 112/132, a preamplifier circuit 130, a magnetic head 180, an analog A bus 200, and a digital bus 202. In Fig.

2, the analog bus 200 includes a plurality of signal lines 200-1, 200-2, and 100-3 that enable transmission of signals through the analog bus 200 between the write channel circuit 110 and the preamplifier circuit 130, 200-2, 200-3, and 200-4. 2, the signal lines 200-1, 200-2, and 200-3 are configured such that read data RD1, RD2, and RD3 during the read operation of the storage device 10 are transferred to the analog bus 200, Signal line that is transmitted from the preamplifier circuit 130 to the write channel circuit 110 via the read channel. The signal line 200-4 is a "write" signal line in which the write data WD is transferred from the write channel circuit 110 to the preamplifier circuit 130 via the analog bus 200. [ 2, the signal lines 200-1, 200-2, 200-3, and 200-4 are coupled between the write channel circuit 110 and the preamplifier circuit 130 via the analog bus 200 Is implemented as differential transmission lines that ensure noise margin and signal quality of the analog signal (or digital signal) being transmitted. In other embodiments, signal lines 200-1, 200-2, and 200-3 may be implemented using other common types of signal transmission lines suitable for a particular application.

The write channel circuit 110 and the preamplifier circuit 130 include a line driver / receiver 206/207/208 which is a line interface element that enables the transmission of signals through the analog bus 200. For example, the write channel circuit 110 includes a line driver 206 configured to drive a write data signal through a signal line 200-4, and the preamplifier circuit 130 includes a signal line 200-4, Lt; RTI ID = 0.0 > 207 < / RTI > In one embodiment of the present invention, since the write data (WD) signal is essentially digital in nature, the line driver / receiver 206/207 is capable of receiving the write data (WD) (Current Mode Logic, current mode logic).

The preamplifier circuit 130 also includes a line driver (not shown) including line drivers 208-1, 208-2 and 208-3 for driving the respective signal lines 200-1, 200-2, and 200-3. Circuit 208, In one embodiment of the present invention, the line driver circuit 208 is configured to drive the read signal RD through the respective signal lines 200-1, 200-2, and 200-3, And is executed using a configured analog line driver. In one embodiment, the signal lines 200-1, 200-2, and 200-3 are coupled to a variable gain amplifier (VGA) circuit in the analog "front end" processing circuit of the write channel circuit 110 Respectively.

2, the digital bus 202 is connected to a single bidirectional serial data line (not shown) that couples the master serial port control circuit 112 and the slave serial port control circuit 132 of the preamplifier circuit 130 202-1). In the embodiment of FIG. 2, a single bidirectional serial data line 202-1 may be used to transmit a high-speed bit stream that transmits a digital signal (such as control data and commands) via bidirectional serial data line 202-1 Lt; / RTI > as a differential transmission line. In another embodiment, a single bidirectional serial data line 202-1 may be implemented using other common types of signal transmission lines suitable for a particular application.

The serial port control circuitry 112/132 includes a bidirectional serial data line 202-1 in either "outbound" or "inbound" Lt; RTI ID = 0.0 > 210/212 < / RTI > The term "outbound " as used herein generally refers to data flow processing of serial bitstream data from the hard disk controller 102 to the preamplifier circuit 130 via the bidirectional serial data line 202-1, , While the term "inbound" as used herein generally refers to data flow processing of serial bit stream data from preamplifier circuit 130 to hard disk controller 102 via bidirectional serial data line 202-1 And the transmission direction.

As further shown in FIG. 2, the write channel circuit 110 further includes a read data circuit 214 and a write data circuit 216. The master serial port control circuit 112 includes a phase-locked loop (PLL) circuit 218, a first-in-first-out (FIFO) circuit 222, a decoder circuit 224, and a deserializer circuit 226, Quot; outbound "data processing path that includes an" inbound "data processing path that includes the FIFO circuit 228, encoder circuit 230, and serializer circuit 232, The master serial port control circuit 112 further includes a control logic circuit 234, an amplifier reset control circuit 236 and a switching circuit 220. The line multiplexing circuit 210 includes a line receiver 210-1 and a line driver 210-1 which are controlled (enabled / disabled) by a direction control signal (+ D / -D) output from the control logic circuit 234, 2). In one embodiment, the line multiplexing circuit 210 is implemented using, for example, CML.

The slave serial port control circuitry 132 (of the preamplifier circuit 130) is coupled to the "outbound" data processing path 242, which includes the PLL circuit 238, the control logic circuit 240, the deserializer 242, An "inbound" data processing path that includes a serializer circuit 246 and an encoder circuit 248, and a preamplifier reset control circuit 250. The line multiplexing circuit 212 includes a line driver 212-1 and a line receiver 212-1 which are controlled (enabled / disabled) by a direction control signal (+ D / -D) output from the control logic circuit 240, 2). In one embodiment, the line multiplexing circuitry 212 is implemented using, for example, CML.

The preamplifier circuit 130 includes a fly height control circuit 252, read circuits 254, 256 and 258, a write circuit 260, and a control register bank 262. The magnetic head 180 includes a gap sensor 180-1, a heater element 180-2, a plurality of read sensors 180-3, 180-4 and 180-5, and a write element 180-6 do. The various components of the magnetic head 180 may be implemented using structures and techniques well known in the art, and a detailed description of such components is not required to understand embodiments of the present invention.

In general, the read circuits 254, 256 and 258 and the respective read sensors 180-3, 180-4 and 180-5 are configured to read and process the magnetic signals representing the data stored in the storage medium 170 . The read sensors 180-3, 180-4 and 180-5 sense the magnetic signals present in the storage medium 170 and generate continuous fine analog signals representing the data stored in the storage medium 170 To output the sensed magnetic signal. The read circuits 254, 256 and 258 are connected to the read sensors 180-3, 180-4 and 180-5 as well as the sensor bias sources that support the read sensors 180-3, 180-4 and 180-5. And a low noise amplifier for amplifying the output analog signal. The read circuits 254, 256, and 258 may include other circuitry typically implemented to process the readback signal.

Figure 2 illustrates an embodiment of a multi-dimensional recording medium in which two or more read sensors are active during a read operation. Multidimensional recording techniques such as Two Dimensional Magnetic Recording (TDMR) have been developed to support higher bit densities in magnetic recording systems. According to the TDMR system, two or more readheads are used to read the same track (and adjacent tracks) with a predetermined read offset to provide some degree of interference cancellation. TDMR allows the use of efficient coding and signal processing algorithms that allow data bits to be stored at high density on magnetic storage disks and to be retrieved and decoded at an acceptable error rate. In the exemplary embodiment of Figure 2, the three read sensors 180-3, 180-4 and 180-5 are each in an active state during a read operation so that a plurality of signals RD1, RD2, RD3 which are simultaneously transmitted from the preamplifier circuit 130 to the write channel circuit 110 via the analog bus 200. [

In the write channel circuit 110, the read data circuit 214 receives and processes the reverse read signals RD1, RD2, and RD3 simultaneously. The read data circuit 214 includes various types of circuitry to condition and digitize analog reverse read signals RD1, RD2, and RD3 and to extract a digital representation of the originally written data. For example, the read data circuit 214 may be configured to receive the reverse read signals RD1, RD2, and RD3 received from the preamplifier circuit 130 using well known circuitry and analog signal processing techniques, Circuit. The read data circuit 214 includes an analog-to-digital converter circuit for digitizing an analog signal, and a data equalization circuit 210 for processing and decoding the digitized reverse read signal commonly included in the write channel and for reproducing the digital data originally recorded on the storage medium Circuitry, data detection circuitry, data decoding circuitry, data deserialization circuitry, clock recovery circuitry, and other circuitry such as other types of circuitry, and the details of which are set forth and described in connection with the embodiments of the invention described herein Not necessary.

In the write channel circuit 110, the write data circuit 216 receives the write data (from the internal bus 116) that is written to the storage medium 170, deserializes the write data, encodes it, Or otherwise convertible into a form that can be recorded on the storage medium 170. The write data circuit 216 outputs the encoded write data WD for transmission to the preamplifier circuit 130 via the analog bus 200. [ In the preamplifier circuit 130, the recording circuit 260 receives the encoded recording data WD and further processes the encoded recording data WD for recording in the storage medium 170 as desired. The write circuit 260 is also configured to drive the write element 180-6 in the magnetic head 180 for writing to the storage medium 170. [

The fly height control circuit 252 is configured to controllably adjust the spacing (or fly height) of the surfaces of the magnetic head 180 and the storage medium 170. In general, the fly height control circuit 252, the spacing sensor 180-1, and the heater element 180-2 are coupled to the components of the write channel circuit 110 and to the hard disk controller 102 In conjunction with the operating firmware, it is configured to keep the head-to-disk spacing required for high-density recording constant and low, using known techniques.

In general, the serial port control circuitry 112/132 outputs a digital signal via the bidirectional serial data line 202-1 in the "outbound" direction towards the preamplifier circuit 130 or the " Inbound "direction as well as a " inbound " direction. The serial port control circuitry 112/132 and the bidirectional serial data line 202-1 provide a high speed bidirectional serial port framework used to perform preamplifier register setup and access operations as well as interrogation functions do. In another embodiment, a high-speed bidirectional serial port framework is traditionally performed by dedicated exclusive-side line 204 and another dedicated serial port control line that controls register access and sequencing functions in preamplifier circuit 130 It can also be used to use control functions.

For example, to direct the digital signal to the preamplifier circuit 130 in the "outbound" direction via the bidirectional serial data line 202-1, the directional control (output from the control logic circuit 234/240) Signal + D / -D is set to logic "1 ", which enables the line driver 210-2 and the line receiver 212-2 and the line receiver 210-1 and the line driver 212- 1). As a result, the master serial port control circuit 112 takes charge of controlling the bidirectional serial data line 202-1, which transfers the digital signal to the preamplifier circuit 130. [ On the other hand, in order to transmit a digital signal from the preamplifier circuit 130 in the "inbound" direction, the direction control signal (+ D / -D) signal is set to a logic "0 " Disables line receiver 212-2 and enables line driver 212-1 and line receiver 210-1. As a result, the slave serial port control circuit 132 takes charge of controlling the bidirectional serial data line 202-1, which transmits the digital signal from the preamplifier circuit 130. [

In the master serial port control circuit 112, the PLL circuit 218 receives a clock signal for controlling the operation of the various circuit components 222, 224, 226, 228, 230, 232 and 234 of the master serial port control circuit 112 (CLK1). The clock signal CLK1 is generated based on the reference clock signal REF applied from the output of the switching circuit 220 to the reference input port of the PLL circuit 218. [ In particular, the reference clock signal REF is one of a plurality of reference signals applied at the input of the switching circuit 220, such that the serial port control circuit 112/132 outputs the serial data stream to the bidirectional serial data line 202-1 Of the plurality of reference signals selectively output from the switching circuit 220 depending on whether the signals are transmitted in the "outbound" direction toward the preamplifier circuit 130 or the "inbound & It is one.

2, the switching circuit 220 includes a first input port (not shown) configured to receive a bit rate clock signal (Bit_Clock) that is transmitted to the master serial port control circuit 112 via an internal bus 116, . In one embodiment, the bit rate clock signal Bit_Clock is generated by a master PLL circuit in the hard disk controller 102 (FIG. 1) and transmitted to the master serial port control circuit 112 via the internal bus 116 Signal. The bit rate clock signal Bit_Clock is fixed or programmable and can be generated using any of a variety of techniques known to those of ordinary skill in the art. In addition, the switching circuit 220 includes a second input port configured to receive a serial bit stream transmitted from the preamplifier circuit 130 in the "inbound" direction via the bidirectional serial data line 202-1.

As will be described in more detail below, the switching circuit 220 is configured such that the master / slave serial port control circuit 112/132 outputs the digital signal to the " outbound "direction through the bidirectional serial data line 202-1, To the PLL circuit 218 as the reference clock signal REF by the control logic circuit 234 when transmitting the bit rate clock signal Bit_Clock to the circuit 130. [ During an "outbound" transmission, the PLL circuit 218 generates a clock signal CLK1 having a phase / frequency fixed to the phase / frequency of the port bitrate clock signal Bit_Clock, wherein the clock signal CLK1 is digital Is used to control the function to encode the signal and transmit it to the preamplifier circuit 130 via the bidirectional serial data line 202-1. In this regard, the frequency of "outbound" data processing / transmission is precisely set by the port bit rate clock signal (Bit_Clock).

On the other hand, when the serial port control circuit 112/132 is transmitting a digital signal from the preamplifier circuit 130 in the "inbound" direction through the bidirectional serial data line 202-1, The serial bit stream received from the PLL circuit 218 via the bidirectional serial data line 202-1 from the preamplifier circuit 130 by the logic circuit 234 is supplied to the PLL circuit 218 via the reference clock signal REF As shown in Fig. During the "inbound" transmission, the PLL circuit 218 generates a clock signal CLK1 having a phase / frequency that is fixed to the phase / frequency of the serial data stream transmitted from the preamplifier circuit 130, Is used to receive and decode the serial bit stream received from the preamplifier circuit 130. [

In the "outbound" data processing path of the master serial port control circuit 112, the FIFO circuit 228 is coupled to the internal bus 116 via the internal bus 116, for example, from the hard disk controller 102 The FIFO circuit 228 is configured to receive and temporarily store digital information signals (e.g., bytes of register data, control characters, etc.). In one embodiment of the present invention, the FIFO circuit 228 includes a 9- Buffer, where each character (byte) is 8-bit and the ninth bit (most significant bit) is used as a Flag Bit (flag bit). As will be described in more detail below with reference to Figure 4 For example, the Flag Bit may be used as an indicator (e.g., set to logic "1 ") indicating an" inbound "transmission to control logic circuitry 234 requested by hard disk controller 102 And the assertion of the Flag Bit is used in the preamplifier (E. G., The generation of a "redirecting control character ") that causes the circuit 130 to take control of the bidirectional serial data line 202-1 and transmit information to the hard disk controller 102 as requested, .

In addition, in the "outbound" data processing path of the master serial port control circuit 112, the encoder circuitry 230 is configured to access and encode the digital information signals stored in the FIFO circuitry 228. The serializer circuit 232 is configured to serialize the encoded digital information signal to a serial bit stream (of control and / or data characters) for transmission to the preamplifier circuit 130 via the bidirectional serial data line 202-1 do.

In addition, in the "outbound" data processing path of the slave serial port control circuit 132, the deserializer 242 is configured to deserialize the serial bit stream received via the bidirectional serial data line 202-1 , The decoder circuit 244 is configured to decode the deserialized bit stream output from the deserializer 242. The decoded data output from the decoder circuit 244 is transferred to the control register bank 262 via the parallel data bus 264 and written to one or more target registers, for example, in the control register bank 262.

In the "inbound" data processing path of the slave serial port control circuit 132, the encoder circuit 248 is configured to encode the digital information signal. The digital information signal may be, for example, one or more bytes of register data read from one or more registers of the control register bank 262 via the parallel data bus 266. The serializer circuit 246 is configured to serialize the encoded digital signal (output from the encoder circuit 248) into a serial bit stream for transmission over the bidirectional serial data line 202-1.

Further, in the "inbound" data processing path of the master serial port control circuit 112, the deserializer circuit 226 receives the serial bit stream < RTI ID = 0.0 > To deserialize. The decoder circuit 224 is configured to decode the deserialized bit stream into data bytes that are temporarily stored in the FIFO circuit 222 for later access by, for example, the hard disk controller 102 do. The PLL circuit 218 and deserializer circuit 226 work together to convert the serial bit stream into parallel data using appropriate clock-data-recovery (CDR) techniques.

In the slave serial port control circuit 132, the PLL circuit 238 receives a clock signal CLK2 that controls the operation of the various circuit components 240, 242, 244, 246, and 248 of the slave serial port control circuit 132, . When the serial port control circuit 112/132 is configured to transmit the serial bit stream in the " outbound "direction to the preamplifier circuit 130 via the bidirectional serial data line 202-1, the PLL circuit 238 As an input, an "outbound" serial bit stream received via a bidirectional serial data line 202-1 is received and the phase / frequency is calibrated to produce a "fixed" phase / frequency to the phase / frequency of the received serial bit stream And generates a clock signal CLK2. During an "outbound" transmission, the clock signal CLK2 is supplied to the pre-amplifier circuit 130 via the bidirectional serial data line 202-1 by the deserializer 242 and the decoder circuit 244, Receive and decode.

On the other hand, when the serial port control circuit 112/132 is configured to transmit the digital signal in the "inbound" direction from the preamplifier circuit 130 via the bidirectional serial data line 202-1, Generates a control signal Hold that causes the PLL circuit 238 to stop adjusting the phase and frequency and keep the clock signal CLK2 as a "static" clock signal (i.e., the clock signal CLK2 is / RTI > is maintained at the same phase / frequency of the clock signal CLK2 present at the time the control signal Hold is asserted). In other words, when the control signal Hold is asserted, the phase / frequency calibration of the PLL circuit 238 is stopped so that a voltage-controlled oscillator (VCO) of the PLL circuit 238 Freewheel "to a nominal baud rate of a previously received" outbound "serial bit stream. In this regard, when transmitting a digital signal in the "inbound" direction, the clock signal CLK2 is held at a constant phase / frequency and the digital signal is encoded, serialized by the encoder circuit 248 and the serializer circuit 246 And from the preamplifier circuit 130 via bidirectional serial data line 202-1.

In one embodiment of the present invention, the PLL circuit 238 is implemented using an analog PLL framework discussed in more detail below with reference to FIG. The analog embodiment of the PLL circuit 238 can be used to recognize a limited digital capability (instead of a digital embodiment) in many analog-centric BiCMOS processes typically used in the manufacture of preamplifiers for data storage devices. However, in another embodiment of the present invention, the PLL circuit 238 may be implemented using a digital PLL framework.

In one embodiment of the present invention, the encoder circuits 230 and 248 and decoder circuits 224 and 244 of the master / slave serial port control circuit 112/132 use the 8B / 10B coding protocol to perform encoding and decoding functions . As is known in the art, the 8B / 10B coding protocol is a serial bitstream transmission protocol in which 8-bit data bytes are converted to 10-bit transmission characters. In particular, in 8B / 10B coding, the data bytes (8-bit data) are encoded using one of 256 of 1024 possible 10-bit code characters conforming to the d, k = 0,4 constraint. The k = 4 constraint of the 8B / 10B code allows the clock to be reliably extracted from the encoded data stream. The dc spectral null characteristics of the 8B / 10B code may or may not be implemented in embodiments of the present invention. The control and framing characters are selected from the remaining 10-bit symbols. For example, the "direction switch" control signal generated in response to the asserted Flag Bit may be a predefined 8B / 10B control character. In an "outbound" transmission, 8B / 10B coding essentially provides an embedded clock, where every 10 bits in a serial bitstream represents one 8B / 10B data or control character.

3 is a flow diagram of a method for implementing serial port communication between a controller and a preamplifier using a single bidirectional serial data line, in accordance with an embodiment of the present invention. More specifically, Figure 3 illustrates a method of controlling a serial port that selectively transmits a digital signal between a controller and a preamplifier via a bidirectional serial data line, in accordance with an embodiment of the present invention. In general, a method of controlling a serial port includes transmitting a serial bit stream from a controller to a preamplifier via a bidirectional serial data line (block 300), and using a phase-locked loop in a preamplifier to generate a clock signal- (Block 302) generating a signal from a controller based on a bit rate of a serial bit stream transmitted over a bidirectional serial data line, and generating a bidirectional serial data line from the controller using a clock signal in the preamplifier (Block 304) receiving and deserializing the serial bits that are transmitted over the link.

As discussed above, in the context of the exemplary embodiment of Figures 1 and 2, the process flow of blocks 300, 302, 304 is such that a digital information signal (e.g., register address information and register data) To the master / slave serial port control circuit 112/132 in the "outbound" direction. On the other hand, the process flow of blocks 306, 308, 310, and 312 (as discussed below) may be performed by, for example, Slave serial port control circuit 112/132, which is implemented to transmit in the "inbound" direction from the host controller 130 to the hard disk controller 102.

More specifically, referring to FIG. 3, a method of controlling a serial port further includes transmitting a redirect control signal to a preamplifier via a bidirectional serial data line (block 306). After detecting the directional switching control signal by the preamplifier, the preamplifier generates a control signal (referred to herein as the Hold signal) to stop the phase and frequency regulation of the phase-locked loop circuit of the preamplifier, And holds the fixed clock signal output from the phase-locked loop (block 308). The preamplifier then takes control of the bidirectional serial data line that transfers the digital signal from the preamplifier to the controller (block 310). The fixed clock signal is used to serialize the data and transmit it from the preamplifier to the controller via the bidirectional serial data line (block 312).

For illustrative purposes, a more detailed embodiment of the method of FIG. 3 will be discussed in more detail below with reference to the timing diagram shown in FIG. 4, where FIG. 4 illustrates a single bi- And schematically illustrates a method of controlling a serial port that selectively transmits a digital signal between a controller and a preamplifier using a serial data line. Furthermore, the embodiment of FIGS. 3 and 4 can be used in the context of the operating mode of the serial port control circuit 112/132, which controls bidirectional transmission of the digital signal via the bidirectional serial data line 202-1, Will be further discussed with reference to FIG.

Generally, FIG. 4 illustrates an example of a serial bitstream 400 that is transmitted in an "outbound" direction and an "inbound" direction through a bidirectional serial data line 202-1 (as indicated by the arrows). 4 includes an "outbound" serial bitstream 400-1, blocks 418, 420, and 422 that include blocks 402, 404, 406, 408, 410, 412, 414, and 416 Outbound "bitstream 400-3, which includes blocks 424,426 and 428, and" inbound " 4 is a control signal for controlling the transmission of the serial bit streams 400-1, 400-2, and 400-3 via the bidirectional serial data line 202-1, for example, a slave serial port control The HOLD control signal 430 generated by the control logic circuit 240 in the circuit 132, the direction control signal 440 (+ D generated by the control logic circuit 234 in the master serial port control circuit 112) / D) generated by the encoder circuit 230 in the slave serial port control circuit 132 and the direction control signal 450 (+ D / -D) generated by the encoder circuit 230 in the slave serial port control circuit 132.

4, the "outbound" serial bit stream 400-1 includes a synchronization bit pattern 402, register write address / data pairs 404/406 and 408/410, Conversion control character 412, register read address information 414, and associated byte count information 416. [ In general, the synchronization pattern 402 is transmitted to the preamplifier circuit 130 and is applied to the positive phase of the PLL circuit 238 in the preamplifier circuit 130, using techniques known to those skilled in the art / RTI > includes a bit pattern used in the slave serial port control circuit 132 to implement the frequency / "full-in" This phase / frequency "pull-in" is needed when there is no precise reference clock in the preamplifier circuit 130 and the output clock CLK2 of the PLL circuit 238 is "outbound " "To" serial bit stream 400-1. Depending on the implementation, the synchronization pattern 402 may include a "constant-frequency preamble" and an 8B / 10B "frame" character that can synchronize the PLL circuit 238 and mark the end of the preamble and the beginning of the bitstream of data .

During the time period from t0 to t1 when the "outbound" serial bit stream 400-1 is transmitted to the preamplifier circuit 130 (as shown further in FIG. 4) (Which is de-asserted) to enable the PLL circuit 238 to perform phase / frequency calibration and the clock signal CLK2 to be < RTI ID = 0.0 > (Which is generated by the respective control logic circuits 234 and 240 in the master / slave serial port control circuit 112/132) to be maintained phase-locked to the serial bit stream 400. Also, Signals 440 and 450 remain at a logic "1" level. In this state, line driver 210-2 and line receiver 212-2 are activated to support "outbound" Driver 212-1 and line receiver 210-1 are deactivated (see FIG. 2).

4, the "outbound" serial bit stream 400-1 includes register address information < RTI ID = 0.0 > (404 and 408), and register data (406 and 410) contain the actual register data that is written into the register at each register address (404 and 408). 2, hard disk controller 102 writes 8-bit information (bytes) to 9-bit-wide FIFO circuitry 228, where the example For example, the first 8 bits represent register data / address information, and the ninth bit is a Flag Bit (logic 1) asserted to indicate the redirection at the serial port.

As discussed further above with reference to FIG. 2, encoder circuit 230 encodes each 8-bit output (byte) into a 10-bit character using the widely known 8B / 10B coding protocol. The encoded 10-bit characters (e.g., represented by blocks 404, 406, 408, and 410) are serialized through serializer circuit 232 and transmitted through bidirectional serial data line 202-1 Lt; / RTI > Within the preamplifier circuit 130, the serialized data stream is input to a deserializer 242 and a PLL circuit 238 that provide a deserialized bit-rate clock (CLK2). Each 10-bit character is decoded by a decoder circuit 244, which decodes the preamplifier configuration and control information into register address information used to store the preamplifier configuration and control information in the registers of the control register bank 262 and the corresponding (8-bit).

Although an address / register data pair is written to the register in the control register bank 262 in FIG. 4, other formats may be implemented. For example, a register write format including start-address / byte-count-N / byte 1 / byte 2 / ... / byte N may be used. In this embodiment, start-address indicates the address of the first register to be written, byte-count-N specifies the N sequential register addresses where data is written, where N is the first register address, And a sequence of N consecutive registers containing an address. The register data (byte 1 / byte 2 / ... / byte N) represents the actual data byte written to the specified N sequential register addresses. For example, assume that each register in control register bank 262 stores one byte of data. If start-address specifies a register address of 5 and byte-count-N specifies a value of 3, this command will cause the preamplifier circuit 130 to store byte 1 into a register at address 5 and then to the next two sequential registers 6 And the remaining register data byte 2 and byte 3 which are contents of 7.

When some register data is read from the control register bank 262 in the preamplifier circuit 130, the master serial port control circuit 112 sends the slave serial port control circuit 132 a direction switching control character 412 into an "outbound" serial bit stream 400-1. More specifically, in one embodiment of the present invention, the insertion of the direction control character 412 is performed by the hard disk controller 102 in the form of a Flag Bit (i. E. , ≪ / RTI > the ninth bit), which is logic "1 ". The asserted Flag Bit acts as an indicator to indicate to the control logic circuit 234 that an "inbound" transmission of the register data is attempted, for example, from the preamplifier circuit 130. For example, in one embodiment, the 8-bit character (with the asserted Flag Bit (ninth bit)) is accessed in the control register bank 262 with the register data accessed and transferred to the hard disk controller 102 Specifies the address of the register. When the control logic circuit 234 detects an asserted Flag Bit of a particular 8-bit character in the FIFO circuit 228, the control logic circuit 234 instructs the encoder circuit 230 Quot; redirection "control character (shown as a 4-bit " redirection " control character 412). In addition, as shown in the embodiment of FIG. 4, a 10-bit 8B / 10B encoded register read-address character 414 and a byte count character 416 follow the redirecting control character 412 .

In the preamplifier circuit 130, the decoder circuit 244 decodes and detects the redirection control character 412 received from the master serial port control circuit 112 and outputs a detection control signal to the control logic circuit 240 do. In response to the detection control signal, the control logic circuit 240 knows that the next character in the "outbound" serial bit stream 400-1 includes a read address character 414 and a byte count character 416 do. Thus, the control logic circuit 240 issues a command to access the contents of the specified register (s) and initiate a serial port redirection so that the accessed register (s) within the "inbound" serial bit stream to be transmitted from the preamplifier circuit 130 Thereby enabling transmission of the content.

In one embodiment of the invention, the read address control character 414 includes register address data that acts as a register read command and specifies the address of the register into which the data (or a pointer to another register) is read. In addition, the byte count character 416 specifies a plurality of consecutive register addresses to cause access to be initiated from the specified register address. For example, if the read address character 414 specifies a register address of 5 and the byte count character 416 specifies a value of 3, then the preamplifier circuit 130 will determine the contents of the register with address 5, and The contents of the next two sequential registers 6 and 7 will be accessed and read. A byte count value of 1 indicates that only the contents of the register of the register address specified by the read address character 414 are to be accessed and returned to the hard disk controller 102.

During transmission of the "outbound" serial bit stream 400-1, the PLL circuit 238 in the preamplifier circuit 130 is phase locked to the serial bit stream received via the bidirectional serial data line 202-1 It remains. 4, at time tl, immediately after the read-address and byte count characters 414 and 416 are transmitted, the control logic circuit 234 in the master serial port control circuit 112 receives the direction control signal < RTI ID = 0.0 > (+ D / -D) to logic 0 level so that the master serial port control circuit 112 stops transmitting the outbound serial bit stream, and the bidirectional serial data line 202-1 The control of the vehicle is stopped.

Also at time t1, immediately after the read-address and byte count characters 414 and 416 are transmitted, the control logic circuit 240 in the slave serial port control circuit 132 receives the HOLD control signal 430 Transition to Logic 1 level. When the HOLD control signal 430 is asserted, the PLL circuit 238 stops the phase / frequency calibration and returns to the PLL circuit 238 which freewheels at the nominal baud rate of the previously received outbound serial bit stream 400-1 And outputs a fixed clock signal CLK2 having a phase and a frequency generated at the output of the voltage-controlled oscillator. In this state, the fixed clock signal CLK2 provides a reference to the "inbound" serial bit stream 400-2 sent from the preamplifier circuit 130 to the hard disk controller 102. [

During the time period from t1 to t2 shown in FIG. 4, the slave serial port control circuit 132 uses the fixed clock signal CLK2 output from the PLL circuit 238 (under the control of the control logic circuit 240) (From the control register bank 262) to transfer the data to the hard disk controller 102 via the bidirectional serial data line 202-1 by performing a predetermined sequencing operation. Once the requested register data has been accessed, encoded and serialized (via the encoder circuit and serialization circuits 248 and 246), at time t2, the control logic circuit 240 sets the direction control signal 450 to a logic 0 Level so that the slave serial port control circuit 132 takes control of the bidirectional serial data line 202-1 and sends the "inbound" serial bit stream 400-2 to the master serial port control circuit 112 It begins to transmit.

In the embodiment of FIG. 4, the "inbound" serial bit stream 400-2 includes a synchronization pattern 418 and encoded data characters 420 and 422. Synchronization pattern 418 is optionally used in master serial port control circuit 112 to derive "pull-in" of the phase / frequency of PLL circuit 218. As described above, during an "inbound" transmission, the switching circuit 220 is selectively controlled to provide an "inbound" serial bit stream as a reference input of the PLL circuit by a direction control signal (+ D / And generates a clock signal CLK1 that is used to receive and decode the inbound serial bit stream transmitted from the preamplifier circuit 130 via the bidirectional serial data line 202-1. In one embodiment, the synchronization pattern 418 includes a bit pattern that is used as a reference signal by the PLL circuit 218 that generates the clock signal CLK1 phase locked to the "inbound" serial bit stream 400-2 do.

In one embodiment of the present invention, the synchronization pattern 418 is generated by a PLL circuit 218 in the master serial port control circuit 112, which is configured to < RTI ID = 0.0 > When implemented using work, it can be a single 8B / 10B control character. As an example, the PLL circuit 218 may be a digital asynchronously-sampled immediate-full-in PLL frame that can be nearly instantaneously phase-locked to an "inbound" serial bit stream for gigabit- (Using a digital asynchronously-sampled instant-pull-in PLL framework).

4, the encoded data characters 420 and 422 of the "inbound" serial bit stream 400-2 are accessed from two different registers, and the encoder circuit 248 is used to read 8B / 10B 10-bit character and then includes the register data serialized using the serializer circuit 246 under the sequencing control of the fixed clock signal CLK2 output from the "frozen" PLL circuit 238 do. During time periods t2 to t3 in FIG. 3, the encoded data characters 420 and 422 are transmitted in serial to the master serial port control circuit 112, where the serial bit stream is sent to the deserializer circuit 226 And decoded by the decoder circuit 224 to 8-bit bytes and stored in the "inbound" data FIFO circuit 222 for later access by the hard disk controller 102. [

4, at time t3 after transmission of the inbound serial bit stream 400-2, the control logic circuit 240 in the slave serial port control circuit 132 receives the direction control signal 450 To the logic one level so that the slave serial port control circuit 132 stops controlling the bidirectional serial data line 202-1. The slave serial port control circuit 132 knows a priori how much information bits are to be transmitted (blocks 420 and 422) in response to previously received outbound requests (blocks 414 and 416) The serial port control circuit 132 immediately stops controlling the bidirectional serial data line 202-1 after the last bit of the "inbound" serial bit stream 400-2 is transmitted.

During time periods t3 to t4, the master serial port control circuit 112 operates to complete the processing of the "inbound" serial bit stream 400-2 and prepares for another outbound transmission. At time t4 the control logic circuit 240 in the slave serial port control circuit 132 transitions the HOLD control signal 430 to a logic zero level so that the PLL circuit 238 performs a phase / I can do it. At time t4 the control logic circuit 234 in the master serial port control circuit 112 transitions the direction control signal 440 to a logic one level so that the master serial port control circuit 112 is bi- And controls the serial data line 202-1. Furthermore, when the direction control signal 440 is asserted, the switching circuit 220 selectively applies a bit-rate clock (Bit-Clock) to the PLL circuit 218 as a reference clock signal REF as discussed.

4, at time t4, the master serial port control circuitry begins transmitting an "outbound" serial bit stream 400-3 to the preamplifier circuitry 130. As shown in FIG. In an exemplary embodiment, the "outbound" serial bit stream includes a synchronization pattern 424, which is similar to the "outbound" serial bit stream 400-1 as discussed above, Sequence 426,428.

In this state, assuming a negligible "phase slip" by the PLL circuit 238 during the "Hold" state, the PLL circuit 238 generates an "outbound" encoded character 426 And 428 to deserialize and decode the clock signal CLK2. In such a case, the phase / frequency of the clock signal CLK2 is used as in the master serial port control circuit 112, which starts to encode and serialize the encoded characters 426 and 428 at time t4 / RTI > will likely be similar to the phase / frequency of the clock signal CLK1 (based on the clock signal Bit_Clock). This assumption is based on the fact that the clock signal CLK2, which was held in a fixed state during the time period from t1 to t4, is already phase locked to the clock signal CLK1 used to encode and serialize the previous outbound serial bit stream 400-1 It is valid.

However, when a relatively large amount of "inbound" character is transmitted from the preamplifier circuit 130, a significant phase slip due to PLL circuit phase slip during the Hold mode is generated, and at time t4, ) Synchronization pattern 424 synchronizes the phase / frequency of the clock signal CLK2 with the nominal baud rate of the clock signal CLK1 currently used to transmit the outbound serial bit stream 400-3 Lt; / RTI > In another embodiment, a phase shift of approximately 1/4 bit-time compared to the state of the PLL circuit 238 at the end of the outbound serial bit stream 400-1 may be used to synchronize the clock signals CLK1 and CLK2 have. If this tolerance can not be maintained, it is possible to attach a phase-trim field before the resumed outbound stream 400-3.

5 schematically illustrates an embodiment of a phase-locked loop circuit that may be implemented in a preamplifier that supports serial port transmission between a controller and a preamplifier over a single bidirectional serial data line, in accordance with an embodiment of the present invention. For example, FIG. 5 shows an embodiment of a PLL circuit 238 implemented in the slave serial port control circuit 132 shown in FIG. 5, PLL circuit 238 includes a phase detector circuit 500, a hold control circuit 510, a charge pump circuit 520, a low pass filter circuit 530, and a voltage controlled oscillator controlled oscillator (VCO) circuit 540. As described above, in one embodiment of the present invention, the PLL circuit 238 may be implemented using an analog PLL framework (not shown) in the case where the preamplifier circuit 130 is implemented using a process technology that is optimized for transmission and / . For example, the PLL circuit 238 may be implemented using, for example, a bipolar device, a CMOS device, or a combination of a bipolar device and a CMOS device.

The hold control circuit 510 includes a first control gate 512 and a second control gate 514. In one embodiment, the control gates 512 and 514 are coupled to an "OR-NOR" circuit configured to enable or disable the charge pump circuit 520 based on the logic level of the HOLD control signal input to the hold control circuit 510. [ Gate. The charge pump circuit 520 includes a first current source 522 (which produces a source current I _UP ), a second current source 524 (which produces a sink current I _DOWN ), and a second transistor T4), which implement a current-to-charge charge pump framework. In one embodiment shown in Figure 5, the bipolar transistors T1 and T2 are PNP transistors and the bipolar transistors T3 and T4 are NPN transistors. The low-pass filter circuit 530 is connected to the output node 550 of the charge pump circuit 520. In one embodiment, the low-pass filter circuit 530 is a proportional-integral + HF pole compensating network that includes a resistor R1 and capacitors C1 and C2. The VCO circuit has a high input impedance control port 542 connected to the output node 550 of the charge pump circuit 520.

5, each control gate 512 and 514 has an input port configured to receive a HOLD control signal (generated and output from control logic circuit 240 as shown in FIG. 2) have. The first control gate 512 also has an input port connected to the output port 502 of the phase detector circuit 500 and configured to receive the control signal UP generated and output from the phase detector circuit 500 Have. Similarly, the second control gate 514 is coupled to the output port 504 of the phase detector circuit 500 and is coupled to an input port < RTI ID = 0.0 >Lt; / RTI >

The first control gate 512 also has a first output port (NOR output) connected to the base terminal of the bipolar transistor t1 and a second output port (OR output) connected to the base terminal of the bipolar transistor T2 have. The second control gate 514 has a first output port (NOR output) connected to the base terminal of the bipolar transistor T4 and a second output port (OR output) connected to the base terminal of the bipolar transistor T3. In an embodiment of the present invention, as indicated by the "round point" inputs of the first and second control gates 512 and 514 shown in FIG. 5, the input ports of the first and second control gates 512 and 514 Is an inverting input.

During the "outbound" transmission of the digital signal through the bidirectional serial data line 202-1, the hold control circuit 510 causes the PLL circuit 238 to perform phase / frequency calibration to generate the bidirectional serial data line 202-1, To generate a clock signal CLK2 that remains phase locked to the "outbound" serial bit stream received via the clock signal CLK2. In particular, the phase detector circuit 500 includes an "outbound" serial bit stream (received by the preamplifier circuit 130 via the bidirectional serial data line 202-1) And receives the clock signal CLK2 as an input. The phase detector circuit 500 is configured to generate and output the pulsed control signals UP and DOWN at each of the output ports 502 and 504 of the phase detector circuit 500. Generally, the phase detector circuit 500 is configured to generate the control signals UP and DOWN based on the phase difference between the received serial bit stream and the clock signal CLK2 using any suitable phase detector circuit framework . In one embodiment, the relative pulse widths of the control signals UP and DOWN are proportional to the phase difference between the received serial bit stream and the clock signal CLK2, as detected by the phase detector circuit 500. Furthermore, in one embodiment of the invention, the control signals UP and DOWN are considered to be asserted to a logic "0" level, as indicated by the output ports 502 and 504 of the rounded circle of the phase detector circuit 500 do.

During the "outbound" transmission, the HOLD control signal input to the hold control circuit 510 is maintained at a logic zero level. In this state, at least one inverting input of the first and second control gates 512 and 514 is maintained at a logic one level, causing the NOR output of the first control gate 512 to remain at a logic one level, 2 control gate 514 remains at a logic 0 level. As such, during an "outbound" transfer, the bipolar transistors T1 and T3 of the charge pump circuit 520 remain OFF.

During the "outbound" transfer, the hold control circuit 510 receives the control signals UP and DOWN from the phase detector circuit 500 and controls the charge pump circuit 520 according to the logic levels of the UP and DOWN control signals. Of the bipolar transistors T2 and T4. For example, when the UP control signal is asserted to a logic 0 level (and the HOLD control signal is a logic 0), the OR output of the first control gate 512 will be at a logic 0 level, T2 will be turned on. On the other hand, when the UP control signal is at a logic 1 level (and the HOLD control signal is logic 0), the OR output of the first control gate 512 will be at a logic 1 level so that the bipolar transistor T2 is turned Off. Similarly, when the DOWN control signal is asserted to a logic 0 level (and the HOLD control signal is a logic 0), the NOR output of the second control gate 514 will be at a logic one level so that the bipolar transistor T4 Will turn on. On the other hand, when the DOWN control signal is at a logic 1 level (and the HOLD control signal is a logic 0), the NOR output of the second control gate 514 will be at a logic 0 level so that the bipolar transistor T4 is turned Off.

In this regard, when the charge pump circuit 520 is enabled during an "outbound" transfer, the charge pump circuit 520 generates the first current source 522 and / or the second current source 522 based on the logic levels of the control signals UP and DOWN. Or a second current source 524 to charge / discharge the voltage at the output node 550. In particular, UP control signal when set to a logic-zero level, the bipolar transistor (T2) is activated, this is the first current source 522, the source current (I _UP) by said then let to be coupled to the output node (550) To charge the output node 550. Similarly, when the DOWN control signal is set to the logic 0 level, the bipolar transistor T4 is activated, which allows the second current source 524 to be connected to the output node 550, thereby causing the sink current current I _DOWN (Which injects a negative charge at the output node 550).

The charge injected into the output node 550 by the charge pump circuit 520 is filtered by the low pass filter circuit 530 to be supplied to the control node 542 of the VCO circuit 540 at the output node 550, . The VCO circuit 540 generates an output clock signal CLK2 having a frequency based on the level of the control voltage applied to the control input port 542 of the VCO circuit 540. [ The clock signal CLK2 is fed back to the phase detector circuit 500 using a feedback loop. During operation of the PLL circuit 238, if the clock signal CLK2 is not phase aligned with the received serial bit stream, the phase detector circuit 500 generates the UP and DOWN control signals and accordingly the output clock signal CLK2 (I.e., phase-locked) to the received serial bit stream. Once the clock signal CLK2 is phase aligned with the received serial bit stream, the clock signal CLK2 is used to control the sequencing operation in the slave serial port control circuit 132 as discussed above.

On the other hand, during an inbound transmission in which the preamplifier takes control of the bidirectional serial data line 202-1, the HOLD control signal input to the hold control circuit 510 transitions to a logic one level. In this state, at least one inverting input of the first and second control gates 512 and 514 is maintained at a logic 0 level, so that the OR output of the first control gate 512 is maintained at a logic 1 level, Causing the NOR output of the second control gate 514 to remain at a logic 0 level. Thus, during an inbound transfer, the bipolar transistors T2 and T4 of the charge pump circuit 520 are maintained in the off state, which causes the voltage level on the output node 550 to be maintained as it existed prior to the assertion of the HOLD control signal do. In this "hold" state, the charge pump circuit 520 is disabled to cease phase / frequency calibration and the control voltage on the output node 550 applied to the control input port 542 of the VCO circuit 540 is constant Lt; / RTI > Thus, the VCO circuit 540 outputs a constant (fixed) clock signal CLK2 based on the control voltage at the node 550. [ In one embodiment of the invention, the control input 542 of the VCO circuit 540 is designed such that the high input impedance remains at the voltage level at the output node 550 during the "hold" state.

Master / slave serial port control circuitry 112/132, as discussed above with reference to FIG. 2, may be used to control the preamplifier circuitry 130, for example, based on the Force_Reset control signal generated by the hard disk controller 102 And preamplifier reset control circuits 236 and 250 for performing a forced reset. For example, a forced reset of the preamplifier circuit 130 may be desirable to restore from, for example, lockup conditions, or to force immediate error recovery. Figures 6 and 7 schematically illustrate a method for resetting a preamplifier in accordance with an alternative embodiment of the present invention.

In particular, Figure 6 is a schematic circuit diagram illustrating a reset circuit for forcibly resetting the preamplifier, in accordance with an embodiment of the present invention. The preamplifier reset scheme shown in Figure 6 is based on puilsing the common-mode voltage on the differential serial data line to a level outside the nominal operating range of the common-mode voltage. Generally, FIG. 6 illustrates a CML implementation of bidirectional serial data line 202-1 and line multiplexing circuitry 210/212 of master / slave serial port control circuit 112/132 of FIG. The bidirectional serial data line 202-1 is shown as a differential transmission line including a differential pair (ZP, ZN). Moreover, the various line drivers / receivers 210-1, 210-2, 212-1 and 212-2 are shown as differential line drivers / receivers. For example, the line driver / receivers 210-1, 210-2, 212-1, and 212-2 may be configured such that the differential amplifier is coupled to a resistor-loaded CML amplifier technology-a differential signal via bidirectional serial data line 202-1 And driving a common mode voltage on the differential lines ZP, ZN to enable communication.

6 shows an embodiment of a preamplifier reset control circuit 610 executed in the master serial port control circuit 112 and a preamplifier reset control circuit 620 executed in the slave serial port control circuit 132 Respectively. The preamplifier reset control circuit 610 is configured to temporarily vary the level of the common mode voltage of the differential pair (ZP, ZN) in response to the assertion of the Force_Reset control signal. In one embodiment, the preamplifier reset control circuit 610 is implemented using first and second switch circuits and associated first and second tail current sources, wherein the first and second switch circuits < RTI ID = 0.0 > Due to the voltage source generated across the load resistance of the CML drivers 210-1 and 210-2 due to the current sources temporarily connected to the respective differential signal lines ZP and ZN, the common mode on the differential lines ZP and ZN Is a transfer gate controlled by a Force_Reset control signal that causes (e.g., increases) voltage variations.

되게 선택되는데, 여기서

는 차동 쌍(ZP, ZN)의 운용하는 공칭의 공통-모드 전압 레벨이며,

는 공통-모드 전압에서의 변동을 나타내는 것으로, 이는 검출되었을 때 전치 증폭기 회로(130)의 리셋을 유발한다. 동작 시, 노드(626)에서 전압은 차동 쌍(ZP, ZN)의 공통-모드 전압으로 유지된다. 공통-모드 전압이 기준 전압(VREF) 이상으로 증가(또는 이하로 감소)할 때, 비교기(624)가 트리거되며, Reset 제어 신호가 비교기(624)의 출력에서 생성된다. 로우 패스 필터(622)는 검출 프로세스에서 잡음 여유도를 개선한다. 전치 증폭기의 리셋 동작은 전치 증폭기 회로(130)가 "아웃바운드" 직렬 비트 스트림을 수신하도록 준비시키는데 사용될 수 있다. (In the slave serial port control circuit 132), the preamplifier reset control circuit 620 detects a change in the common mode voltage and outputs a reset control signal to the preamplifier circuit 130 to reset the preamplifier circuit 130 . 6, the pre-amplifier reset control circuit 620 includes a low-pass filter 622 and a comparator 624. The low- The low-pass filter 622 includes resistors R10 and R12 and a capacitor C10. Comparator 624 has a first (non-inverting) input coupled to node 626 of lowpass filter 622 and a second (inverting) input configured to receive reference voltage VREF. The reference voltage VREF is at a predetermined level

, Where

Is the nominal common-mode voltage level operated by the differential pair (ZP, ZN)

Indicates a variation in the common-mode voltage, which causes a reset of the preamplifier circuit 130 when it is detected. In operation, the voltage at node 626 is maintained at the common-mode voltage of the differential pair (ZP, ZN). When the common-mode voltage increases (or decreases below) the reference voltage VREF, the comparator 624 is triggered and a Reset control signal is generated at the output of the comparator 624. The low pass filter 622 improves the noise margin in the detection process. The reset operation of the preamplifier can be used to prepare the preamplifier circuit 130 to receive an "outbound" serial bit stream.

7 is a schematic circuit diagram showing a reset circuit for forcibly resetting a preamplifier according to another embodiment of the present invention. The preamplifier reset scheme shown in FIG. 7 maintains a logic level on the bidirectional serial data line for a predetermined period of time, detects a run-length violation and initiates a preamplifier reset operation to force- It is based on a control method that violates the length. In an embodiment in which 8B / 10B encoding is performed, the line-length violation is a period that does not have a transition on the bidirectional serial data line 202-1 for some period of time that is longer than the maximum span allowed under the 8B / 10B encoding rule It is accomplished by forcing.

Generally, FIG. 7 illustrates a CML implementation of bi-directional serial data line 202-1 and line multiplexing circuit 210/212 of master / slave serial port control circuit 112/132 of FIG. 2 Where bidirectional serial data line 202-1 is shown as a differential transmission line including differential pair ZP and ZN and line driver / receivers 210-1, 210-2, 212- 1 and 212-2 are shown as a differential line driver / receiver.

7 shows an embodiment of the preamplifier reset control circuit 710 executed in the master serial port control circuit 112 and the preamplifier reset control circuit 720 executed in the slave serial port control circuit 132 do. The preamplifier reset control circuit 710 includes a first input configured to receive the Force_Reset control signal and a second input configured to receive an "outbound" serial bit stream transmitted over the bidirectional serial data line 202-1 . When the Force_Reset control signal is asserted to a logic one level, the output of OR gate 710 will remain at a logic one level, regardless of the logic level of the data bits of the serial bit stream input to OR gate 710. As such, the logic level on the bidirectional serial data line will remain at logic one level for a predetermined time period during which the Force_Reset control signal remains asserted, thus causing a line length violation in the bidirectional serial data line. In one embodiment, in which the 8B / 10B encoding is used to transmit a serial bit stream over the bidirectional serial data line 202-1, the Force_Reset control signal is applied to the encoded serial bit 202-1 transmitted via the bidirectional serial data line 202-1 The stream d, k = 0, 4 - a meaningful length constraint It remains asserted for a given time period causing the violation.

(In the slave serial port control circuit 132), the preamplifier reset control circuit 720 detects a line-length violation in the received serial bit stream and outputs a Reset control signal to the preamplifier circuit 130, 130 to start resetting. 7, the pre-amplifier reset control circuit 720 includes a low-pass filter 722 and a comparator 724. The low- The low-pass filter 722 includes a resistor R20 and a capacitor C20. Comparator 724 has a first (non-inverting) input coupled to node 726 of lowpass filter 722 and a second (inverting) input configured to receive a threshold voltage VT. A comparator 724 is configured to compare the voltage on node 726 of lowpass filter 722 with a threshold voltage VT to determine when the run-time violation will occur.

7 illustrates an exemplary waveform generated at node 726 in response to a waveform at node 728 as well as an exemplary waveform generated at node 728, Respectively. 7, the logic level at the output node 728 of the line receiver 212-2 is at logic level 1 (in response to the assertion of the Force_Reset control signal from time tl to t2) during the time period < RTI ID = Which causes the voltage at node 726 to rise to the threshold voltage VT. When the voltage at node 726 rises to the VT level, comparator 724 is triggered and a Reset control signal is generated at the output of comparator 724. In practice, the preamplifier reset control circuit 720 functions as an asynchronous timer, where the asynchronous timer is reset each time a rising edge is generated in the received serial bit stream, and when the asynchronous timer overflows (i.e., ), It is assumed that a run-time violation that has been forcibly performed has occurred and has begun to reset the preamplifier circuit 130. The low pass filter 722 improves the noise margin in the detection process.

In another embodiment of the present invention, a data storage device as shown in Figures 1 and 2 includes an analog bus 200 that supports communication between various components of a data storage device, a digital bus 202, Lt; RTI ID = 0.0 > 204 < / RTI > For example, although FIG. 2 is shown as being implemented as bidirectional serial data lines 200-1, 200-2, 200-3, and 200-4, analog bus 200 is described as "Multiplexed Directional analog bus using circuits and methods as disclosed in commonly owned U. S. Patent Application Serial No. 14 / 267,354, filed under the name " Communication In A Storage Device, Multiplexed in Storage Device " For example, this application discloses an analog bus framework in which a plurality of signal lines of an analog bus are controlled by a multiplexing circuit, wherein the multiplexing circuit Directional readout of the read and write information signals through one or more signal lines of the analog bus between the write channel circuit and the preamplifier circuit, The multiplexed analog bus framework allows a read data signal to be transferred in one direction through the read signal line during a read operation while a write control signal during a write operation is read in the opposite direction Lt; / RTI >

In another embodiment of the present invention, one or more control signals transmitted over the mantissa sub-line 204 are transferred via the bidirectional serial data line 202-1 under the control of the master / slave serial port control circuit 112/132, May be transmitted between the disk controller 102 and the preamplifier circuit 130. [ For example, the one or more mantissa control signals may be, for example, as described in " Preamplifier-To-Channel Communication in a Storage Device, Preamplifier-to-Channel Communication in Storage Device " U.S. Patent Application No. 13 / 650,474, and U.S. Patent Application No. 13 / 719,615, filed on December 19, 2012 entitled " Tag Multiplication Via A Preamplifier Interface, Tag Extension via Preamplifier Interface & And methods using a serial port. These patent applications describe methods and control circuits that may be included within the master / slave serial port control circuitry 112/132 of FIG. 2 to generate a mantissa signal and combine it into a serial port framework as discussed herein have. Generally, U.S. Patent Application No. 13 / 650,474 discloses a method for combining a mantissa signal into a unified high speed serial port. Moreover, U.S. Patent Application No. 13 / 719,615 discloses a method for generating additional mantissa signals in a preamplifier circuit without requiring additional signaling wires. These applications are commonly assigned and are incorporated herein by reference in their entirety.

The bidirectional serial data line 202-1 of the serial port is used by the write channel circuitry 110 and the preamplifier circuitry 130 to perform data access operations on the storage medium 170. In another embodiment of the present invention, Which is implemented using one or more of the signal lines 200-1, 200-2, 200-3, and 200-4. In such an embodiment, the storage device may be configured to master one or more signal lines of the analog bus 200 during a time period during which one or more signal lines of the analog bus 200 are not used to perform data access operations to the storage medium 170 / Slave serial port control circuit 112/132. Exemplary embodiments of the present invention will now be described in more detail with reference to Figures 8 and 9, for example.

8 illustrates a data storage device having control circuitry for supporting serial port communication between a controller and a preamplifier using signal lines of an analog bus to implement bidirectional serial data lines for a serial port, according to an embodiment of the present invention. FIG. In particular, FIG. 8 is a block diagram of an embodiment of the present invention, except that the bidirectional serial data line 202-1 of FIG. 2 is implemented using a read data signal line (e.g., signal line 200-3) , A data storage device 800 similar to the embodiment of FIG. 8, read signal line 200-3 may be read from read circuit 258 (of pre-amplifier circuit 130) (of write channel circuit 110) during a read operation of storage device 800 And serves as a unidirectional line for transferring the read data RD3 to the data circuit 214. [ In addition, the read signal line 200-3 serves as a unidirectional serial data line for transferring a serial bit stream between the master / slave serial port control circuits 112/132, using the protocol described above.

8, the read signal line 200-3 is connected to the read data circuit 214 via the read data circuit 214 and the read circuit 200-3 via the write gate control signal (+ WRITE / -READ) (E.g., CML differential amplifiers) that are controlled (enabled / disabled) to connect or disconnect from the line drivers 258 and 258, respectively. In addition, the write gate control signal (+ WRITE / -READ) is applied to the master / slave serial port control circuit 112/132 so that the line multiplexing circuit 210/212 in the serial port control circuit 112/132 is connected to the master / And controls the slave serial port control circuit 112/132 to connect or disconnect from the read signal line 200-3. In one embodiment, the write gate control signal (+ WRITE / -READ) is used to control the line multiplexing circuit 210/212 by the serial port control circuit 112/132 in accordance with the read or write operation being performed .

Collectively, the line receivers and line drivers 802 and 804 and the line multiplexing circuit 210/212 are connected to the master / slave serial port control circuit 112/132 by a write gate control signal (+ WRITE / -READ) ) From the read signal line 200-3 and to connect the master / slave serial port control circuit 112/132 to the read signal line 200-3 during the write operation . In particular, during a read operation, the line receiver and drivers 802 and 804 are activated in response to a write gate control signal (+ WRITE / -READ) to transfer read data RD3 from the preamplifier circuit 130 to the write channel circuit 110 While the line multiplexing circuitry 210/212 of the master / slave serial port control circuit 112/132 prevents transmission of the serial bit stream through the read signal line 200-3 during the read operation . Also, during a write operation, the line receiver and drivers 802 and 804 are deactivated in response to the write gate control signal (+ WRITE / -READ), while the line multiplexing circuit 210 / 212 are activated to enable serial port communication using the read signal line 200-3 during a write operation, using the serial port control scheme as discussed above.

In the embodiment of FIG. 8, the preamplifier circuit 130 can not be changed during the read operation because the master / slave serial port control circuit 112/132 does not access the read signal line 200-3. Although the embodiment of FIG. 8 illustrates the sharing use of the read signal lines of the analog bus 200 as bidirectional serial data lines of the serial port, in another embodiment, the write signal lines (e.g., Line (signal line 200-4) may be used as the bidirectional serial data line of the serial port by the master / slave serial port control circuit 112/132. In this embodiment, the master / slave serial port control circuit 112/132 will be enabled during the read operation to enable serial port communication using the read signal line 200-3 and will be inactive during the write operation. The amplifier circuit 130 may not change during the write operation.

9 is a block diagram of a data storage device having a control circuit that supports serial port communication between a controller and a preamplifier using a signal line of an analog bus to implement a bidirectional serial data line for a serial port, Fig. In particular, FIG. 9 shows that the bidirectional serial data line 202-1 of FIG. 2 is implemented using the read data signal line 200-3 of the analog bus 200 during a write operation and the read data signal line 200-3 of the analog bus 200 during a read operation. And data storage device 900 that is inferior to the embodiment of FIGS. 2 and 8, except that it is implemented using write data signal line 200-4.

9, the read signal line 200-3 outputs read data RD3 (from the preamplifier circuit 130) from the PLL circuit 238 (during the read operation of the storage device 900) (To the read data circuitry 214 of the memory device 110). Furthermore, the write signal line 200-4 supplies the write data WD from the write data circuit 216 (of the write channel circuit 110) (of the preamplifier circuit 130) ) Writing circuit 260. The write circuit 260 is a non-volatile memory. In addition, the read signal line 200-3 of the analog bus 200 serves as a bidirectional serial data line for transferring a serial bit stream between the master / slave serial port control circuits 112/132 during a write operation, The write signal line 200-4 of the analog bus 200 serves as a bidirectional serial data line for transferring a serial bit stream between the master / slave serial port control circuits 112/132 during a read operation.

In the exemplary embodiment of FIG. 9, similar to the embodiment of FIG. 8, the read signal line 200-3 reads the read signal line 200-3 by the write gate control signal (+ WRITE / -READ) Includes a line receiver 802 and a line driver 804 (e.g., CML differential amplifiers) that are controlled to connect or disconnect from the data circuit 214 and the read circuit 258. Similarly, the write signal line 200-4 is connected or disconnected from the write data circuit 216 and the write circuit 260 by the write gate control signal (+ WRITE / -READ) A line driver 902 and a line driver 904 (e.g., CML differential amplifiers) that are controlled to be controlled.

In addition, the storage device 900 can be connected to the master serial port control circuit 112 by the write gate control signal (+ WRITE / -READ) according to the write or read operation to be performed, And a switching circuit 906 controlled to be connected to any one of the lines 200-4. Similarly, the storage device 900 may control the slave serial port control circuit 132 by the write gate control signal (+ WRITE / -READ) to the read signal line 200-3 or write And a switching circuit 908 controlled to be connected to any one of the signal lines 200-4. In one embodiment, each switching circuit 906 and 908 is implemented using a complementary pair of line drivers / receivers, for example, similar to the line multiplexing circuit 210/212.

Collectively, the line receivers 802, 804, 902 and 904 and the switching circuits 906/908 comprise multiplexing circuits controlled by a write gate control signal (+ WRITE / -READ), during which the multiplexing Circuit 802 / 804/902/904/906/908 disconnects the master / slave serial port control circuit 112/132 from the read signal line 200-3 and the master / slave serial port control circuit 112 / 132) to the recording signal line 200-4. Therefore, during the read operation, the master / slave serial port control circuit 112/132 can use the write signal line 200-4 as the bidirectional serial data line, but the read data RD3 is supplied to the read signal line 200-3 ≪ / RTI > On the other hand, during the write operation, the multiplexing circuit 802/804/902/904/906/908 connects the master / slave serial port control circuit 112/132 to the read signal line 200-3, And to disconnect the serial port control circuit 112/132 from the write signal line 200-4. Therefore, during the write operation, the master / slave serial port control circuit 112/132 can use the read signal line 200-3 as a bidirectional serial data line, but the write data WD is transferred to the write signal line 200-4 ≪ / RTI > The embodiment of Figure 9 utilizes the signal line of the analog bus as a bidirectional serial data line while allowing a serial port transaction to occur both during both read and write operations.

In another embodiment of the present invention, the multiple disk-based storage device 10 (FIG. 1) may be included in a virtual storage system as shown in FIG. In particular, FIG. 10 is a block diagram of a virtual storage system 1000 that includes a plurality of disk-based storage devices of the type shown in FIG. A virtual storage system 1000, also referred to as a storage virtualization system, includes a virtual storage controller 1010, which is illustratively coupled to a RAID system 1020, wherein a RAID is a redundant array of independent disks It says. More specifically, RAID system 1020 includes N individual storage devices labeled 10-1, 10-2, ..., 10-N, one or more of which may be the same as discussed herein It is assumed to comprise an embodiment of the storage device 10 as shown in Fig. 1 with multiplexed communication control circuitry. These and other virtual storage systems, including hard disk drives or other disk-based storage devices of the type described herein, are considered embodiments of the present invention. The host processing device may also be a component of a virtual storage system and may include a virtual storage controller 1010.

Although embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the embodiments of the present invention are not limited to the described embodiments, It should be understood that various changes and modifications may be made therein which result in other embodiments of the invention.

Claims (10)

A method of providing communication between a controller and a preamplifier in a storage device,
Implementing a serial port configured to transmit a digital signal between the controller and the preamplifier via a single bidirectional serial data line;
Controlling the serial port to selectively transmit a digital signal in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller via the bidirectional serial data line, Included
Way.
The method according to claim 1,
Wherein controlling the serial port comprises:
Transmitting a serial bit stream from the controller to the preamplifier via the bidirectional serial data line;
Generating a clock signal using a phase-locked loop circuit in the preamplifier, wherein the clock signal is generated based on a bit rate of the serial bit stream received by the preamplifier, Wow,
Receiving and deserializing the serial bit stream received by the preamplifier using the clock signal;
And transmitting a direction switch control signal via the bidirectional serial data line to the preamplifier,
After the direction switching control signal is detected by the preamplifier,
A control signal for suspending phase and frequency regulation of the phase-locked loop circuit of the preamplifier and for maintaining a static clock signal output from the phase-locked loop of the preamplifier Step,
Assuming control of the bidirectional serial data line by the preamplifier;
Serializing the data using the fixed clock signal and transmitting the data from the preamplifier to the controller via the bidirectional serial data line
Way.
3. The method of claim 2,
Wherein the step of transmitting the directional switching control signal to the preamplifier comprises:
Detecting an asserted flag bit associated with the digital signal transmitted from the controller to the preamplifier;
Generating the direction switching control signal in response to the asserted flag bit and transmitting the direction switching control signal to the preamplifier through the bidirectional serial data line,
Wherein the step of controlling the serial port further comprises transmitting the associated digital signal via the bidirectional serial data line after transmission of the redirection control signal
Way.
3. The method of claim 2,
Wherein the step of controlling the serial port further comprises generating a clock signal in the controller using the phase-locked loop circuit based on a reference signal input to the phase-locked loop circuit in the controller,
Wherein the step of generating the clock signal in the controller comprises:
Using a port bitrate clock signal as the reference signal to generate a clock signal used to encode and serialize a digital signal to be transmitted from the controller to the preamplifier via the bidirectional serial data line,
Generating a clock signal used for deserializing and decoding the serial bit stream transmitted from the preamplifier through the bidirectional serial data line using the serial bit stream transmitted from the preamplifier as the reference signal, Included
Way.
The method according to claim 1,
The bidirectional serial data line is a signal line of an analog bus used for performing a data access operation by the preamplifier and the write channel,
Wherein controlling the serial port comprises:
During a period during which the signal line is not used to perform a data access operation by the preamplifier and the write channel, from a first direction from the controller to the preamplifier or from the preamplifier through the signal line of the analog bus Controlling the serial port to selectively transmit a digital signal in either one of a second direction to the controller,
Controlling the serial port to stop transmitting a digital signal over the signal line of the analog bus for a period while the signal line is being used to perform a data access operation by the preamplifier and the write channel Included
Way.
A controller,
A preamplifier,
A serial port circuit configured to transmit a digital signal through a single bidirectional serial data line between the controller and the preamplifier, the serial port circuit having a first direction from the controller to the preamplifier via the bidirectional serial data line Or to selectively transmit a digital signal in either a second direction from the preamplifier to the controller
Device.
A storage medium,
A read / write head configured to read data from and write data to the storage medium;
A preamplifier configured to process data written to and read from the storage medium;
A controller configured to control the preamplifier;
A serial port circuit configured to transmit a digital signal through a single bidirectional serial data line between the controller and the preamplifier, the serial port circuit having a first direction from the controller to the preamplifier via the bidirectional serial data line Or to selectively transmit a digital signal in either a second direction from the preamplifier to the controller
Storage device.
8. The method of claim 7,
The serial port circuit comprising:
A master serial port control circuit implemented by the controller,
And a slave serial port control circuit implemented by the preamplifier,
Wherein the master serial port control circuit is configured to transmit a serial bit stream to the preamplifier via the bidirectional serial data line,
Wherein the slave serial port control circuit comprises a phase-locked loop circuit configured to generate a clock signal based on a bit rate of the serial bit stream received by the preamplifier,
Wherein the slave serial port control circuit is configured to receive and deserialize the serial bit stream received by the preamplifier using the clock signal,
Wherein the master serial port control circuit is configured to generate a redirection control signal to transfer from the controller to the preamplifier via the bidirectional serial data line,
Wherein the slave serial port control circuit is configured to detect the direction change control signal, and in response to the direction change control signal, the slave serial port control circuit is configured to: (i) detect the slave serial port control circuit (Ii) controlling the bidirectional serial data line; (iii) serializing the data using the fixed clock signal; and (iii) stopping the phase and frequency adjustments and outputting a fixed clock signal from the phase-locked loop circuit of the preamplifier. Directional serial data line from the preamplifier to the controller via the bidirectional serial data line
Storage device.
8. The method of claim 7,
Wherein the bidirectional serial data line is implemented using a signal line of an analog bus and the signal line is used to perform a data access operation on the storage medium by the preamplifier and the write channel circuit, And a multiplexing circuit configured to enable the line to share the signal line by the serial port circuit during a time period when the line is not utilized to perform a data access operation on the storage medium
Storage device.
10. The method of claim 9,
The signal line of the analog bus is a read signal line through which read data is transferred from the preamplifier to the write channel circuit during a read operation,
During a write operation, the multiplexing circuit is configured to connect the serial port circuit to the read signal line,
During the read operation, the multiplexing circuit is configured to disconnect the serial port circuit from the read signal line,
During the read operation, the multiplexing circuit is further configured to connect the serial port control circuit to a write signal line of the analog bus to which write data is transferred from the write channel circuit to the preamplifier during a write operation,
During the write operation, the multiplexing circuit is configured to disconnect the serial port control circuit from the write signal line
Storage device.

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