KR20160004193A - Junction gate field-effect transistor (jfet), semiconductor device and method of manufacturing - Google Patents

Abstract

A junction gate field-effect transistor (JFET) includes: a substrate; a source region formed in the substrate; a drain region formed in the substrate; a channel region formed in the substrate; and at least one gate region formed in the substrate. The channel region connects the source and drain regions. At least one gate region contacts one region of the source and drain regions at an interface, and is isolated from the other area of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one region of the source and drain regions.

Description

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a junction field effect transistor, a semiconductor device,

<Priority claim>

The present application is a continuation-in-part of U.S. Serial No. 13 / 892,960 filed on May 13, 2013, the entirety of which is incorporated herein by reference.

<Background>

Junction gate field effect transistors (JFETs) provide a variety of useful features such as low noise, fast switching speeds, and high power handling capability. These characteristics make JEFT a design consideration in various power applications such as power amplifiers.

In one or more embodiments, which are shown by way of illustration and not limitation in the accompanying drawings, the same reference numerals denote the same elements throughout. The drawings are not to scale unless otherwise disclosed.
1 is a perspective partial cross-sectional view of an n-channel JFET (NJFET) according to some embodiments.
2 is a perspective partial cross-sectional view of a p-channel JFET (PJFET) in accordance with some embodiments.
FIG. 3A is a circuit diagram of a semiconductor device according to some embodiments, and FIG. 3B is a perspective sectional partial view of the semiconductor device.
4 is a top plan view of a JFET according to some embodiments.
5 is a perspective, partial cross-sectional view of a JFET in accordance with some embodiments.
6 is a flow diagram of a method of fabricating an NJFET in accordance with some embodiments.
7A-7D are cross-sectional views of an NJFET at various stages during fabrication according to some embodiments.
8 is a flow diagram of a method of fabricating a PJFET in accordance with some embodiments.
9 is a perspective partial cross-sectional view of an NJFET according to some embodiments.
10 is a perspective, partial cross-sectional view of an NJFET according to some embodiments.
11 is a top plan view of a JFET according to some embodiments.
12 is a perspective partial cross-sectional view of an NJFET according to some embodiments.

The following description provides a number of different embodiments or embodiments for implementing different features of various embodiments. Specific embodiments of components and configurations are described below to simplify the present disclosure. However, the concept of the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, it is apparent that one or more embodiments may be practiced without these specific details. Like reference numerals in the drawings denote like elements.

In some embodiments, the JFET includes source and drain regions, a channel region connecting the source and drain regions, and a gate region. The gate region is configured to develop a depletion region in one of the source and drain regions in response to a voltage applied to the gate region. This is different from the other construction in which the gate region is formed with the depletion region in the channel region. A JFET according to some embodiments is a vertical JFET having a gate region that is at least partially co-elevated with the source and drain regions to reduce the JFET thickness. It is also possible to incorporate the fabrication process of JFETs according to some embodiments into complementary metal-oxide-semiconductor (CMOS) processes for making CMOS circuits, for example on devices such as JFETs or on chips.

1 is a perspective, partial cross-sectional view of an NJFET 100 in accordance with some embodiments. The NJFET 100 includes a substrate 110 and a deep n-well 112, an n-well 114, and a n-well 114 are formed in a substrate 110, And an insulating region (STI) 116 are formed. The NJFET 100 further includes a channel region 120, a drain region 130, a source region 140, and a gate region 150, all of which are formed in the substrate 110. A perspective partial cross-sectional view of FIG. 1 illustrates approximately half of NJFET 100. The other half (not shown) of the NJFET 100 is structurally similar to the half shown in FIG.

The substrate 110 has a thickness direction Z and directions X and Y intersecting with each other and intersecting with the thickness direction Z as well. The substrate 110 includes an elemental semiconductor, a compound semiconductor, an alloy semiconductor, or a combination thereof. Examples of element semiconductors include, but are not limited to, silicon and germanium. Examples of compound semiconductors include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. Examples of alloy semiconductors include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP. In some embodiments, other semiconductor materials including Group III, Group IV, and Group V elements are used. In one or more embodiments, the substrate 110 may comprise a semiconductor on insulator (SOI), a doped epitaxial layer, a graded semiconductor layer, and / or one semiconductor layer (e.g., Si) , &Lt; / RTI &gt; Ge). In some embodiments, the substrate 110 includes a p-type doped substrate labeled P-sub in FIG. Examples of p-type dopants in the p-type doped substrate 110 include, but are not limited to, boron, gallium, and indium. In at least one embodiment, the substrate 110 comprises a p-type doped silicon substrate.

A deep n-well 112 and an n-well 114 are formed in the substrate 110. The deep n-well 112 and n-well 114 are regions where the n-type dopant is lightly doped. Examples of n-type dopants in deep n-well 112 and / or n-well 114 include, but are not limited to phosphorus and arsenic. The n well 114 extends downward from the top surface 118 of the substrate 110 in the thickness direction Z of the substrate 110 and contacts the deep n well 112. The deep n-well 112 and the n-well 114 together form an n-well 100 that isolates the other components of the NJFET 100 from the p-doped substrate 110 and / or from other circuits formed in / Thereby forming a doped structure. The deep n-well 112 causes a current to flow along the channel region 120. In at least one embodiment, the deep n-well 112 and / or n-well 114 are omitted. The isolation region 116 extends downward in the thickness direction Z from the top side 118 of the substrate 110 and around the source region 140 and the gate region 150. Isolation region 116 serves to isolate various regions of NJFET 100 as described herein.

The channel region 120 is an n-channel doped with at least one n-type dopant. The drain region 130 is an n-doped region formed in the upper portion of the n-well 114 adjacent to the upper side 118 of the substrate 110. The source region 140 is also an n doped region formed adjacent to the top side 118 of the substrate 110 and above the channel region 120. The channel region 120 is in contact with the source region 140 and the lower portion of the n-well 114. The channel region 120 electrically connects the drain region 130 and the source region 140.

The gate region 150 is a p-doped gate disposed over the channel region 120. The gate region 150 extends around the source region 140. 1, the gate region 150 includes a first gate region 151 and a second gate region 152 on either side of the source region 140. The first gate region 151 and the second gate region 152 have corresponding interfaces 153 and 154 with the source region 140. The first gate region 151 and the second gate region 152 are isolated from the drain region 130 by an isolation region 116. The drain region 130, the source region 140, and the gate region 150 are at least partially the same height in the thickness direction Z with respect to each other.

The NJFET 100 is typically on a device. During a period when no voltage is applied to the gate region 150, the NJFET 100 is in a fully conductive state in which the channel region 120 electrically connects the drain region 130 and the source region 140 . When the NJFET 100 is conducting, a current flows along the current path 155 as indicated by the arrow in Fig. Specifically, the current flows from the source region 140 downward in the thickness direction Z to the channel region 120, and then flows in the direction of X along the channel region 120 in the direction X intersecting with the thickness direction Z (114) and flows into the drain region (130) upward in the thickness direction (Z). By applying a reverse bias voltage to the gate region 150 the width of the current path 155 and thus the level of the current flowing from the source region 140 to the drain region 130 through the channel region 120 It is possible. In the case of NJFET 100, the reverse bias voltage is a negative voltage. At a sufficiently high reverse bias voltage, the current path 155 is pinched off and the NJFET 100 is switched off.

In particular, during a period when a reverse bias voltage is applied to the gate region 150, the depletion region is built into the source region 140 to reduce the width of the current path 155 or even pinch off the current path. For example, upon application of a reverse bias voltage, depletion regions 157 and 158 are formed in the source region 140 over the channel region 120. The depletion regions 157 and 158 extend from the corresponding interface of the first and second gate regions 151 and 152 with the source region 140 in a direction X intersecting the thickness direction Z of the substrate 110 And extend toward each other. Depletion regions 157 and 158 reduce the width of current path 155 and limit the level of current passing through NJFET 100. As the level of the reverse bias voltage rises, the depletion regions 157 and 158 further extend toward each other, further reducing the width of the current path 155. At a sufficient level of reverse bias voltage, i.e., a pinch-off voltage, the current path 155 is pinned off and the NJFET 100 is switched off.

In the NJFET 100, a depletion region is formed in the source region 140 above the channel region 120. This is different from other structures in which the depletion region is formed in the channel region. In another configuration, to form a depletion region in the channel region, the bottom gate includes a bottom gate below the channel region, and the depletion region is formed and extended in the thickness direction of the substrate. A lower gate is included below the channel region to increase the thickness of the device. On the other hand, since the lower gate is not included in the JFET according to some embodiments, the device thickness is reduced.

One or more electrical characteristics of the NJFET 100 can be obtained by varying the length LS of the source region 140, i.e., the length between the first gate region 151 and the second gate region 152, . For example, the longer the length LS, the higher the pinch-off voltage will be. By changing or controlling the length LS, the pinch-off voltage will also be varied or controlled accordingly. A change in length LS or control (also referred to herein as "scalability") in direction X, according to some embodiments, may be achieved by varying the channel depth of the channel region in the thickness direction, It is easier than configuration. As a result, it is possible in some embodiments to design and fabricate JFETs that have reliable electrical characteristics and / or are not unacceptably high or low pinch-off voltage concerns.

It is also possible to integrate a JFET according to some embodiments with a CMOS process, as described herein. By integrating JFET fabrication within a CMOS process, JFETs can provide a low-cost solution to the power application modules used. An example of such a power application module is a power amplifier, in particular a radio frequency (RF) power amplifier for, for example, a cell phone or similar wireless device. In some embodiments, the RF performance of the RF power amplifier is enhanced as a substrate 110 using a bulk or high resistance substrate, such as an 8-12 ohmic Si substrate.

2 is a perspective, partial cross-sectional view of a PJFET 200 according to some embodiments. The PJFET 200 includes a substrate 210 and a p-bottom 211, an n-well 213, a p-well PW 214, a deep n- A well (DNW) 215, and an isolation region (STI) A section 217 of the substrate 210 is located between the n-well 213 and the p-well 214. In some embodiments, compartment 217 is another isolation region. The n-well 213, the p-well 214, the isolation region 216 and the substrate compartment (or isolation region) 217 extend downward from the top side 218 of the substrate 210 in the thickness direction Z . The PJFET 200 further includes a channel region 220, a source region 230, a drain region 240 and a gate region 250 which are formed within the substrate 110. A perspective partial cross-sectional view of FIG. 2 shows approximately half of the PJFET 200. The other half (not shown) of the PJFET 200 is structurally similar to the half shown in FIG.

In some embodiments, the substrate 210 is similar to the substrate 110 of the NJFET 100. For example, the substrate 210 is a p-doped substrate. The p-doped bottom region 212 and the p-well 214 correspond to the deep n-well 112 and n-well 114 of the NJFET 100. The p-doped bottom region 212 and the p-well 214 are regions where the p-type dopant is lightly doped. The p-well 214 extends downward in the thickness direction Z from the top surface 218 of the substrate 210 and contacts the p-doped bottom region 212. The p-doped bottom region 212 allows current to flow along the channel region 220. In at least one embodiment, the p-doped bottom region 212 and / or the p-well 214 are omitted. Isolation regions 116 and 117 serve to isolate the various regions of PJFET 200 as described herein.

The n-well 213 and the deep n-well 215 are regions where the n-type dopant is lightly doped. The n-well 213 extends downward in the thickness direction Z from the upper side 218 of the substrate 210 and contacts the deep n-well 215. An n-well 213 extends around the p-well 214 and is isolated from the p-well 214 by a substrate compartment (or isolation region) A deep n-well 215 is formed below the p-doped bottom region 212. In one or more embodiments, the deep n-well 215 is in contact with the p-doped bottom region 212. In at least one embodiment, the deep n-well 215 is spaced from the p-doped bottom region 212. The deep n-well 215 and the n-well 213 together form an n-doped (n-type) doping layer that isolates the other components of the PJFET 200 from the p-doped substrate 210 and / Structure.

The channel region 220, the source region 230, the drain region 240 and the gate region 250 are formed in the channel region 120, the drain region 130, the source region 140, and the gate region (not shown) of the NJFET 100 150). The channel region 220 is a p-channel doped with at least one p-type dopant. The source region 230 is a p-doped region formed in the upper portion of the p-well 214 adjacent to the upper side 218 of the substrate 210. The drain region 240 is also a p-doped region formed adjacent to the top surface 218 of the substrate 210 and above the channel region 220. The channel region 220 contacts the drain region 240 and the lower portion of the p-well 214. The channel region 220 electrically connects the source region 230 and the drain region 240.

Gate region 250 is an n-doped gate disposed over channel region 220. The gate region 250 extends around the drain region 240. 2, the gate region 250 includes a first gate region 251 and a second gate region 252 on either side of the drain region 240. In FIG. The first gate region 251 and the second gate region 152 have corresponding interfaces 253 and 254 with the drain region 240. The first gate region 251 and the second gate region 252 are isolated from the source region 230 by the isolation region 216. The source region 230, the drain region 240, and the gate region 250 are at least partially the same height in the thickness direction Z with respect to each other.

The PJFET 200 operates in the same manner as the NJFET 100. Specifically, during a period when no voltage is applied to the gate region 250, the PJFET 200 is in a fully conductive state in which the channel region 220 electrically connects the source region 230 and the drain region 240. When the PJFET 200 is conducting, a current flows along the current path 255 as indicated by the arrow in Fig. Specifically, the current flows from the source region 230 downward in the thickness direction Z to the channel region 220 and then flows in the direction X intersecting the thickness direction Z along the channel region 220, And flows in the drain region 240 in the upward direction (Z). Depletion regions 257 and 258 are formed in the drain region 240 over the channel region 220 during a period when a reverse bias voltage, i.e., a positive voltage, is applied to the gate region 250. [ The depletion regions 257 and 258 extend toward each other in the direction X from the corresponding interfaces 253 and 254 to reduce the width of the current path 255 and limit the level of current passing through the PJFET 200 . As the level of the reverse bias voltage rises, the depletion regions 257 and 258 further extend toward each other, further reducing the width of the current path 255. At a sufficient level of reverse bias voltage, i. E. Pinch-off voltage, the current path 255 is pinned off and the PJFET 200 is switched off. One or more effects described for NJFET 100 may also be achieved in PJFET 200 according to some embodiments.

FIG. 3A is a circuit diagram of the semiconductor device 300. FIG. The semiconductor device 300 includes an NJFET 301 and a PJFET 302. The gate regions of the NJFET 301 and the PJFET 302 are connected to each other and connected to the input node IN to receive the input signal at the input node IN. The drain region of the NJFET 301 and the source region of the PJFET 302 are connected to each other and connected to the output node OUT to output an output signal to the output node OUT. The source region of the NJFET 301 is connected to the first voltage terminal VSS to receive a first power supply voltage, e.g., a ground voltage. The drain region of the PJFET 302 is connected to the second voltage terminal VDD to receive a second power supply voltage, e.g., a positive power supply voltage.

3B is a perspective, partial cross-sectional view of a semiconductor device 300 according to some embodiments. The NJFET 301 and the PJFET 302 of the semiconductor device 300 are formed in the substrate 310 such as the substrate 110 or the substrate 210. [ The NJFET 301 is configured similarly to the NJFET 100, and the PJFET 302 is configured similarly to the PJFET 200. The gate regions 150 and 250 of the NJFET 301 and the PJFET 302 are connected to corresponding vias 371 and 372 embedded in one or more dielectric layers (not shown) formed on the substrate 310. The vias 371 and 372 are connected to each other and are connected to the input node IN by the conductive layer 373. [ The drain region 130 of the NJFET 301 and the source region 230 of the PJFET 302 are connected to corresponding vias 381 and 382 embedded in one or more dielectric layers formed on the substrate 310. The vias 381 and 382 are connected to each other and are connected to the output node OUT by the conductive layer 383. The source region 140 of the NJFET 301 is connected to a corresponding via 391 buried in one or more dielectric layers formed on the substrate 310. [ The via 391 is connected to the ground voltage terminal VSS by the conductive layer 392. The drain region 240 of the PJFET 302 is connected to the corresponding via 393. The via 393 is connected to the positive voltage terminal VDD by the conductive layer 394.

The semiconductor device 300 operates as an inverter that inverts the input signal received at the input node IN and outputs the inverted signal to the output node OUT as an output signal. Semiconductor device 300 also functions as a power amplifier that amplifies the amplitude of the input signal from terminal VDD to a higher level positive supply voltage. According to some embodiments, the NJFET 100 and / or the PJFET 200 may be fabricated herein by configuring the PJFET 302, such as the NJFET 301 and / or the PJFET 200, One or more effects can be achieved in the semiconductor device 300 as described. One or more additional effects, such as low noise, high breakdown voltage, high switching speed, etc., may also be achieved in semiconductor device 300 in accordance with some embodiments.

4 is a top plan view of the NJFET 400 according to some embodiments. The NJFET 400 is formed in the substrate 410 having the isolation region 416. The NJFET 400 includes a drain region 430, a source region 440, and a gate region 450. In some embodiments, the substrate 410, the isolation region 416, the drain region 430, the source region 440 and the gate region 450 are formed on the substrate 110 of the NJFET 100, the isolation region 116, The drain region 130, the source region 140, and the gate region 150, respectively. The gate region 450 has first and second gate regions 451 and 452 corresponding to the first and second gate regions 151 and 152 of the gate region 150. However, unlike the first gate region 151 and the second gate region 152, which are best seen in FIG. 1, the first gate region 451 and the second gate region 452, Are not connected to each other as best shown in Fig. In some embodiments, the same gate voltage, e.g., reverse bias voltage, is applied in both the first gate region 451 and the second gate region 452 during operation. In at least one embodiment, a different gate voltage is applied to the first gate region 451 and the second gate region 452 in operation to change the electrical characteristics of the NJFET 400. [ In at least one embodiment, either the first gate region 451 or the second gate region 452 is etched.

Each of the first gate region 451 and the second gate region 452 has a gate length LG. In at least one embodiment, the gate length of the first gate region 451 is different from the gate length of the second gate region 452. The drain region 430 has a drain length LD and the source region 440 has a source length LS. At least one of the gate length LG, the drain length LD and the source length LS can be varied or extended to achieve the target electrical characteristic of the NJFET 400, while the remainder ensures that the NJFET 400 is fabricated To meet a plurality of design rules. The description and effects of the NJFET 400 are applicable to the PJFET according to some embodiments.

5 is a perspective partial cross-sectional view of an NJFET 500 in accordance with some embodiments. NJFET 500 is formed in substrate 510 having isolation region 516 and n-well 514. The NJFET 500 includes a drain region 530, a source region 540, and a gate region 550. In some embodiments, the substrate 510, the n-well 514, the isolation region 516, the drain region 530, the source region 540 and the gate region 550 are formed on the substrate 110 of the NJFET 100, the n-well 114, the isolation region 116, the drain region 130, the source region 140, and the gate region 150, respectively. The gate region 550 has first and second gate regions 551 and 552 corresponding to the first and second gate regions 151 and 152 of the gate region 150.

At least one of the drain region 530 and the source region 540 has a corresponding drain or source enhancement layer. The enhancement layer has the same type of dopant as the channel region 520 but has a higher doping concentration of the dopant than in the channel region 520. For example, the drain region 530 has an n-type dopant, that is, a drain enhancement layer 531 having the same dopant type as the channel region 520. The doping concentration of the n type dopant in the drain enhancement layer 531 is higher than that of the channel region 520. For example, in at least one embodiment, the n-type dopant in the drain enhancement layer 531 has a doping concentration of about 100 x 10 ¹⁴ atoms / cm ³ and the n-type dopant in the channel region 520 has a doping concentration of about 450 x 10 to ¹² has a doping concentration of the atoms / cm ^3. The drain enhancement layer 531 is formed at least partially at the same height as the first and second gate regions 551 and 552 in the upper portion of the n-well 514. In at least one embodiment, the drain enhancement layer 531 contacts the channel region 520. Drain region 530 further includes a drain contact layer 532 that forms an ohmic or Schottky contact 534 with the drain enhancement layer 531. [

Source region 540 includes source enhancement layer 541 and source contact layer 542 that forms an ohmic or Schottky contact 544 with source enhancement layer 541 do. The source enhancement layer 541 has the same dopant type as the channel region 520, i. E., N type, but the doping concentration is higher. In at least one embodiment, the doping concentration of the n-type dopant in the source enhancement layer 541 is higher than in the drain enhancement layer 531. [ In at least one embodiment, the doping concentrations of the n type dopants in the source enhancement layer 541 and the drain enhancement layer 531 are different. The source enhancement layer 541 is at least partially at the same height as the first and second gate regions 551 and 552 and contacts the channel region 520. In at least one embodiment, the drain enhancement layer 531 or source enhancement layer 541 is omitted. Gate region 550 also includes a gate contact layer 553 that forms an ohmic or Schottky contact 554 with the first and second gate regions 551 and 552.

Since the enhancement layers 531 and 541 have a higher doping concentration than the channel region 520, the enhancement layers 531 and 541 have lower resistance than the channel region 520. When the resistance of the enhancement layers 531 and 542 is low, the ON resistance of the NJFET 500 decreases. The ohmic or Schottky contacts 534, 544, 554 further enhance the electrical performance of the gate region 550. The description and effects of the NJFET 500 are applicable to the PJFET according to some embodiments.

FIG. 6 is a flow diagram of a method 600 of manufacturing an NJFET, and FIGS. 7A-7D are cross-sectional views of an NJFET at various stages in manufacturing method 600, in accordance with some embodiments.

In step 605 of Fig. 6, a deep n-well and at least one isolation region are formed in the substrate. For example, deep n-well 712 and isolation regions 716 and 719 are formed in substrate 710, as shown in Fig. 7A. In at least one embodiment, substrate 710, isolation region 716, and deep n-well 712 are formed in substrate 510, isolation region 516, and deep n-well 512 of NJFET 500 Respectively. An isolation region 716 extends around the portion 713 of the substrate 710 where the source and gate regions of the NJFET are formed. Isolation region 719 extends around portion 715, portion 713, and isolation region 716 of substrate 710 where the drain region of the NJFET is formed. In this embodiment, the isolation region 719 is the same as the substrate section (or isolation region) 217 described with reference to FIG.

In some embodiments, a photoresist (not shown) is laminated on a substrate 710, and a mask (not shown) having a pattern of deep n-wells 712 is formed by patterning the laminated photoresist to form a substrate 710 A deep n-well 712 is formed. The mask is used in ion implantation to implant an n-type dopant into the substrate 710 to form a deep n-well 712. In at least one embodiment, the ion implantation is controlled by at least one of energy, dose, and implant angle for implanting the n-type dopant deep enough into the substrate 710. The mask is then removed.

In some embodiments, isolation regions 716 and 719 are formed in the substrate 710 by forming a trench (not shown) in the substrate 710 and then filling the trench with an insulating material such as silicon oxide. In at least one embodiment, a trench is formed by a lithographic and / or etching process. The depth and / or width of isolation regions 716 and 719 are selected according to the design and / or target electrical properties of the NJFET to be fabricated.

In step 615 of Fig. 6, an n-channel region is formed in the substrate. For example, as shown in Fig. 7B, a channel region (NJI) 720 is formed in the partition 713 of the substrate 710. [ In at least one embodiment, the channel region 720 corresponds to the channel region 520 of the NJFET 500. In some embodiments, a channel region 720 is formed by using this mask in ion implantation, which is done to create a mask and then implant an n-type dopant into the substrate 710. The mask for forming the channel region 720 is created in a manner as described for step 605. [ The ion implantation for forming the channel region 720 is controlled by at least one of energy, dose and implant angle. In at least one embodiment, the doping concentration or doping dose for forming the channel region 720 is higher than for forming the deep n-well 712.

In step 625 of Fig. 6, an n-well is formed in the substrate. For example, as shown in FIG. 7B, an n-well 714 is formed in the partition 715 of the substrate 710. In at least one embodiment, n-well 714 corresponds to n-well 514 of NJFET 500. The n-well 714 has an upper portion of the same height as the adjacent isolation regions 716, 719 and lies between them. The n-well 714 also has a lower portion that is lower than the isolation regions 716, 719. The lower portion of n-well 714 is in contact with deep n-well 712 and channel region 720. The lower portion of the n-well 714 extends laterally to partially locate under one or both of the isolation regions 716, 719. In some embodiments, the n-well 714 is formed in the manner described above for the channel region 720, but the mask used is different.

In step 635 of FIG. 6, a source and / or drain enhancement layer is formed in the substrate. For example, as shown in Fig. 7C, drain and source enhancement layers (NJDS) 731 and 741 are formed at positions corresponding to the drain region and the source region of the NJFET to be manufactured. In at least one embodiment, the drain and source enhancement layers 731 and 741 correspond to the drain and source enhancement layers 531 and 541 of the NJFET 500. A drain enhancement layer 731 is formed on the upper side of the n-well 714 and between the adjacent isolation regions 716, 719. The drain enhancement layer 731 extends further under the isolation regions 716 and 719 and has a portion located under one or both of the isolation regions 716 and 719. [ In at least one embodiment, the drain enhancement layer 731 is in contact with the channel region 720. A source enhancement layer 741 is formed in the central portion of the compartment 713 and contacts the channel region 720. In some embodiments, enhancement layers 731 and 741 are formed in the manner described above for channel region 720, but the masks used are different and the dopant concentration is higher.

In step 645 of Fig. 6, a gate region is formed in the substrate. For example, as shown in FIG. 7D, first and second gate regions 751 and 752 are formed as a p-doped region in the substrate 710. In at least one embodiment, the first and second gate regions 751 and 752 correspond to the first and second gate regions 551 and 552 of the NJFET 500. Each of the first and second gate regions 751 and 752 is in contact with the isolation region 716 and the source enhancement layer 741. In some embodiments, the first and second gate regions 751 and 752 are formed in the manner described above for the channel region 720, but the masks used are different and the dopant is p-type.

In step 655 of FIG. 6, a dielectric layer, such as a resist protective oxide (RPO) layer, is formed over the junction area between the source and gate regions. 7D, the RPO layers 761 and 762 are formed between the first gate region 751 and the source enhancement layer 741 and between the second gate region 752 and the source enhancement layer 741, Are formed on the corresponding junction regions. The RPO layers 761 and 762 serve to prevent subsequently formed contact layers from contacting each other. In at least one embodiment, the RPO layer is formed by depositing a dielectric material such as silicon oxide and / or silicon nitride over the substrate 710 and etching away the dielectric material outside the junction region.

At step 665 of FIG. 6, at least one of the drain, source, and gate contact layers is formed over the corresponding drain, source, and gate regions. For example, as shown in FIG. 7D, the drain contact layer 732, the source contact layer 742, and the gate contact layer 753 correspond to the corresponding drain enhancement layer 731, source enhancement layer 741, and Is formed over the first and second gate regions 751, 752. The drain contact layer 732, the source contact layer 742 and the gate contact layer 753 are formed in the drain contact layer 532 of the NJFET 500, the source contact layer 542, (553). In some embodiments, the drain, source, and gate contact layers 732, 742, and 753 are silicide layers that are in ohmic (or schottky) contact with the corresponding drain, source, and gate regions of the lower portion. In at least one embodiment, a metal such as Ti, Co, Ni is deposited on a previously formed structure on a substrate 710, the substrate 710 having the structure is annealed, , Reacting with silicon in the source and gate regions, and then removing the unreacted metal, the silicide layer is formed. The source contact layer 742 and the gate contact layer 753 are separated from each other by the RPO layers 761 and 762. Thus, an NJFET is obtained.

Additional processing is subsequently performed in some embodiments to connect the NJFET to other circuits. For example, one or more dielectric layers (not shown) may be stacked on a substrate 710 over which an NJFET is formed, and one or more dielectric layers (not shown) may be deposited in electrical contact with corresponding gate, drain, and source contact layers 753,732, Contact vias 771, 781, and 791 are formed. In at least one embodiment, the contact vias 771, 781, and 791 correspond to the vias 371, 381, and 391 described for the semiconductor device 300.

The steps of the method 600 for fabricating a JFET according to some embodiments are possible to integrate into a CMOS process for fabricating CMOS circuits on the same substrate (e.g., on the same wafer). Two additional masks and associated ion implantation are added to form the channel region and the source and / or drain enhancement layer. Thus, it is possible to fabricate a JFET according to some embodiments by a CMOS process without substantial changes to the CMOS process, so that a low cost product (e.g., a power amplifier) having one or more of the advantages of the JFET described herein can be obtained have.

8 is a flow diagram of a method 800 of fabricating a PJFET in accordance with some embodiments.

At step 805, a deep n-well and at least one isolation region are formed in the substrate, e.g., as described for step 605. [

In step 815, a p-bottom region and a p-channel are formed in the substrate. For example, a p-bottom region 212 and a p-channel 220 are formed in the substrate 210 as described for the PJFET 200. The p-bottom region and the p-channel are formed by using the mask in the ion implantation performed to implant the p-type dopant into the substrate after forming the mask in the manner as described for the step 615 except for the dopant type. In at least one embodiment, the p-bottom region and the p-channel are formed using the same mask. In at least one embodiment, the p-type dopant concentration or dose in the p-bottom region is lower than that of the p-channel.

In step 825, an n-well and a p-well are formed in the substrate. For example, an n-well 213 and a p-well 214 are formed in the substrate 210 as described for the PJFET 200. In at least one embodiment, the formation of the n-well is the same as step 625. The formation of the p-well is the same as the formation of the n-well, except that a different mask and p-type dopant are used.

In step 835, a source and / or drain enhancement layer is formed in the substrate. In addition to the use of a p-type dopant, for example, a source and / or drain enhancement layer similar to the source and / or drain enhancement layers 741 and 731 described for step 635, .

In step 845, a gate region is formed in the substrate. A gate region similar to the first and second gate regions 751 and 752 described for step 645 is formed using the same masking and ion implantation process, in addition to the use of, for example, n-type dopants.

In step 855, a dielectric layer, such as an RPO layer, is formed over the junction region between the drain and gate regions, e.g., as described for step 855. [

At step 865, at least one of the drain, source, and gate contact layers is formed over the corresponding drain, source, and gate regions, e.g., as described for step 865.

The effect of the method 600 is also applicable to the method 800 according to some embodiments.

While the above methods include exemplary steps, these steps need not necessarily be performed in the order they are presented. Steps may be added, substituted, reordered, and / or eliminated in accordance with the spirit and scope of the embodiments of the present disclosure. Embodiments incorporating different features and / or different embodiments within the scope of this disclosure will be apparent to those skilled in the art after review of this disclosure.

9 is a perspective partial cross-sectional view of an NJFET 900 in accordance with some embodiments. Like FIG. 1, a perspective partial cross-sectional view of FIG. 9 illustrates approximately half of NJFET 900. The other half (not shown) of the NJFET 900 is structurally similar to the half shown in FIG. 1, NJFET 900 is formed in substrate 910 and has a dielectric layer 960 that covers the interface of gate region 150 with source region 140. In this embodiment,

In some embodiments, the substrate 910 comprises an SOI substrate. In at least one embodiment, the substrate 910 comprises 5000 to 10000 ohmic Si substrates, i.e. the Si substrate has a resistance in the range of 5000 to 10000 ohm.cm.

In some embodiments, dielectric layer 960 includes an RPO material as described for the RPO layer in Figure 7D. The dielectric layer 960 covers the interface between the gate region 150 and the source region 140 and the gate region 150 and other portions of the source region 140 for electrical contact between the NJFET 900 and other circuitry Exposed. In at least one embodiment, the dielectric layer 960 completely covers the interface between the gate region 150 and the source region 140 from above. 9, in a top view of substrate 910, drain region 130 extends around gate region 150, gate region 150 extends around dielectric layer 960, (960) extends around the source region (140).

The operation of the NJFET 900 is the same as that of the NJFET 100 described with reference to FIG. For example, when a reverse bias voltage is applied to the gate region 150, the depletion regions 157 and 158 extend from the interfaces 153 and 154 into the source region 140.

In some embodiments, the same as the PJFET 200 described with respect to FIG. 2, but the same as the dielectric layer 960 formed in a substrate such as the substrate 910 and covering the interface between the gate region 250 and the drain region 240 A PJFET (not shown) having a dielectric layer is provided. The operation of the PJFET 900 is the same as that of the PJFET 200 described with reference to FIG.

In some embodiments, by providing a dielectric layer, such as dielectric layer 960, over the interface between the gate region of the JFET and the corresponding source or drain region, the breakdown voltage of the JFET rises. This effect is particularly useful in one or more embodiments where the substrate of the JFET is a high resistance substrate such as an SOI substrate. Specifically, as the leakage current increases, the turn-on of the parasitic bipolar junction transistor (BJT) in the JFET is likely to be induced early, so that a burnout structure may occur between the gate contacts and the electrical contacts on the top of the corresponding source or drain region There is a possibility. By forming a dielectric layer 960 between the electrical contacts on the top portion of the gate region 150 and the source region 140, for example, by forming a dielectric layer between the electrical contacts on the top of the gate region and the corresponding source or drain region, The leakage current decreases and the voltage at which the BJT is turned on rises, which means that the JFET has an increased breakdown voltage.

In some embodiments, the width of the dielectric layer is a factor that affects how the breakdown voltage of the JFET rises. In at least one embodiment, the thickness of the dielectric layer is in the range of 0.5 to 5 占 퐉 (microns). In some circumstances, dielectric layers having a width less than 0.5 占 퐉 are insufficient to reduce the leakage current and / or raise the breakdown voltage. In some situations, dielectric layers larger than 5 占 퐉 in width do not necessarily result in additional breakdown voltage rise, and such large dielectric layers may also consume too much material and / or may have an electrical contact on the gate region and / There is a possibility that an insufficient area is left. The sizes and materials of the dielectric layers described are exemplary. Other configurations are within the scope of various embodiments.

10 is a perspective, partial cross-sectional view of an NJFET 1000 in accordance with some embodiments. Like FIG. 1, a perspective partial cross-sectional view of FIG. 10 illustrates approximately half of NJFET 1000. The other half (not shown) of the NJFET 1000 is structurally similar to the half shown in FIG. Compared to the NJFET 900 described for FIG. 9, the NJFET 1000 has an isolation region 1016 below the dielectric layer 960.

An isolation region 1016 is disposed between the gate region 150 and the source region 140. More specifically, the isolation region 1016 is disposed between the gate region 150 and the upper portions of the source region 140, while at the interfaces 1053 and 1054 corresponding to the interfaces 153 and 154, The gate region 150 and the lower portions of the source region 140 are brought into contact with each other. 10, a drain region 130 extends around the gate region 150 and a gate region 150 extends around the dielectric layer 960 and the isolation region 1016. In a plan view of the substrate 910 in the exemplary configuration shown in Figure 10, And the dielectric layer 960 and the isolation region 1016 extend around the source region 140. 10, the dielectric layer 960 is narrower than the isolation region 1016, and a portion of the isolation region 1016 is exposed from below the dielectric layer 960. In the exemplary configuration shown in FIG. Other width relationships between dielectric layer 960 and isolation region 1016 are also within the scope of various embodiments. In at least one embodiment, the material and / or manufacturing process of isolation region 1016 is the same as that of isolation region 116 described with respect to FIG. The configuration of the described isolation region 1016 is an example. Other configurations are within the scope of various embodiments.

The operation of the NJFET 1000 is the same as the operation of the NJFET 100 described with reference to FIG. For example, when a reverse bias voltage is applied to the gate region 150, the depletion regions 1057 and 1058 corresponding to the depletion regions 157 and 158 described with respect to FIG. 1, but less than the depletion regions 1057 and 1058, The source region 140 is formed.

In some embodiments, a PJFET (not shown) is provided, which is the same as the PJFET described with reference to FIGS. 2 and 9, but with an isolation region such as isolation region 1016 formed therein. The operation of such a PJFET is the same as the operation of the PJFET 200 described with reference to FIG.

In some embodiments, the isolation region, such as isolation region 1016, between the gate region and the corresponding source or drain region reduces the strong electric field present at the higher operating voltage, The depletion region becomes smaller as compared with the structure, and the breakdown voltage of the JFET increases. In at least one embodiment, an isolation region, such as isolation region 1016, is formed within one or more of the JFET structures described with respect to FIGS. 1-8, and one or more of the effects described herein for the isolation region 1016 Can also be achieved.

11 is a top plan view of JFET 1100 in accordance with some embodiments. 4, NJFET 1100 is formed in substrate 1110 and includes dielectric layer 1160 and isolation region 1116 underneath dielectric layer 1160. In this embodiment, In some embodiments, substrate 1110, dielectric layer 1160 and isolation region 1116 correspond to substrate 910, dielectric layer 960, and isolation region 1016 described with respect to FIG. The isolation region 1116 has portions 1117 and 1118 disposed between the source region 140 and the corresponding first and second gate regions 151 and 152. An isolation region 1116 extends around the source region 140 and also around the first and second gate regions 151 and 152. One or more of the effects described with respect to the corresponding JFETs 400, 900, 1000 of FIGS. 4, 9, and 10 may also be achieved in a JFET 1100 in accordance with some embodiments.

12 is a perspective, partial cross-sectional view of an NJFET 1200 in accordance with some embodiments. 7D, NJFET 1200 is formed in substrate 1210 and includes at least one dielectric layer 1261, 1262 and at least one isolation region 1261, 1262 below the corresponding dielectric layer 1261, (1296, 1297). In some embodiments, the substrate 1210, the at least one dielectric layer 1261, 1262, and the at least one isolation region 1296, 1297 may be formed over the substrate 910, the dielectric layer 960, 1016).

In at least one embodiment, the NJFET 1200 is fabricated with a process as described with respect to Figures 6, 7A-7D, with the following differences. Specifically, at least one isolation region 1296, 1297 is additionally formed in the portion 713 (FIG. 7A) where the source region and the gate region of the NJFET 1200 are formed. In at least one embodiment, at least one isolation region 1296, 1297 is formed with isolation regions 716, 719, in the same process, and / or with the same material and / or the same depth. Other configurations are within the scope of various embodiments. In one or more steps, a source enhancement layer 741 is formed in a central portion that is surrounded by at least one isolation region 1296, 1297. In at least one embodiment, the first and second gate regions 751, 752 are formed around at least one isolation region 1296, 1297 (as described for FIG. 10) or at least one isolation region 1296 , 1297 (as described with reference to Fig. 11). In at least one step, at least one dielectric layer 1261, 1262 is formed over the corresponding at least one isolation region 1296, 1297 to electrically isolate the source and gate contact layers 742, 743 from one another.

Some embodiments provide a PJFET fabrication process as described for FIG. 8, but have at least one of the differences described for the fabrication process of the NJFET 1200.

In some embodiments, by providing a dielectric layer, such as an RPO layer, over the interface between the gate region and the source / drain region and / or by providing an isolation region between the gate region and the upper portions of the source / drain regions, Or a breakdown voltage rise occurs. In one or more embodiments, one or more of these configurations and / or effects is useful in a semiconductor device formed in a high-resistance substrate, such as an SOI substrate.

According to some embodiments, a JFET includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. At least one gate region contacts one region of the source and drain regions at the interface, and at least one gate region is isolated from the other region of the source and drain regions. A dielectric layer covers the interface while exposing portions of the one and the other of the source and drain regions.

In some embodiments, the semiconductor device comprises a substrate and at least one transistor formed in the substrate. The at least one transistor includes source and drain regions formed in the substrate, first and second gate regions formed in the substrate, and a channel region formed in the substrate. The first and second gate regions are at least partially at the same height as the source and drain regions. One of the source and drain regions is disposed between the first and second gate regions. The channel region connects the source and drain regions. The isolation region is disposed between (i) the upper portion of the first and second gate regions and (ii) the upper portion of one of the source and drain regions.

 In some embodiments, in the method of fabricating a transistor, an isolation region, a channel region, and source and drain regions are formed in the substrate. In a top view of the substrate, one of the source and drain regions is surrounded by the other of the source and drain regions. A gate region is formed in the substrate. The isolation region is disposed between the first gate region and one of the source and drain regions. A dielectric layer is formed over the gate region and an isolation region disposed between one region of the source and drain regions. A contact layer is formed over the corresponding gate, source and drain regions. The dielectric layer isolates the contact layer over the gate region from the contact layer over one of the source and drain regions.

One of ordinary skill in the art will readily understand that one or more of the disclosed embodiments accomplish one or more of the foregoing advantages. Having read the foregoing specification, it will be apparent to those skilled in the art that various changes, alternatives, and various other embodiments, which are broadly described herein, may be practiced. It is therefore intended that the protection afforded there be limited only by the terms of the appended claims and their equivalents.

Claims (10)

For a junction gate field-effect transistor (JFET)
A substrate;
A source region formed in the substrate,
A drain region formed in the substrate,
A channel region formed in the substrate and connecting the source region and the drain region,
At least one gate region formed in the substrate, the at least one gate region contacting at an interface with one of the source and drain regions and being isolated from the other of the source and drain regions,
A dielectric layer covering the interface while exposing portions of the one region and the gate region of the source and drain regions,
/ RTI &gt; 2. The device of claim 1 wherein the at least one gate region is configured to extend a depletion region from the interface to the one of the source and drain regions in response to a reverse bias voltage applied to the at least one gate region. Lt; / RTI &gt; The JFET of claim 1, wherein the substrate comprises an SOI (semiconductor on insulator) substrate. The JFET of claim 1, wherein in a top view of the substrate, the dielectric layer extends around the one of the source and drain regions. The JFET of claim 1, wherein in a top view of the substrate, the gate region extends around the one of the dielectric layer and the source and drain regions. The method according to claim 1,
Wherein the at least one gate region comprises a first gate region and a second gate region,
Wherein the one of the source and drain regions and the dielectric layer are sandwiched between the first and second gate regions. The method according to claim 1,
Further comprising contact layers over exposed portions of the one of the source and drain regions and the gate region,
Wherein the dielectric layer is disposed between the contact layers and is at least partially co-elevated with the contact layers. The method according to claim 1,
Further comprising an isolation region below said dielectric layer, said isolation region being disposed between said gate region and said one of said source and drain regions. A semiconductor device comprising:
A substrate;
At least one transistor formed in the substrate,
Source and drain regions formed in the substrate;
Wherein the first and second gate regions are at least partially at the same height as the source and drain regions, and wherein one of the source and drain regions is formed in the first and second gate regions, The first and second gate regions being disposed between the second gate regions,
The at least one transistor being formed in the substrate and including a channel region connecting the source and drain regions;
(i) upper portions of the first and second gate regions and (ii) an isolation region between the upper portion of the one of the source and drain regions
&Lt; / RTI &gt; A method of fabricating a transistor in a substrate,
Forming an isolation region in the substrate;
Forming a channel region in the substrate;
Forming source and drain regions in the substrate, wherein in a top view of the substrate, one of the source and drain regions is surrounded by another of the source and drain regions; Forming step,
Forming a gate region in the substrate, wherein the isolation region is disposed between the gate region and the one of the source and drain regions;
Forming a dielectric layer on the gate region and the isolation region disposed between the one of the source and drain regions;
Forming contact layers over the corresponding gate, source and drain regions
Lt; / RTI &gt;
Wherein the dielectric layer isolates the contact layer over the gate region from the contact layer over the one of the source and drain regions.

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