KR20160003101A - 타일-기반 렌더러들에 대한 쿼리 프로세싱 - Google Patents

타일-기반 렌더러들에 대한 쿼리 프로세싱 Download PDF

Info

Publication number
KR20160003101A
KR20160003101A KR1020157033589A KR20157033589A KR20160003101A KR 20160003101 A KR20160003101 A KR 20160003101A KR 1020157033589 A KR1020157033589 A KR 1020157033589A KR 20157033589 A KR20157033589 A KR 20157033589A KR 20160003101 A KR20160003101 A KR 20160003101A
Authority
KR
South Korea
Prior art keywords
query
value
memory
memory location
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020157033589A
Other languages
English (en)
Korean (ko)
Inventor
아비나쉬 세트하라마이아
히텐드라 모한 간가니
나이젤 테렌스 풀
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160003101A publication Critical patent/KR20160003101A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
    • G06T15/10—Geometric effects
    • G06T15/40—Hidden part removal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Geometry (AREA)
  • Image Generation (AREA)
KR1020157033589A 2013-04-29 2014-04-21 타일-기반 렌더러들에 대한 쿼리 프로세싱 Withdrawn KR20160003101A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361817154P 2013-04-29 2013-04-29
US61/817,154 2013-04-29
US14/014,118 2013-08-29
US14/014,118 US9589314B2 (en) 2013-04-29 2013-08-29 Query processing for tile-based renderers
PCT/US2014/034833 WO2014179097A1 (en) 2013-04-29 2014-04-21 Query processing for tile-based renderers

Publications (1)

Publication Number Publication Date
KR20160003101A true KR20160003101A (ko) 2016-01-08

Family

ID=51788876

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157033589A Withdrawn KR20160003101A (ko) 2013-04-29 2014-04-21 타일-기반 렌더러들에 대한 쿼리 프로세싱

Country Status (6)

Country Link
US (1) US9589314B2 (https=)
EP (1) EP2992511A1 (https=)
JP (1) JP2016520909A (https=)
KR (1) KR20160003101A (https=)
CN (1) CN105144244B (https=)
WO (1) WO2014179097A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9569883B2 (en) * 2013-12-12 2017-02-14 Intel Corporation Decoupled shading pipeline
US9842428B2 (en) * 2014-06-27 2017-12-12 Samsung Electronics Co., Ltd. Dynamically optimized deferred rendering pipeline
US9298769B1 (en) * 2014-09-05 2016-03-29 Futurewei Technologies, Inc. Method and apparatus to facilitate discrete-device accelertaion of queries on structured data
US10535114B2 (en) * 2015-08-18 2020-01-14 Nvidia Corporation Controlling multi-pass rendering sequences in a cache tiling architecture
US10885603B2 (en) * 2015-12-25 2021-01-05 Intel Corporation Alpha blending and display update bandwidth saving during render and display operations
GB201713052D0 (en) * 2017-08-15 2017-09-27 Imagination Tech Ltd Single pass rendering for head mounted displays
US10672182B2 (en) * 2018-04-19 2020-06-02 Microsoft Technology Licensing, Llc Compact visibility state for GPUs compatible with hardware instancing
CN111209116B (zh) * 2020-01-06 2023-09-12 西安芯瞳半导体技术有限公司 一种分配显存空间的方法、装置及计算机存储介质

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6636215B1 (en) 1998-07-22 2003-10-21 Nvidia Corporation Hardware-assisted z-pyramid creation for host-based occlusion culling
US6952206B1 (en) 2002-08-12 2005-10-04 Nvidia Corporation Graphics application program interface system and method for accelerating graphics processing
GB0425204D0 (en) * 2004-11-15 2004-12-15 Falanx Microsystems As Processing of 3-dimensional graphics
US7425956B1 (en) 2005-06-21 2008-09-16 Nvidia Corporation System and method for occlusion testing with deferred rendering
US7519797B1 (en) * 2006-11-02 2009-04-14 Nividia Corporation Hierarchical multi-precision pipeline counters
CA2734613C (en) * 2008-08-19 2020-06-09 Digimarc Corporation Methods and systems for content processing
US8471858B2 (en) 2009-06-02 2013-06-25 Qualcomm Incorporated Displaying a visual representation of performance metrics for rendered graphics elements
JP5392199B2 (ja) * 2010-07-09 2014-01-22 ソニー株式会社 画像処理装置および方法
US8902228B2 (en) * 2011-09-19 2014-12-02 Qualcomm Incorporated Optimizing resolve performance with tiling graphics architectures
GB201116438D0 (en) * 2011-09-22 2011-11-02 Advanced Risc Mach Ltd Occlusion queries in graphics processing

Also Published As

Publication number Publication date
WO2014179097A1 (en) 2014-11-06
US20140320512A1 (en) 2014-10-30
JP2016520909A (ja) 2016-07-14
CN105144244B (zh) 2018-06-15
CN105144244A (zh) 2015-12-09
EP2992511A1 (en) 2016-03-09
US9589314B2 (en) 2017-03-07

Similar Documents

Publication Publication Date Title
US9483861B2 (en) Tile-based rendering
CN105122310B (zh) 用于基于瓦片的渲染的帧内时戳
US10885607B2 (en) Storage for foveated rendering
US9589314B2 (en) Query processing for tile-based renderers
KR101800987B1 (ko) 계층적 z-컬링을 수행하기 위한 부분적으로-커버된 타일들의 선택적 병합
EP3180773B1 (en) Bandwidth reduction using texture lookup by adaptive shading
US10078883B2 (en) Writing graphics data from local memory to system memory
US20180182066A1 (en) Foveated rendering in tiled architectures
US9659399B2 (en) System, method, and computer program product for passing attribute structures between shader stages in a graphics pipeline
US9721381B2 (en) System, method, and computer program product for discarding pixel samples
US20170243375A1 (en) Multi-step texture processing with feedback in texture unit
US10580151B2 (en) Tile-based low-resolution depth storage
US9305388B2 (en) Bit-count texture format

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20151125

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid