KR20150136148A - Display device and display panel - Google Patents

Abstract

The present invention relates to a display device and a display panel thereof. The display device comprises: a gate driving integrated circuit for receiving driving voltage and a clock signal, and outputting a scan signal to a gate line; and a driving voltage control unit for controlling a level of the driving voltage according to change of voltage of a monitoring node connected to an output node where the scan signal is outputted in the gate driving integrated circuit, and outputting the driving voltage to the gate driving integrated circuit.

Description

[0001] DISPLAY DEVICE AND DISPLAY PANEL [0002]

The present invention relates to a display device and a display panel.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. In recent years, a liquid crystal display (LCD), a plasma display panel (Plasma Display Panel) Light Emitting Display Device) have been utilized.

The display device includes a data driver for generating data signals to the data lines, a gate driver for supplying a scan signal to the gate lines, And a timing controller for controlling the driving timing of the driving unit and the gate driving unit.

In the display device, the gate driver includes a plurality of gate driver ICs. The gate driver IC receives a clock signal and a driving voltage, and outputs a scan signal to the corresponding gate line. For this purpose, An up-transistor and a pull-down transistor, and a circuit section for controlling the operation of these transistors.

Since each gate driving integrated circuit outputs a high-level scan signal for a short time, a high voltage is applied to the pull-down transistor connected to the Qb (Q bar) node for a long time and the gate of the pull- A phenomenon occurs in which the voltage is shifted. Such a threshold voltage transfer phenomenon causes a circuit malfunction and shortens the lifetime of the gate drive integrated circuit.

In view of the above, it is an object of the present invention to provide a display device and a display panel capable of effectively applying a driving voltage to each gate driving integrated circuit.

It is another object of the present invention to provide a display device and a display panel for controlling a driving voltage so that a high voltage fixed for a long time is not applied to a pull-down transistor connected to a Qb node in each gate driving integrated circuit.

In order to accomplish the above object, in one aspect, the present invention provides a liquid crystal display comprising: a gate driving integrated circuit for receiving a driving voltage and a clock signal, outputting a scan signal to a gate line, or outputting a dummy signal; And a driving voltage controller for controlling the magnitude of the driving voltage according to a change in the voltage of the monitoring node connected to the output node of the scan signal in the gate driving integrated circuit and outputting the adjusted driving voltage to the gate driving integrated circuit .

In another aspect, the present invention provides a display panel comprising: a gate line for transmitting a scan signal to a pixel column; And a pull-down transistor and a pull-down transistor connected to the gate line, the pull-down transistor and the pull-down transistor being connected to the gate line and receiving the clock signal and the driving voltage whose magnitude is continuously adjusted for a continuous time interval, And a gate driving integrated circuit for outputting a signal to the gate line.

As described above, according to the present invention, it is possible to provide a display device and a display panel capable of effectively applying a driving voltage to each gate driving integrated circuit.

According to the present invention, it is possible to provide a display device and a display panel in which a high voltage fixed for a long time is not applied to a pull-down transistor connected to a Qb node in each gate driving integrated circuit through a driving voltage control.

Further, according to the present invention, it is possible to provide a display device and a display panel capable of minimizing the movement and speed of a threshold voltage of a pull-down transistor or the like connected to a Qb node in each gate driving integrated circuit through drive voltage control .

Further, according to the present invention, it is possible to provide a display device and a display panel which can prevent a malfunction and a shortened life span of a gate drive integrated circuit through drive voltage control.

Further, according to the present invention, continuous driving voltage control is performed for a continuous time period, thereby enabling efficient and precise gate driving.

Further, according to the present invention, it is possible to perform more efficient and precise gate driving by monitoring the threshold voltage shift of the transistors in the gate driving integrated circuit and controlling the driving voltage based on the monitoring of the threshold voltage shift in the same environment as the actual operation of the gate driving integrated circuit .

1 is a diagram showing a schematic system of a display device according to an embodiment.
2 is a view showing a part of a display panel when the gate driver of the display device according to the embodiment is implemented as GIP type gate drive integrated circuits.
3 is a diagram showing a gate drive integrated circuit and a drive voltage control configuration of a display device according to an embodiment.
4 is a view for explaining the principle of controlling the driving voltage applied to the gate driving integrated circuit of the display device according to the embodiment.
5 is a graph illustrating a threshold voltage transfer phenomenon of the monitoring transistor in the gate driving integrated circuit of the display device according to the embodiment.
6 is a graph of a driving voltage according to driving voltage control applied to the gate driving integrated circuit of the display device according to the embodiment.
7 is a graph showing the relationship between the threshold voltage shift of the monitoring transistor in the gate driving integrated circuit of the display apparatus according to the embodiment and the driving voltage applied to the gate driving integrated circuit controlled by the driving voltage control unit.
8 is a graph showing a change in threshold voltage of the monitoring transistor inside the gate driving integrated circuit of the display device according to the embodiment and a driving voltage applied to the gate driving integrated circuit controlled by the driving voltage controlling part over time.
9 and 10 are graphs showing the operation timings of the first switch and the second switch together with the scan signal waveform in order to control a driving voltage applied to the gate driving integrated circuit of the display device according to the embodiment.
11 is an illustration of an example of a gate drive integrated circuit of a display device according to an embodiment.
12 is a diagram showing a main signal waveform and a voltage waveform of a main node applied to the gate driving integrated circuit of the display apparatus according to the embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

FIG. 1 is a diagram showing a schematic system of a display device 100 according to an embodiment.

1, a display device 100 according to an embodiment includes m data lines DL1 to DLm and n gate lines GL1 to GLn formed in a direction crossing each other and m data lines DL1 A display panel 110 in which a pixel P is defined by intersecting n gate lines GL1 to GLn and m data lines DL1 to DLm for driving m data lines DL1 to DLm, A data driver 120 for supplying data voltages to the n gate lines GL1 to GLm to sequentially drive the n gate lines GL1 to GLn, A timing controller (not shown) for controlling the driving timings of the driving unit 130, the data driving unit 120 and the gate driving unit 130 and outputting various control signals to the data driving unit 120 and the gate driving unit 130, 140).

The data driver 120 may include a plurality of data driver ICs (also referred to as source driver ICs), which may be a Tape Automated Bonding (TAB) May be connected to a bonding pad of the display panel 110 by a chip on glass (COG) method or may be formed directly on the display panel 110 and may be formed on the display panel 110, It is possible.

1, the gate driver 130 may be located on one side of the display panel 110, or on both sides of the display panel 110 in two, depending on the driving method.

In addition, the gate driver 130 may include a plurality of gate driver integrated circuits (GDICs). The plurality of gate driver integrated circuits (GDICs) may include a plurality of gate driver ICs, such as Tape Automated Bonding ) Or a chip on glass (COG) method, or may be directly formed on the display panel 110 by being implemented in a GIP (Gate In Panel) type and directly connected to a bonding pad of the display panel 110, The display panel 110 may be formed by being integrated with the display panel 110. [

Each of the plurality of gate driving integrated circuits GDIC includes at least one clock signal CLK and a high level voltage such as a driving voltage Vdd to supply a scan signal to the gate line GL. VDD), etc.), at least one low-level voltage (e.g., a base voltage VSS), and the like, and outputs a scan signal through an internal circuit.

Some of the plurality of gate driving integrated circuits (GDIC) may not be connected to the gate line GL. In this case, the gate drive integrated circuit GDIC not connected to the gate line GL may output a dummy signal as a kind of scan signal. At this time, the driving voltage VDD applied to each gate driving integrated circuit GDIC of the display device 100 according to the embodiment is not a fixed voltage but a variable voltage.

The driving voltage VDD applied to each gate driving integrated circuit GDIC of the display device 100 according to the embodiment is not a fixed high voltage but may be a voltage starting from a low voltage and gradually increasing in some situations have.

The driving voltage control for varying the driving voltage VDD applied to each gate driving integrated circuit GDIC of the display device 100 according to the embodiment will be described in more detail below.

Hereinafter, the gate drive integrated circuit GDIC of the display device 100 according to the embodiment will be described as an example of a GIP (Gate In Panel) type formed directly on the display panel 110. FIG.

Meanwhile, the display device 100 according to the embodiment may be, for example, a liquid crystal display (LCD) or an organic light emitting display.

2 is a block diagram illustrating the structure of a display panel according to an embodiment of the present invention when the gate driver 130 of the display device 100 is implemented as GIP (Gate In Panel) type gate drive integrated circuits (GDIC) And a portion of the panel 110.

Referring to FIG. 2, a plurality of gate lines GL1, GL2, GL3,... Are formed in one direction for transferring a scan signal SCAN to each pixel line, A plurality of gate driving integrated circuits GDIC1, GDIC2, GDIC3, ... are connected to each of the gate lines GL1, GL2, GL3, ... to output scan signals SCAN1, SCAN2, SCAN3, do.

Each of the plurality of gate driving integrated circuits GDIC1, GDIC2, GDIC3, ... includes a pull-up transistor, a pull-down transistor, And a control circuit section for controlling the control section.

Here, the pull-up transistor Tup is also referred to as a buffer transistor (Tbuffer: Buffer Transistor). In addition, the pull-down transistor Tdown is a transistor involved in voltage monitoring for driving voltage control and is also referred to as a monitoring transistor (Tm).

Each of the plurality of gate drive integrated circuits GDIC1, GDIC2, GDIC3 ... includes at least one clock signal CLK, a high level voltage (e.g., a drive voltage VDD), at least one low level (For example, a base voltage VSS), and outputs a scan signal through an internal circuit.

The driving voltage VDD applied to each of the plurality of gate driving integrated circuits GDIC1, GDIC2, GDIC3, ... may be a variable voltage instead of a fixed voltage.

In particular, the driving voltage VDD applied to each of the plurality of gate driving integrated circuits GDIC1, GDIC2, GDIC3, ... may be a voltage whose magnitude is continuously adjusted for a continuous time period.

Hereinafter, a method of controlling the driving voltage VDD applied to one gate driving integrated circuit (GDIC) and its configuration will be described in more detail with reference to FIGS. 3 to 9. FIG.

3 is a diagram showing a gate drive integrated circuit (GDIC) and a drive voltage control configuration of the display device 100 according to the embodiment.

3, a display device 100 according to an embodiment includes a gate driving IC (not shown) for receiving a driving voltage VDD and a clock signal CLK and outputting a scanning signal SCAN to a gate line GL And the voltage Vm of the monitoring node Nm connected to the output node No at which the scan signal SCAN is output from the gate driving integrated circuit GDIC And a driving voltage control unit 300 for outputting the adjusted driving voltage to the corresponding gate driving integrated circuit GDIC.

 3, the driving voltage control unit 300 continuously monitors the voltage Vm of the monitoring node Nm for a monitoring time interval corresponding to a continuous time interval, and at the same time, The voltage Vm of the monitoring node Nm may be compared with the voltage Vm of the monitoring node Nm and the magnitude of the driving voltage VDD to be applied to the gate driving integrated circuit GDIC may be adjusted according to the comparison result.

3, a driving voltage control unit 300 includes a first input terminal Vin1 to which a voltage Vm of the monitoring node Nm is applied and a second input terminal Vin1 to which a reference voltage Vref is applied, There is an input stage Vin2 and an output stage Vout for outputting a controlled driving voltage VDD.

3, in addition to the driving voltage control unit 300, the driving voltage control unit 300 includes a first node Vin1 connected between the monitoring node Nm and the first input terminal Vin1 of the driving voltage control unit 300, And may further include a switch SW1.

The first switch SW1 is turned on during the monitoring time interval so that the voltage Vm of the monitoring node Nm is controlled to be applied to the first input terminal Vin1 of the driving voltage controller 300 .

3, the reference voltage Vref may further include a second switch SW2 connected between a second input terminal Vin2 of the driving voltage control unit 300 and a reference voltage supply unit (not shown) have.

The second switch SW2 may control the reference voltage Vref to be applied to the second input terminal of the driving voltage controller 300.

The timing at which the drive voltage control unit 300 monitors the voltage Vm of the monitoring node Nm by the on-off switching operation of the first switch SW1 and the second switch SW2 And the timing for controlling the driving voltage VDD can be controlled.

That is, the monitoring time interval can be controlled by the on-off switching operation of the first switch SW1 and the second switch SW2.

Here, the monitoring time interval may be, for example, an entire interval or a partial interval of a blank time between frames, or may be a full interval of a time when the pullup transistor Tup is off, Or the full or partial section of time during which the pull-up transistor Tup is off and the Qb (Q bar) node is not low level.

In other words, the first switch SW1 may be turned on during the entire time period during which the voltage of the scan signal SCAN becomes a low level voltage or during some time periods of the entire time period.

On the other hand, the second switch SW2 may be always turned on or may be turned on only for a part of the time in some cases.

The second switch SW2 is turned on in synchronization with the timing at which the first switch SW1 is turned on when the second switch SW2 is turned on only for a part of the time, . That is, the second switch SW2 may perform the same on-off switch operation as the first switch SW1.

On the other hand, assuming that the second switch SW2 is turned on when the first switch SW1 is turned on, the drive voltage VDD for one monitoring time period in which the first switch SW1 is turned on, May be a continuous function with no discontinuity point for one monitoring time interval.

3, one end of a capacitor C1 may be connected between the first switch SW1 and the driving voltage control unit 300. In addition,

This capacitor C1 serves to maintain the voltage Vm of the monitoring node Nm until the next monitoring time interval starts.

On the other hand, one end of the other capacitor C2 may be connected between the second switch SW2 and the drive voltage control unit 300. [

On the other hand, in order to monitor the voltage Vm of the monitoring node Nm, the resistance element R may be connected between the monitoring node Nm and a set voltage terminal to which the set voltage Vset is applied.

Here, the set voltage Vset is lower than the base voltage V1 connected to the source or the drain of the pull-down transistor Tdown.

By implementing the driving voltage control structures 300 (SW1, SW2, R, C1, C2, etc.) as described above, the driving voltage can be controlled more efficiently and accurately.

The driving voltage control structures 300, SW1, SW2, R, C1, C2 and the like as described above are controlled by the voltage Vm (Vm) of the monitoring node Nm in a state in which the circuit is constituted together with the gate driving integrated circuit ) To control the driving voltage VDD will be described in more detail with reference to Fig.

3 is formed on a source printed circuit board (SPCB) connected to the display panel 110. The driving voltage control structures 300, SW1, SW2, R, C1, C2, And may be formed on a printed circuit board such as a control printed circuit board (CPCB) in some cases.

A set of the driving voltage control structures 300 (for example, SW1, SW2, R, C1, C2, etc.) illustrated in FIG. 3 is formed in correspondence with each gate driving integrated circuit GDIC Or may be formed in a smaller number than the number of gate driving integrated circuits (GDIC).

If there is only one set of the drive voltage control structures 300 (e.g., 300, SW1, SW2, R, C1, C2, etc.) and a plurality of gate drive integrated circuits A switching element (not shown) for connecting the output node No of the gate drive integrated circuit to be monitored among the two or more gate driving integrated circuits GDIC while being switched to the monitoring node Nm, ) May be further included. Here, the switching element selectively connects two output nodes No to the monitoring node Nm.

4 is a view for explaining a control principle of the driving voltage VDD applied to the gate driving integrated circuit (GDIC) of the display device 100 according to the embodiment.

The circuit configuration for monitoring the voltage Vm of the monitoring node Nm as the resistance element R is connected between the monitoring node Nm and the set voltage terminal to which the set voltage Vset is applied is as shown in Fig. It can be expressed simply and equivalently.

4, the voltage monitoring circuit includes a resistor Rm corresponding to the monitoring transistor Tm in the gate drive integrated circuit GDIC between the base voltage V1 and the set voltage Vset, ) Are connected in series.

When the first switch SW1 is turned on, the voltage at the point where the monitoring transistor Tm and the resistor R are connected in series is the voltage Vm of the monitoring node Nm, Is applied to the input terminal Vin1 and monitored.

That is, the driving voltage control unit 300 monitors the voltage Vm of the monitoring node Nm applied to the first input terminal Vin1.

The driving voltage control unit 300 compares the voltage Vm of the monitoring node Nm learned according to the monitoring result with the reference voltage Vref applied to the second input terminal Vin2, VDD) can be adjusted.

At this time, the voltage Vm of the monitoring node Nm may be monitored differently depending on the state of the monitoring transistor Tm, that is, according to the resistance Rm corresponding to the pull-down transistor Tdown.

Therefore, when the state of the monitoring transistor Tm is changed, that is, when the resistance Rm corresponding to the pull-down transistor Tdown is changed, the voltage Vm of the monitoring node Nm is monitored differently, VDD) may be adjusted differently.

Here, the state of the monitoring transistor Tm, that is, the resistance Rm corresponding to the pull-down transistor Tdown is a pull-down transistor corresponding to the characteristic value of the pull-down transistor Tdown The threshold voltage (Vth: Threshold Voltage) of the transistor Tdown is not constant but varies.

In this specification, the phenomenon that the threshold voltage Vth of the pull-down transistor Tdown changes (moves) is referred to as "threshold voltage shift (Vth shift)".

In the conventional gate driving integrated circuit GDIC, since the high driving voltage VDD fixed to the Qb node is applied, the threshold voltage shift of the pull-down transistor Tdown occurs, and the threshold voltage shift speed also increases.

The threshold voltage transfer of the pull-down transistor Tdown may cause circuit malfunction. In addition, the threshold voltage shift of the pull-down transistor Tdown may shorten the lifetime of the gate drive integrated circuit GDIC.

Thus, in the present embodiment, monitoring of the voltage Vm of the monitoring node Nm that the state of the monitoring transistor Tm, that is, the resistance Rm, has changed due to the threshold voltage shift phenomenon of the pull-down transistor Tdown And adjusts to increase or decrease the magnitude of the driving voltage VDD according to the result.

The driving voltage controller 300 of the present embodiment adjusts the magnitude of the driving voltage VDD but applies the driving voltage VDD at a low voltage level and the threshold voltage shift phenomenon of the pull down transistor Tdown The magnitude of the driving voltage VDD is gradually increased to control the high driving voltage VDD to be applied.

The driving voltage control unit 300 according to the present embodiment controls the voltage Vm of the monitoring node Nm by shifting (Vth Shift) to the threshold voltage Vth of the monitoring transistor Tm in the gate driving integrated circuit GDIC And the difference between the reference voltage Vref and the voltage Vm of the monitoring node Nm when the difference between the reference voltage Vref and the voltage Vm of the monitoring node Nm exceeds a certain level, The magnitude of the driving voltage VDD can be adjusted.

For example, the driving voltage control unit 300 according to the present embodiment increases the threshold voltage Vth of the monitoring transistor Tm in the gate driving integrated circuit GDIC so that the threshold voltage Vth in the positive (+) direction When the voltage Vm of the monitoring node Nm is monitored to decrease, the control of increasing the magnitude of the driving voltage VDD can be performed.

Describing again, a threshold voltage transfer phenomenon occurs in which the threshold voltage of the pull-down transistor Tdown is increased, so that the resistance Rm corresponding to the pull-down transistor Tdown becomes larger and a voltage drop occurs in the resistor Rm , The voltage Vm of the monitoring node Nm becomes smaller and the driving voltage control unit 300 confirms that the difference Vref-Vm between the reference voltage Vref and the voltage Vm of the monitoring node Nm is increased . Accordingly, the driving voltage control unit 300 can control to increase the magnitude of the driving voltage VDD.

The threshold voltage Vth of the monitoring transistor Tm in the gate drive integrated circuit GDIC is reduced and the threshold voltage shift in the negative (-) direction It is possible to perform control to reduce the magnitude of the driving voltage VDD when the voltage Vm of the monitoring node Nm is monitored to increase.

Describing again, a threshold voltage transfer phenomenon in which the threshold voltage of the pull-down transistor Tdown is reduced causes a resistance Rm corresponding to the pull-down transistor Tdown to decrease, and a voltage drop The voltage Vm of the monitoring node Nm becomes larger and the driving voltage controller 300 controls the driving voltage control unit 300 such that the difference Vref-Vm between the reference voltage Vref and the voltage Vm of the monitoring node Nm is small I can confirm that it is gone. Accordingly, the driving voltage control unit 300 can control to reduce the magnitude of the driving voltage VDD.

On the other hand, the driving voltage controller 300 can adjust the magnitude of the driving voltage VDD between an initial setting voltage (Initial Voltage) and a limit voltage (Limited Voltage).

According to the driving voltage control as described above, the voltage applied to the Qb node can be minimized, and the occurrence of the threshold voltage shift phenomenon or the threshold voltage shift speed can be minimized.

As a result, it is possible to prevent a circuit malfunction due to a threshold voltage shift phenomenon, and to prolong the life of the gate drive integrated circuit (GDIC).

In addition, according to the voltage monitoring method of this embodiment, it becomes possible to monitor the threshold voltage transfer phenomenon in the same environment as the circuit actually operating, and this can precisely provide drive voltage control that is very suitable for actual operation conditions .

6 is a graph of the driving voltage according to the driving voltage control applied to the gate driving integrated circuit (GDIC) of the display device 100 according to the embodiment. 6A and 6B, it is assumed that the driving voltage VDD is controlled to increase from VDD1 to VDD2 for one monitoring time period t1 to t2.

Referring to FIG. 6A, the driving voltage control unit 300 may continuously adjust the driving voltage VDD for one monitoring time interval t1 to t2.

That is, the driving voltage control unit 300 determines whether the function of the driving voltage VDD for one monitoring time period t1 to t2 is a continuous function in which there is no discontinuity point for one monitoring time period t1 to t2 So that the magnitude of the driving voltage VDD can be adjusted.

6B, the driving voltage control unit 300 discretizes the driving voltage VDD for one monitoring time period t1 to t2, as shown in FIG. 6B, (Discrete) control.

According to this discrete control method, as shown in FIG. 6B, the function of the driving voltage VDD for one monitoring time period t1 to t2 is a function of the discontinuous function ( For example, a step function).

6A and 6B can be applied. However, by using the control method shown in FIG. 6A, it is possible to minimize the voltage applied to the node Qb, And the threshold voltage transfer speed can be maximized. As a result, it is possible to prevent the circuit malfunction due to the threshold voltage transfer phenomenon more effectively, and the lifetime of the gate drive integrated circuit (GDIC) Therefore, it is possible to control the drive voltage more precisely.

In the following, the relation of controlling the driving voltage VDD in accordance with the variation of the threshold voltage Vth of the monitoring transistor Tm corresponding to the pull-down transistor Tdown and the relation of controlling the threshold voltage Vd of the monitoring transistor Tm (Vth) and the driving voltage (VDD) will be described with reference to FIGS. 7 and 8. FIG.

7 is a timing chart showing the shift of the threshold voltage Vth of the monitoring transistor Tm in the gate driving integrated circuit GDIC of the display device 100 according to the embodiment and the driving voltage control of the gate driving integrated circuit And a driving voltage VDD applied to the gate electrode GDIC.

7, when a threshold voltage shift occurs in a direction in which the threshold voltage Vth of the monitoring transistor Tm in the gate driving integrated circuit GDIC increases, the driving voltage control unit 300 controls the driving voltage VDD) may be increased.

7, when a threshold voltage shift occurs in a direction in which the threshold voltage Vth of the monitoring transistor Tm in the gate driving integrated circuit GDIC decreases, the driving voltage control unit 300 controls the driving voltage VDD) can be performed.

However, the driving voltage control unit 300 may adjust the magnitude of the driving voltage VDD between the initial setting voltage (Initial Voltage) and the limit voltage (Limited Voltage).

8 is a graph showing the relationship between the threshold voltage Vth of the monitoring transistor Tm in the gate driving integrated circuit GDIC of the display device 100 according to the embodiment and the threshold voltage Vth of the gate driving integrated circuit GDIC ) Of the driving voltage (VDD).

8, when a threshold voltage shift occurs in a direction in which the threshold voltage Vth of the monitoring transistor Tm increases in accordance with the increase of the driving time, the driving voltage control unit 300 sets the driving voltage VDD to , And the magnitude of the driving voltage (VDD) can be controlled by giving a predetermined margin (Margin) higher than the threshold voltage (Vth).

8, when a threshold voltage shift occurs in a direction in which the threshold voltage Vth of the monitoring transistor Tm decreases in accordance with an increase in the driving time, the driving voltage control unit 300 sets the driving voltage VDD to And the magnitude of the driving voltage VDD can be controlled by giving a margin that is higher than the varying threshold voltage Vth.

The first switch SW1 and the second switch SW2 for controlling the timing for monitoring the voltage Vm of the monitoring node Nm for driving voltage control as described above and the driving voltage control timing accordingly, Will be described again with reference to Figs. 9 and 10. Fig.

9 and 10 are diagrams for explaining the operation of the first switch SW1 and the second switch SW2 in order to control the drive voltage VDD applied to the gate drive integrated circuit GDIC of the display device 100 according to the embodiment. And the operation timing thereof together with the scan signal (SCAN) waveform.

9 and 10, a first switch SW1 connected between the monitoring node Nm and the first input terminal Vin1 of the driving voltage control unit 300, and a second switch SW2 connected between the monitoring node Nm and the driving voltage control unit 300, One monitoring time interval is defined by turning on the second switch SW2 connected between the second input terminal Vin2 of the switching elements 300 and the reference voltage supply unit (not shown).

9 and 10, the first switch SW1 is turned on when the output signal Vgout of the gate drive integrated circuit GDIC, that is, the scan signal SCAN becomes a low level voltage And may be on during a time interval or some time interval of the entire time interval.

On the other hand, the second switch SW2 may be always turned on as shown in Fig. 9, or may be turned on when the first switch SW1 is turned on as shown in Fig. 10 It may be turned on in synchronization with the timing.

The on-off switching operation of the first switch SW1 and the second switch SW2 as described above may be controlled by a control signal output from the timing controller 140 or may be controlled by another integrated circuit.

The gate driving integrated circuit GDIC of the display device 100 according to the embodiment described above is provided with a pull-up transistor Tup and a pull-up transistor Td to receive a clock signal, a driving voltage, and the like and output scan signals SCAN and Vgout. Down circuit includes a pull-down transistor Tdown and a circuit for controlling the operation of these transistors Tup and Tdown.

The circuit configuration of such a gate drive integrated circuit GDIC varies greatly depending on the number of clock signals (for example, 2, 4, 6, etc.) for the gate drive, the position on the display panel 110, .

11 is an exemplary view of a gate drive integrated circuit (GDIC) of the display device 100 according to the embodiment. 12 is a diagram showing waveforms of main signals (VST1, CLK1 to CLK4) and voltage waveforms of main nodes (Q node, Qb node) applied to the gate drive integrated circuit (GDIC) of the display device 100 according to the embodiment to be.

11, gate driving is performed by a four-phase driving method using four clock signals CLK1, CLK2, CLK3, and CLK4 for gate driving, and pull-up transistors Tup and M6 and pull- M3, M3, M41, M4q, M4, M5q, M6w, M7w) for controlling the operation of the transistors Q1, (GDIC) for the case of including a gate drive IC

Referring to FIG. 12, the voltage of the Q bar (Qb) node is maintained at a high level for a long time when the Q node becomes a low level, that is, a long time when the scan signal Vgout becomes a low level.

Therefore, in the case of the transistors M7, M7w, and M3 connected to the node Qb, a high voltage may be applied to the gate for a long period of time to cause a threshold voltage shift. Such threshold voltage shift may cause circuit malfunction.

Therefore, in this embodiment, the transistors M7, M7w, and M3 connected to the Qb node, which may be the monitoring transistor Tm, can be controlled by gradually applying the driving voltage, which is a voltage component applied to the Qb node, ) And the rate of occurrence of the threshold voltage can be minimized.

Referring to Fig. 12, in driving voltage control, the driving voltage VDD can be controlled for a whole period or a partial period of time during which the voltage of the Qb node becomes a high level.

As described above, according to the present invention, it is possible to provide a display device 100 and a display panel 110 that can effectively apply a driving voltage to each gate driving integrated circuit (GDIC).

Further, according to the present invention, a display device 100 and a display panel (not shown) in which a high voltage fixed for a long time is not applied to a pull-down transistor connected to a Qb node in each gate driving integrated circuit (GDIC) 110).

Further, according to the present invention, the display device 100 and the display panel 100 capable of minimizing the movement and the speed of the threshold voltage of the pull-down transistor connected to the Qb node in each gate driving integrated circuit (GDIC) (110).

According to the present invention, it is possible to provide a display device (100) and a display panel (110) that can prevent a malfunction and a shortened life span of a gate drive integrated circuit (GDIC) through drive voltage control.

Further, according to the present invention, continuous driving voltage control is performed for a continuous time period, thereby enabling efficient and precise gate driving.

Further, according to the present invention, by monitoring the threshold voltage shift of the transistor in the gate drive integrated circuit (GDIC) and controlling the drive voltage based on this, in an environment identical to the environment in which the gate drive integrated circuit (GDIC) actually operates, And it is possible to perform precise gate driving.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: Gate driver
140: Timing controller
300: driving voltage control unit
GDIC: Gate Driver IC

Claims (14)

A gate driving integrated circuit receiving a driving voltage and a clock signal and outputting a scan signal to a gate line or a dummy signal; And
And a driving voltage controller for controlling the magnitude of the driving voltage according to a change in the voltage of the monitoring node connected to the output node of the scan signal or the dummy signal in the gate driving integrated circuit and outputting the adjusted driving voltage to the gate driving integrated circuit . The method according to claim 1,
Wherein the driving voltage control unit includes:
Monitors the voltage of the monitoring node during a monitoring time interval corresponding to a continuous time interval, and adjusts the magnitude of the driving voltage by comparing the reference voltage and the voltage of the monitoring node. 3. The method of claim 2,
And a first switch connected between the monitoring node and a first input terminal of the driving voltage control unit. The method of claim 3,
Wherein the function of the driving voltage with respect to a time period during which the first switch is on is a continuous function. The method of claim 3,
Wherein the first switch comprises:
Wherein the scan signal is turned on during a whole time period during which the voltage of the scan signal becomes a low level voltage or during a certain time period of the entire time period. The method of claim 3,
And a capacitor having one end connected between the first switch and the driving voltage control unit. 3. The method of claim 2,
And a second switch for controlling the reference voltage to be applied to the second input terminal of the driving voltage control unit. 8. The method of claim 7,
Wherein the second switch comprises:
The display is always turned on or turned on for a certain period of time. 8. The method of claim 7,
And a capacitor having one end connected between the second switch and the driving voltage control unit. 3. The method of claim 2,
And a resistance element connected between the monitoring node and the set voltage terminal. 11. The method of claim 10,
The monitoring transistor in the gate driving integrated circuit and the resistance element are connected in series between the base voltage and the set voltage,
A voltage at a point where the monitoring transistor and the resistance element are connected in series is monitored as a voltage of the monitoring node,
Wherein the voltage of the monitoring node is monitored differently according to the state of the monitoring transistor. 3. The method of claim 2,
Wherein the driving voltage control unit includes:
Wherein when a change in the voltage of the monitoring node is monitored by a threshold voltage shift (Vth Shift) of the monitoring transistor in the gate driving integrated circuit, a magnitude of the driving voltage is calculated based on a difference between the reference voltage and the voltage of the monitoring node And the display device. 3. The method of claim 2,
Wherein the driving voltage control unit includes:
When the threshold voltage of the monitoring transistor in the gate driving integrated circuit is increased and a threshold voltage shift in the positive direction occurs to monitor the voltage of the monitoring node to be reduced, control for increasing the size of the driving voltage is performed and,
When a threshold voltage of the monitoring transistor in the gate driving integrated circuit is reduced and a threshold voltage shift in a negative direction occurs to monitor the voltage of the monitoring node, control for decreasing the driving voltage is performed And the display device. In the display panel,
A gate line for transmitting a scan signal to a pixel column; And
And a pull-down transistor connected to the gate line and formed on the display panel, the pull-down transistor including a pull-down transistor and a pull-down transistor, the clock signal and the driving voltage whose magnitude is continuously adjusted with respect to a continuous time interval, And a gate driving integrated circuit outputting the gate driving signal to the gate line.

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