KR20150132655A - Time-digital converter and converting method thereof - Google Patents

Abstract

The present invention relates to a time-to-digital converter capable of higher order noise shaping, and a time-to-digital converting method using the same. The time-to-digital converter comprises: a time-to-digital converting unit for outputting a digital signal corresponding to the time difference between two input signals using a gated-ring oscillator (GRO); and a time-domain error feedback filter for processing quantization noise generated in the time-to-digital converting unit to have an N^th degree delta-sigma property, and providing the quantization noise as an input of the time-to-digital converter.

Description

TIME-DIGITAL CONVERTER AND CONVERTING METHOD THEREOF < RTI ID = 0.0 >

The present invention relates to a time-to-digital converter (TDC), and more particularly to a high-order delta-sigma time-to-digital converter using a gated-ring oscillator (GRO) ≪ / RTI >

A time-to-digital converter (TDC) is a device that converts the time difference between two signals into a digital signal, the input signal may be in the form of a pulse and a simple rising signal from a different source Rising signal.

As the semiconductor process technology develops, the transition time of the digital signal decreases, and the time-based resolution increases. Accordingly, studies on time-based circuits and studies on the performance improvement of time-to-digital converters have been actively conducted.

A time-to-digital converter capable of first-order noise shaping using an open-and-close circular oscillator is known as a method for reducing the quantization error and improving the performance of the time-digital converter. When the time-to-digital converter capable of shaping the first-order noise is used, the quantization noise can be relatively reduced in the low frequency band. However, as higher-specification systems are required, it is necessary to further reduce the quantization noise of the time-to-digital converter.

On the other hand, in order to reduce the quantization noise, the oscillation frequency used in the opening-and-closing ring oscillator should be increased to make the minimum usable time interval smaller. However, if the oscillation frequency increases, the power consumption increases and the circuit design becomes difficult.

It is an object of the present invention to provide a time digital converter capable of high-order noise shaping and a time digital conversion method using the same.

The present invention is also applicable to an analog-to-digital converter (ADC) and an all-digital phase-locked loop (ADPLL) with improved performance using a time-digital converter capable of high-order noise shaping. And a communication system.

A time-to-digital converter capable of high-order noise shaping according to an embodiment of the present invention includes: a time-to-digital converter for outputting a digital signal corresponding to a time difference between two input signals using an open / close circular oscillator (GRO); And a time error feedback filter for processing the quantization noise generated in the time-to-digital converter to have an N-ary delta-sigma characteristic and providing the input as an input to the time-to-digital converter.

The analog-to-digital converter according to an embodiment of the present invention includes the time-to-digital converter.

The digital phase locked loop according to an embodiment of the present invention includes the time-to-digital converter.

Also, the time-to-digital conversion method according to the embodiment of the present invention outputs a digital signal corresponding to a time difference between two input signals using a time-to-digital converter based on an open / close circular oscillator (GRO) Processing the quantization noise generated in the cyclic oscillator-based time-to-digital converter to have an N-ary delta-sigma characteristic; And providing a signal processed to have the N-ary delta-sigma characteristic as an input signal to the open-and-close circular oscillator-based time-to-digital converter.

According to an embodiment of the present invention, it is possible to perform high-order noise shaping using an open-and-closed circular oscillator-based time-to-digital converter (GRO-TDC) capable of first order noise shaping and a time-domain error feedback filter Time digital converter, it is possible to improve the performance of the time digital converter to have a high temporal resolution and a wide signal bandwidth.

In addition, as circuit fabrication processes for the implementation of high-order delta-sigma time digital converters are developed, the chip area and power consumption of communication devices can be reduced.

1 is a diagram showing an embodiment of a configuration of an open-close circular oscillator based time-to-digital converter (GRO-TDC).
2 is a timing chart for explaining the operation of the open-close circular oscillator-based time-to-digital converter (GRO-TDC).
3 is a block diagram showing an embodiment of a configuration of a time-digital converter according to the present invention.
4 is a flowchart illustrating a time digital conversion method according to an embodiment of the present invention.
5 is a diagram showing an embodiment of a configuration of a time-domain error feedback filter.
6 is a circuit diagram showing an embodiment of a configuration of a time storage unit provided in a time error feedback filter.
7 is a timing chart for explaining the operation of the time storage unit.
8 is a block diagram showing another embodiment of the configuration of the time error feedback filter.
9 is a block diagram showing another embodiment of the configuration of a time-digital converter according to the present invention.
10 is a timing chart for explaining the operation of the time error feedback filter.

The operation principle of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings and description. It should be understood, however, that the drawings and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention, and are not to be construed as limiting the present invention. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terms used below are defined in consideration of the functions of the present invention, which may vary depending on the user, intention or custom of the operator. Therefore, the definition should be based on the contents throughout the present invention.

As a result, the technical idea of the present invention is determined by the claims, and the following embodiments are merely means for effectively explaining the technical idea of the present invention to a person having ordinary skill in the art to which the present invention belongs Only.

1 illustrates an embodiment of a configuration of an open-and-close circular oscillator based time-to-digital converter (GRO-TDC), wherein the illustrated time-to-digital converter 100 includes an enable generator 110, A gated ring oscillator (GRO) 120, and a counter (Counter) 130.

Referring to FIG. 1, an enable signal generator 110 receives two input signals Start, Stop to be compared and generates an enable signal EN.

The open / close circular oscillator (GRO) 120 generates the oscillation signal GRO_OUT in response to the enable signal EN generated by the enable signal generator 110.

The counter 130 receives the oscillation signal GRO_OUT generated by the open / close circular oscillator GRO 120 and generates a digital output signal DIGITAL OUTPUT y [n].

FIG. 2 is a timing chart for explaining the operation of the open-and-close circular oscillator-based time-to-digital converter (GRO-TDC) 100 as shown in FIG.

Hereinafter, the operation of the open-and-close circular oscillator-based time-to-digital converter (GRO-TDC) 100 will be described in detail with reference to FIG. 1 and FIG.

The enable signal generator 110 receives the two input signals Start and Stop to be compared and outputs the start signal to the rising edge of the Stop signal from the rising edge of the Start signal to the rising edge of the Stop signal, Lt; RTI ID = 0.0 > EN < / RTI >

The open / close circular oscillator (GRO) 120 oscillates only when the enable signal EN is logic 'high'. If the enable signal EN is logic 'low', the oscillation is stopped and the previous phase information The oscillation can start again from the phase state according to the stored phase information when the enable signal EN becomes logic 'high'.

The counter 130 may count the number of rising edges of the oscillation signal GRO_OUT, which is the output signal of the open-close and circular oscillator GRO1, for each sampling period to provide the digital output signal y [n] .

The opening and closing ring oscillator GRO1 120 increases the phase of the oscillation signal GRO_OUT when the enable signal EN is at a logic high level and increases the phase of the enable signal EN The quantization error during the previous sampling period becomes the initial phase of the current sampling period, and the digital output signal y [n] Can be expressed by Equation (1).

N [n] represents a phase changed by the open-loop oscillator (GRO) 120, and e [n] represents a digital output signal of the counter 130 at time n Lt; / RTI >

(N + 1) represents the quantization error at time (n-1), p0 [n] represents the initial phase at time n, and p0 [n + . ≪ / RTI >

The z-transform of Equation (1) is expressed as Equation (2) below.

According to Equation (2), the open / close circular oscillator-based time-to-digital converter 100 shown in FIG. 1 has a noise transfer function having a high pass characteristic as shown in Equation 3 below. Able to know.

Therefore, the open-and-closed circular oscillator-based time-to-digital converter 100 as shown in FIG. 1 can have the first-order noise shaping characteristic.

According to an embodiment of the present invention, a high-order noise (noise) can be obtained by using an open-and-close circular oscillator based time-digital converter (GRO-TDC) 100 capable of primary noise shaping and a time- A shaping-capable time-digital converter can be constructed, thereby improving the performance of the time-digital converter to have a high temporal resolution and a wide signal bandwidth.

FIG. 3 is a block diagram of an embodiment of the time-digital converter according to the present invention. The time-to-digital converter shown in FIG. 3 includes a time-to-digital converter 100, a time error feedback filter 200, (300) and a summation unit (310).

Referring to FIG. 3, the time-to-digital converter 100 includes a digital-to-analog converter (I / O) It is possible to output the signal D _OUT .

That is, the time-to-digital converter 100 includes an enable signal generator 110 for generating an enable signal that is enabled during a time interval between rising edges of the two input signals Start and Stop, And a counter 130 for generating a digital output signal corresponding to the number of rising edges of the oscillation signal in response to the oscillation signal, Can be implemented to have a differential noise shaping characteristic.

The temporal error feedback filter 200 may process the quantization noise generated in the time-digital converter 100 so as to have an N-ary delta-sigma characteristic and provide it as an input to the time-digital converter 100.

The quantization noise generator 300 may generate the quantization noise QE generated in the time-digital converter 100 as a pulse and transmit the quantization noise QE to the time error feedback filter 200.

More specifically, the quantization noise generator 300 generates a pulse signal corresponding to the quantization noise QE generated at the output terminal of the open-and-close circular oscillator 120 provided in the time-digital converter 100, (200).

The summation unit 310 may receive the input signals Start and Stop and the signals output from the time error feedback filter 200 and output the signals to the time-to-digital converter 100.

Hereinafter, a time-to-digital converter according to an embodiment of the present invention and a conversion method using the same will be described in detail with reference to FIG. 4 to FIG.

4 is a flowchart illustrating a time digital conversion method according to an embodiment of the present invention. The conversion method shown in FIG. 4 is a block diagram showing a configuration of a time-digital converter according to an embodiment of the present invention shown in FIG. .

Referring to FIG. 4, the time error feedback filter 200 included in the time-to-digital converter processes the quantization noise generated by the time-to-digital converter 100 so as to have an N-ary delta-sigma characteristic (S400).

In order to obtain the N-th order noise shaping characteristic NTF as described above, the transfer function H _EF of the time-error feedback filter 200 may be expressed by Equation (4).

Therefore, the time error feedback filter 200 included in the time-digital converter according to the embodiment of the present invention can be designed to have the same characteristics as the transfer function H _{EF in} Equation (4).

According to an embodiment of the present invention, the transfer function (H _EF ) of the time error feedback filter 200 to have the third-order delta sigma-characteristic may be configured as shown in Equation (5).

FIG. 5 shows an embodiment of the configuration of a time-domain error feedback filter. In order to obtain the third-order delta-sigma characteristic according to the transfer function H _EF shown in Equation (5) Time error feedback filter 200 shown in FIG.

Then, the time error feedback filter 200 provides a signal processed to have the N-ary delta-sigma characteristic as described above as an input signal of the time-to-digital converter 100 (step S410).

Meanwhile, since the time error feedback filter 200 must operate in the time domain, a time operator capable of processing time information for the time error feedback filter 200 may be required.

In order to enable the above operation, the time error feedback filter 200 may include a time storage unit for storing the time signal and outputting the stored time signal in a pulse form in response to the input trigger signal.

6 is a circuit diagram showing an embodiment of the configuration of the time storage unit included in the time error feedback filter 200. As shown in FIG.

Referring to FIG. 6, a time-register (TR) is a delay unit that stores a time signal T _X , and when the trigger signal Trig is applied, (Y) in the form of a pulse.

More specifically, the time storage unit includes a capacitor C and a plurality of switches, and the input signal T _X is converted into a capacitor voltage V _C using the switches and the capacitor C, do.

Referring to the timing diagram shown in FIG. 7, the capacitor voltage (V _C ) is reset to VDD before storing the time information, and the voltage of the capacitor is discharged to the switch while the time input is applied.

When the application of the input signal is completed, the capacitor voltage V _C maintains the voltage level until the trigger signal Trig is input, and may be discharged again after the trigger signal Trig is applied.

When the capacitor voltage V _C exceeds the threshold voltages V _{TH and INV} of the inverter, an output pulse signal Y is generated. At this time, the pulse width information T _Y becomes 'T _FS -T _X '.

Meanwhile, the time information is stored by the time storage unit as described above, but the polarity is changed.

8 is a block diagram of another embodiment of the configuration of the time error feedback filter, and a description of the same configuration as that described with reference to Figs. 3 to 7 will be omitted.

Referring to FIG. 8, the time error feedback filter 200 includes a plurality of time storage units, a time multiplier, and an OR gate to implement a transfer function corresponding to the N-ary delta-sigma characteristic as described above. .

For example, the time multiplier may be implemented using a pulse-train time calculator, and the time addition and subtraction may be implemented using an OR gate.

A third order delta-sigma time digital converter having NTF = (1-z ^-1 ) ³ can be constructed by using the time digital conversion unit 100 and the time error feedback filter 200 as described above. However, in the above structure, ideally, all zeroes of the NTF must be placed in the DC, so that zero shifts may occur due to the non-ideality of the time storage.

For example, zero shifts occur due to the noise of the time storage, and thus the condition of NTF = (1-z ^-1 ) ³ can not be satisfied. Therefore, the third-order delta-sigma time digital converter Performance may be degraded.

According to another embodiment of the present invention, in order to solve the above-described deterioration in performance, another time-digital converter is provided at the preceding stage of the third-order delta-sigma time digital converter as described with reference to FIGS. (E.g., GRO-TDC) can be cascaded.

FIG. 9 is a block diagram of another embodiment of the time digital converter according to the present invention. The time digital converter shown in FIG. 3 further includes a time digital converter 150, And a 1-3 multi-stage noise-shaping (MASH) TDC structure.

The operation of each of the time digital converters 100 and 150, the quantization noise generators 300 and 350 and the time error feedback filter 200 in the time digital converter shown in FIG. 9 will be described with reference to FIGS. And therefore, the following description will be omitted.

9, the previous time digital converter 150 quantizes the input time signal T _{IN and} outputs the remaining quantization error QE ₁ to the time digital converter 100 of the subsequent stage Quantize again. Expression of the above operation is expressed as Equation 6 below.

Meanwhile, the digital cancellation filter 400 combines the digital signals output from the digital-to-analog converter 150 and digital-to-analog converter D2, The final digital output (D _OUT ) can be expressed by the following Equation (7).

Referring to Equation (7), the quantization error (QE ₁ ) of the preceding stage is removed and the quantization error (QE ₂ ) of the rear stage is left in the final digital output (D _OUT ) The quantization error (QE ₂ ) of the rear end is finally quadratic noise-shaping so that the total NTF can be (1-z ^-1 ) ⁴ .

The proposed multi-stage-noise-shaping (MASH) TDC structure, as described with reference to FIG. 9, TDC noise or time-of-day noise) can also be used to understand the principle of first-order filtering. The non-ideal effects of the real-time error feedback filter 200 are all included in D2.

The D2 is first filtered by the digital cancellation filter 400 so that the effects due to the non-ideality of the time store are naturally first filtered, so that the effect does not appear in the full-time digital converter.

In addition, higher order-to-noise can be achieved by increasing the order of the entire NTF from third to fourth order, resulting in higher time-resolution.

10 is a timing chart for explaining the operation of the time error feedback filter 200 as described above.

Referring to FIG. 10, the first time storage unit TR ₁ outputs a pulse signal having a width of 'T _FS -T _QE2 [n]' by delaying the quantization noise QE ₂ by one clock have.

The OR gate located before the second time storage unit TR ₂ can produce two pulse signals, each of width T _QE2 [n] and T _FS -T _QE2 [n-1] .

And if the pulse signal input to the second time storage unit (TR _2), the second time storage unit (TR ₂₎ is _{'T FS - (T FS -T} QE2 [n-1] + T QE2 [n]' The pulse signal having the width of the pulse signal can be outputted.

According to the above-described method, the transfer function (H _EF ) of the time error feedback filter 200 having the third-order delta-sigma characteristic can be implemented.

According to another embodiment of the present invention, by adjusting the output of at least a part of the plurality of time storage units included in the time error feedback filter 200, the delta-sigma degree of the time error feedback filter 200 is adjusted .

For example, as the output of the second time storage unit TR ₂ and the output of the fourth time storage unit TR ₄ are adjusted, the delta-sigma degree of the time error feedback filter 200 is changed to a second or third order Lt; / RTI >

The time digital conversion method according to the present invention may be implemented as a program for execution in a computer and stored in a computer-readable recording medium. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM , A magnetic tape, a floppy disk, an optical data storage device, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet).

The computer readable recording medium may be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner. And, functional programs, codes and code segments for implementing the above method can be easily inferred by programmers of the technical field to which the present invention belongs.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (16)

A time-to-digital converter capable of high-order noise shaping,
A time digital converter for outputting a digital signal corresponding to a time difference between two input signals using an open / close circular oscillator (GRO); And
And a time error feedback filter for processing the quantization noise generated in the time-to-digital converter so as to have an N-ary delta-sigma characteristic and providing it as an input to the time-to-digital converter. The apparatus of claim 1, wherein the time-to-digital converter
A time-to-digital converter having a primary noise shaping characteristic. The apparatus of claim 1, wherein the time-to-digital converter
An enable signal generator for generating an enable signal that is enabled during a time interval between rising edges of the two input signals;
An openable and closable oscillator for generating an oscillation signal in response to the enable signal; And
And a counter for generating a digital output signal corresponding to the number of rising edges of the oscillation signal in response to the oscillation signal. The method of claim 3,
And a quantization noise generator for generating a pulse signal corresponding to a quantization noise generated at an output terminal of the open-and-close circular oscillator and outputting the pulse signal to the time error feedback filter. The method according to claim 1,
And a summation unit for receiving the two input signals and the signal output from the time error feedback filter and outputting the signals to the time digital conversion unit. 2. The apparatus of claim 1, wherein the temporal error feedback filter
And a time storage unit for storing the time signal and outputting the stored time signal in a pulse form in response to an input trigger signal for operation in the time domain. 7. The apparatus of claim 6, wherein the temporal error feedback filter
A time multiplier and an OR gate for implementing a transfer function corresponding to the N-ary delta-sigma characteristic. 8. The apparatus of claim 7, wherein the time multiplier
A time-to-digital converter implemented using a pulse-train time multiplier. 8. The method of claim 7,
Wherein the delta-sigma order of the time error feedback filter is adjusted by adjusting the output of at least some of the plurality of time storage units. An analog-to-digital converter comprising the time-to-digital converter according to any one of claims 1 to 9. A digital phase locked loop comprising the time digital converter according to any one of claims 1 to 9. A time-to-digital conversion method for outputting a digital signal corresponding to a time difference between two input signals using a time-to-digital converter based on an open / close circular oscillator (GRO)
Processing the quantization noise generated in the open-and-close circular oscillator-based time-digital converter capable of first-order noise shaping to have an N-ary delta-sigma characteristic; And
And providing a signal processed to have the N-ary delta-sigma characteristic as an input signal to the open-and-close circular oscillator-based time-to-digital converter. 13. The method according to claim 12,
And a time error feedback filter having a transfer function corresponding to the N-ary delta-sigma characteristic. 14. The method of claim 13,
Generating a pulse signal corresponding to a quantization noise generated in the open-and-close circular oscillator-based time-to-digital converter; And
And transmitting the generated pulse signal to the time error feedback filter. 14. The method of claim 13,
Storing a time signal for time domain operation of the time error feedback filter; And
And outputting the stored time signal in a pulse form in response to an input trigger signal. 14. The method of claim 13,
Further comprising adjusting the delta-sigma order of the time error feedback filter by adjusting the output of at least some of the plurality of time storage units included in the time error feedback filter.

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