KR20150116995A - Vertical memory devices - Google Patents

Abstract

A vertical memory device includes channels, gate lines, first separation insulation film patterns, and second separation insulation film patterns. The channels are extended in a first direction perpendicular to the upper side of a substrate. The gate lines are extended to surround the outer sidewalls of the channels, and are separately stacked in the first direction. The first separation insulation film patterns pass through the gate lines in the first direction. The second separation insulation film patterns are formed between the first separation insulation film patterns to face each other, and pass through a part of the gate lines.

Description

{Vertical Memory Devices}

The present invention relates to a vertical memory device. More particularly, the present invention relates to a non-volatile vertical memory device having a channel perpendicular to the substrate.

Recently, vertical memory devices in which memory cells and insulating films are stacked perpendicularly from the substrate surface are being developed for high integration of memory devices. In the vertical memory device, a column or cylinder shaped channel vertically protruding from the upper surface of the substrate is provided, and a plurality of gate lines and the insulating films which are in contact with the channel are stacked.

In order to further increase the capacity and integration of the vertical memory device, it is necessary to stack more the gate lines and the insulating films in the vertical direction. In this case, stress due to stacking of a plurality of films may occur.

It is an object of the present invention to provide a vertical memory device with improved mechanical stability and operational reliability.

In order to accomplish one object of the present invention, a vertical type memory device according to embodiments of the present invention includes a vertical type memory device having channels, gate lines, first isolation insulating film patterns, . The channels extend in a first direction perpendicular to the top surface of the substrate. The gate lines extend around the outer walls of the channels and are stacked and spaced apart from each other along the first direction. The first isolation insulating film patterns penetrate the gate lines along the first direction. The second isolation insulating film pattern is formed between the first isolation insulating film patterns facing each other and penetrates a part of the gate lines.

In exemplary embodiments, the first isolation insulating film patterns may be spaced apart from each other along a second direction parallel to the upper surface of the substrate, so that the cell blocks may be defined. The cell block may include the gate lines and the plurality of channels partially separated by the first isolation insulating film patterns.

In the exemplary embodiments, the gate lines of adjacent cell blocks are connected to each other between the first isolation insulating film patterns that are parallel to the substrate surface and face in a third direction perpendicular to the second direction A connection area can be formed.

In exemplary embodiments, the second isolation insulating film pattern may be disposed in the connection region.

In exemplary embodiments, the gate lines may include a ground selection line (GSL), a word line, and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate along the first direction. The second isolation insulating film pattern may pass through the string selection line.

In the exemplary embodiments, the string selection lines of the cell blocks are separated from each other by the second isolation insulating film pattern, and the word lines and the ground selection lines of the cell blocks may be connected to each other to extend.

In the exemplary embodiments, the vertical memory device may further include a third isolation insulating film pattern that completely separates the gate lines of the adjacent cell blocks.

In the exemplary embodiments, the vertical memory device may further include dummy channels passing through the second isolation insulating film pattern.

In the exemplary embodiments, the vertical memory device may further include an impurity region formed on the substrate below the first isolation insulating film pattern.

In exemplary embodiments, the impurity regions function as a common source line (CSL), and the vertical memory device may further include a CSL connection structure connecting the impurity regions separated from each other to each other.

As described above, according to the vertical memory device according to the exemplary embodiments, each cell block can be completely isolated from each other or separated from each other by a separate insulating film pattern provided in a gate line cut pattern, and can be partially connected. Accordingly, the stress generated as the height of the cell block increases can be alleviated, and the mold structure for forming the cell block or the cell block can be prevented from falling down or tilting.

1 is a plan view illustrating a vertical memory device according to exemplary embodiments;
2 and 3 are cross-sectional views taken along lines I-I 'and II-II' of FIG. 1, respectively.
4 is a plan view illustrating a vertical memory device according to an embodiment.
5 is a cross-sectional view taken along line III-III 'of FIG.
6 is a plan view illustrating a vertical memory device according to an embodiment.
7 is a cross-sectional view taken along the line IV-IV 'of FIG. 6,
8A and 8B are plan views illustrating a vertical memory device according to an embodiment.
9 and 10 are plan views illustrating a vertical memory device according to an embodiment.
11 is a plan view for explaining a vertical type memory device according to an embodiment.
12 is a plan view for explaining a vertical type memory device according to an embodiment.
13 and 14 are cross-sectional views taken along line V-V 'of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the following description. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a vertical memory device according to exemplary embodiments; 2 and 3 are cross-sectional views taken along lines I-I 'and II-II' of FIG. 1, respectively.

In FIGS. 1 to 3, a direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and substantially perpendicular to each other are defined as a second direction and a third direction, respectively. The direction indicated by the arrow in the figure and the direction opposite thereto are described in the same direction. The definition of the above-mentioned direction is the same in all subsequent figures.

1, the vertical memory device includes a plurality of channels 130 protruding from a top surface of a substrate 100 in a first direction, a dielectric layer structure 120 surrounding an outer wall of the channel 130, And gate lines 108 formed and extended on the outer wall of the dielectric film structure 120 and spaced apart from each other along the first direction. In addition, the pad 150 may be provided on the channel 130 and the dielectric film structure 120.

The substrate 100 may comprise a semiconductor material, such as, for example, silicon, germanium. According to exemplary embodiments, the substrate 100 may function as a p-type well of the vertical memory device.

The channel 130 may protrude vertically from the upper surface of the substrate 100 and may have an essentially hollow cylinder or cup shape. In one embodiment, the channel 130 may have a substantially truncated column or pillar shape.

The channel 130 may include polysilicon or single crystal silicon and a portion of the channel 130 may be doped with a p-type impurity such as boron (B) or gallium (Ga).

In one embodiment, a semiconductor pattern 110 may be formed between the channel 130 and the upper surface of the substrate 100. The semiconductor pattern 130 may include polysilicon or single crystal silicon. In this case, the bottom surface of the channel 130 may contact the upper surface of the semiconductor pattern 110 and extend in the first direction.

The dielectric layer structure 120 may be formed on the outer wall of the channel 130 to have a cup shape or a straw shape substantially open at the bottom center portion. The dielectric layer structure 120 may be formed on the peripheral portion of the upper surface of the semiconductor pattern 110.

The dielectric film structure 120 may include a tunnel insulating film, a charge storage film, and a first blocking film sequentially stacked from the outer wall of the channel 130, though not specifically shown. For example, the stacking structure of the first blocking layer, the charge storage layer, and the tunnel insulating layer may have an ONO (Oxide-Nitride-Oxide) structure in which an oxide-nitride layer-oxide layer is sequentially stacked.

A buried film pattern 140 may be formed in the channel 130. The buried film pattern 140 may comprise an insulating material such as, for example, silicon oxide. When the channel 130 has a pillar or pillar shape that is hollow, the buried film pattern 140 may be omitted.

A pad 150 may be formed on the dielectric film structure 120, the channel 130, and the buried film pattern 140. For example, the pad 150 may have a shape that caps the dielectric film structure 120, the channel 130, and the buried film pattern 140. The pad 150 may include polysilicon or monocrystalline silicon and may further include n-type impurities such as phosphorus (P), arsenic (As), and the like.

According to exemplary embodiments, as shown in FIG. 1, a plurality of channels 140 may be formed along the third direction to form a channel column. In addition, a plurality of the channel columns may be arranged along the second direction. A plurality of pad columns corresponding to the channel column may be defined.

According to exemplary embodiments, a mold film structure can be formed by alternately and repeatedly stacking interlayer insulating films and sacrificial films on a substrate 100. [ The interlayer insulating film and the sacrificial layer may be formed using silicon oxide and silicon nitride, respectively. The mold film structure may be partially etched along the first direction to form a plurality of channel holes exposing the upper surface of the substrate 100. A semiconductor pattern 110 filling the bottom of the channel hole is formed through a selective epitaxial growth (SEG) process using the upper surface of the substrate 100 exposed by the channel hole as a seed .

Then, a dielectric film structure 120, a channel 130 and a buried film pattern 140 filling the remaining portion of the channel hole on the semiconductor pattern 110 can be sequentially formed. The upper portions of the dielectric film structure 120, the channel 130 and the buried film pattern 140 are removed through, for example, an etch-back process to form a recess, The pad 150 may be formed.

The gate line 108 may comprise a metal or a metal nitride. For example, the gate line 108 may comprise a low resistance metal or metal nitride, such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, platinum and the like.

In Figures 2 and 3, the gate line 108 is shown as being formed in six layers. In this case, for example, the lowermost gate lines 108a may be provided as a ground selection line (GSL), and four layers of gate lines 108b, 108c, and 108d , And 108e may be provided as a word line. Further, the two-layer gate lines 108f and 108g disposed on the word line may be provided in a String Selection Line (SSL). However, the number of stacked gate lines and the number of stacked layers of SSL, word lines and GSL are not particularly limited. For example, the GSL may be formed in two layers, and the word lines may be stacked with 2n (n is an integer of 3 or more) layers.

Each layer between the gate lines 108 may be provided with an interlayer insulating film pattern 106. The interlayer insulating film patterns 106 may include silicon oxide-based materials. The gate lines 108 can be insulated from each other along the first direction by the interlayer insulating film patterns 106. [

According to exemplary embodiments, the gate line 108 and the interlayer dielectric layer pattern 106 may extend along the third direction surrounding the outer walls of the plurality of channels 130. In one embodiment, as shown in FIGS. 2 and 3, the GSL 108a may surround and extend the outer wall of the semiconductor pattern 110. In this case, a second blocking film (not shown) may be formed between the GSL 108a and the outer wall of the semiconductor pattern 110.

A first isolation insulating film pattern 160 penetrating the gate lines 108 and the interlayer insulating film patterns 106 in the first direction may be formed. According to exemplary embodiments, the first isolation insulating film pattern 160 may extend in the third direction and partially cut the gate lines 108 and the interlayer insulating film patterns 106.

According to the exemplary embodiments, a connection region (CR) may be defined between the first isolation insulating film patterns 160 facing the third direction. In addition, a plurality of first isolation insulating film patterns 160 are arranged along the second direction to form a cell block (cell) including the channel columns, the gate lines 108, and the interlayer insulating film patterns 106 block: CB) can be defined. For example, one cell block CB may be defined between adjacent first insulation layer pattern 160 along the second direction.

One cell block CB may include predetermined channel sequences. For example, as shown in FIG. 1, four channel columns may be included in one cell block CB. However, the number of the channel columns included in the cell block CB is not particularly limited.

According to exemplary embodiments, the cell blocks CB in the connection region CR may be connected to each other along the second direction. For example, the gate lines 108 and the interlayer insulating layer patterns 106 included in each cell block CB are divided by the first separating insulating layer pattern 160 and extend in the third direction, May be merged in the CR and extend along the second direction.

The gate lines 108 and the interlayer insulating layer patterns 106 are connected to each other in the connection region CR so that the cell blocks CB are completely separated by the first separating insulating layer pattern 160 It is possible to prevent the cell block CB and / or the mold structure from falling down, warping, and the like.

Particularly, as the degree of integration of the vertical memory device increases, the number of stacked layers of the gate lines 108 and interlayer insulating layer patterns 106 can be increased. Accordingly, the aspect ratio of the cell block CB and / or the mold structure is increased, and stress concentration phenomenon may occur. According to exemplary embodiments, as the gate lines 108 included in the cell blocks CB and the interlayer insulating film patterns 106 are partially connected or merged in the connection region CR, And it is possible to suppress the above-mentioned collapsing and warping phenomena.

A second isolation insulating film pattern 165 partially penetrating the gate lines 108 and the interlayer insulating film patterns 106 may be formed on the connection region CR. For example, the second isolation insulating film pattern 165 may be formed between the first isolation insulating film patterns 160 facing in the third direction. The second isolation insulating film pattern 165 may have a smaller width or width than the first isolation insulating film pattern 160.

According to exemplary embodiments, some of the gate lines 108 and the interlayer insulating film patterns 106 disposed on the upper portion may be separated by the second isolation insulating film pattern 165. [ As shown in FIG. 3, the second isolation insulating film pattern 165 may pass through the SSLs 108g and 108f. Therefore, the SSLs 108g and 108f can be separated for each cell block CB by the second isolation insulating film patterns 165. [ In this case, the second isolation insulating film pattern 165 penetrates the interlayer insulating film pattern 106h between the uppermost interlayer insulating film pattern 106h and the SSLs 108g and 108f, and is disposed under the SSL 108f as the lower layer The interlayer insulating film pattern 106f can be partially penetrated.

According to exemplary embodiments, after forming the channel 130 and the pad 150, the mold structure between the adjacent channel columns may be partially etched to form an opening. The opening may include a first opening for forming the first isolation insulating film pattern 160 and a second opening for forming the second isolation insulating film pattern 165. The first opening may be provided as a gate line cut region.

The second opening may communicate the first openings adjacent to each other along the third direction, and may have a width or width smaller than the first opening. In addition, the first opening may penetrate the mold structure in the first direction to expose the upper surface of the substrate 100, and the second opening may partially penetrate the upper portion of the mold structure. Therefore, the second opening may have a smaller depth than the first opening.

Then, the sacrificial layer exposed through the first and second openings may be removed through, for example, a wet etching process, and then the gate lines 108 may be formed in the space from which the sacrificial layer is removed. The first impurity region 103 can be formed by implanting, for example, an n-type impurity through the upper surface of the substrate 100 exposed through the first opening. The first impurity region 103 may be provided as a common source line (CSL) of the vertical memory device.

The first and second isolation insulating film patterns 160 and 165 may be formed by filling the first and second openings using an insulating material such as silicon oxide.

According to the above-described exemplary embodiments, adjacent cell blocks CB are partially merged or connected through the connection region CR while defining the cell block CB through the first isolation insulating film pattern 160 . Thus, the mechanical stability of the cell blocks CB can be improved.

On the other hand, by separating the SSLs 108f and 108g of each cell block CB through the second separation insulating film pattern 165, it is possible to secure the operating characteristics of each cell block CB of the vertical memory device.

4 and 6 are plan views illustrating a vertical memory device according to an embodiment. Figs. 5 and 7 are cross-sectional views taken along line III-III 'and line IV-IV' in Figs. 4 and 6, respectively. A detailed description of the substantially same or similar configurations as those described with reference to Figs. 1 to 3 will be omitted.

Referring to FIGS. 4 and 5, a dummy channel 135 may be disposed on the connection region CR. For example, a predetermined number of dummy channels 135 may be disposed in the connection region CR along the third direction to form a dummy channel column. According to one embodiment, one dummy channel column may be disposed between the first isolation insulating film patterns 160 facing in the third direction. A dummy pad 155 may be disposed on the dummy channel 135 to define a dummy pad row.

According to one embodiment, the dummy channel 135 may penetrate the second isolation insulating film pattern 165. [

The dummy channel 135 may be designed so as not to affect the operation of the vertical memory device. For example, the dummy channel 135 and / or the dummy pad 155 may not be electrically connected to the bit line or to other wirings for signal transmission. In one embodiment. The dummy channel 135 and / or the dummy pad 155 may compensate for the p-type well characteristics of the substrate 100. In this case, the dummy pad 155 may include a p-type impurity, and the dummy pad 155 may be connected to the p-type well line.

Referring to FIGS. 6 and 7, a plurality of dummy channel columns may pass through one second isolation insulating film pattern 166. FIG. For example, the two dummy channel columns may pass through both sides of the second isolation insulating film pattern 166. [

8A and 8B are plan views illustrating a vertical memory device according to an embodiment.

Referring to FIG. 8A, the first isolation insulating film patterns 161 and the second isolation insulating film patterns 167 may be arranged asymmetrically.

For example, the second isolation insulating film patterns 167 may be arranged in a zig-zag shape in the plan view direction of the vertical memory device. In this case, a second isolation insulating film pattern 167 may be interposed between the first isolation insulating film patterns 161 adjacent to each other in the second direction. Thus, the connection regions where the gate lines 108 are merged or connected can also be jig-reordered.

In the vertical memory devices described with reference to FIGS. 1 to 7, when the second isolation insulating film patterns 167 are arranged along the second direction on the connection region CR, in the connection region CR, 1 isolation insulating film pattern 160 is formed, the sacrificial layer may not be completely removed because the etching solution is not smoothly transferred from the first opening.

However, as shown in FIG. 8A, by disposing first isolation insulating film patterns 161 on both sides of one second isolation insulating film pattern 167 in the second direction, the first isolation insulating film pattern 161 The etching solution can be smoothly transferred from the first opening for forming the etching solution. Thus, the sacrificial layer can be completely removed, and the sacrificial layer can be removed to form the gate lines 108.

Referring to FIG. 8B, dummy channels may be formed through the second isolation insulating film pattern 167, and a dummy pad 155 may be formed on the dummy channel, as described with reference to FIGS. .

9 and 10 are plan views illustrating a vertical memory device according to an embodiment.

Referring to FIG. 9, a third isolation insulating film pattern 163 that completely separates the gate lines 108 may be additionally formed.

According to one embodiment, the third isolation insulating film pattern 163 may extend entirely through the gate lines 108 and the interlayer insulating film patterns 106 along the first direction, and may extend along the third direction .

A plurality of first cell blocks CB1 are disposed on both sides of the third isolation insulating film pattern 163 and the first cell blocks CB1 are partially separated from each other by a first isolation insulating film pattern 160. [ Or may be disconnected and connected to one another in the connection area CR. The second cell block CB2 includes a predetermined number of first cell blocks CB1 and the adjacent second cell blocks CB2 are completely separated or disconnected by the third isolation insulating film pattern 163 .

As described above, the first isolation insulating film pattern 160 for partially separating the cell blocks and the third isolation insulating film pattern 163 for completely separating the cell blocks are suitably arranged to perform a desired operation of the vertical memory device Properties can be implemented.

Referring to FIG. 10, the second isolation insulating film pattern 168 may be disposed at one end of the first isolation insulating film pattern 162 in the third direction. In this case, the SSLs of the first cell blocks CB1 are separated from each other by the second isolation insulating film pattern 168, and the word lines may be connected to each other through one ends. 10, channels and / or pads 150 may not be formed on the end side to which the word lines are connected. Therefore, it is possible to secure a free space in which an additional wiring can be formed at the end side.

11 is a plan view for explaining a vertical type memory device according to an embodiment. For example, FIG. 11 is a diagram for explaining the arrangement of bit lines in the vertical type memory device.

Referring to FIG. 11, bit lines 172 and 174 electrically connected to at least one of the pads 150 may be disposed on the pads 150. Although only two bit lines 172 and 174 are shown in FIG. 11, a plurality of bit lines are disposed along the third direction, each bit line extends in the second direction, and a plurality of pads 150 and an electrical .

According to exemplary embodiments, each bit line may be formed to selectively electrically connect with pads 150 included in one cell block CB. For example, the first bit line 172 may be selectively connected to the pads 150 of the cell block CB shown in the left side of FIG. 11 through the first bit line contacts 171. The second bit line 174 may be selectively connected to the pads 150 of the cell block CB shown in the right side of FIG. 11 through the second bit line contacts 173. [

As described above, the desired operation characteristics of the vertical memory device can be realized by selectively connecting the bit lines to each cell block CB. In one embodiment, since the operation of each cell block CB can be controlled by the bit line, the second isolation insulating film pattern 165 for separating SSLs into cell blocks CB in the connection region CR is omitted It is possible.

12 is a plan view for explaining a vertical type memory device according to an embodiment. 13 and 14 are cross-sectional views taken along line V-V 'of FIG. For example, FIGS. 12 to 14 are views for explaining a CSL connection structure of the vertical memory device.

12 and 13, the first impurity region 103 provided in the CSL of the vertical type memory device is formed in a portion of the substrate 100 under the first isolation layer pattern 160, A plurality of first impurity regions 103 may be formed separately.

Therefore, according to the exemplary embodiments, a CSL connection structure for electrically connecting the first impurity regions 103 separated along the third direction to each other may be formed. The CSL connection structure may include, for example, a CSL contact and a CSL wiring.

For example, the first CSL contact 175 may contact the first impurity region 103 through the first isolation insulating film pattern 160. In one embodiment, a metal silicide pattern for reducing the contact resistance between the first impurity region 103 and the first CSL contact 175 may be further formed.

A first upper insulating film 177 is formed to cover the first isolation insulating film pattern 160 and the second isolation insulating film pattern 165 and the pads 150. The first upper insulating film 177 penetrates the first upper insulating film 177, A second CSL contact 179 may be formed which contacts the first contact 175. A first CSL wiring 180 electrically connected to the plurality of second CSL contacts 179 may be formed on the first upper insulating film 177. [

According to one embodiment, a wiring layer for further signal transmission may be further formed on the first CSL wiring 180. A second upper insulating film 183 covering the first CSL wiring 180 is formed and a wiring contact 185 penetrating the second upper insulating film 183 and in contact with the first CSL wiring 180 . A second CSL wiring 190 electrically connected to the wiring contact 185 may be formed on the second upper insulating film 183. The second CSL wiring 190 may be formed in the third upper insulating film 195.

According to exemplary embodiments, the first CSL wiring 180 and the second CSL wiring 190 may extend and cross in different directions. For example, the first CSL wiring 180 may electrically connect the first impurity regions 103 extending in the third direction and separated from each other. The second CSL wiring 190 may be electrically connected to the plurality of first CSL wirings 180 and may extend along the second direction.

Referring to FIG. 14, a second impurity region 105 extending along the third direction and connecting the first impurity regions 103 separated from each other may be formed on the substrate 100. The second impurity region 105 includes, for example, an n-type impurity and can function as a CSL line together with the first impurity region 103,

According to exemplary embodiments, the second impurity region 105 may overlap the second isolation insulating film pattern 165 in the first direction. The second impurity region 105 is formed in the dummy pad 155 and the dummy channel 135 in the case where the dummy pad 155 and the dummy channel 135 penetrating the second isolation insulating film pattern 165 are formed. ) In the first direction.

The second impurity region 105 may be formed on the substrate 100 by implanting an impurity into the upper portion of the substrate 100 before forming the mold structure. In this case, the second impurity region 105 may be formed to have a narrower width than the first impurity region 103 in order to prevent defects such as short-circuiting due to misalignment with the channel 130 in the subsequent process.

In the vertical memory device according to the exemplary embodiments of the present invention, the first and second isolation insulating film patterns, which partly separate the cell blocks, and the second isolation insulating film pattern that separates the SSL of each cell block, It is possible to implement the operation characteristics of the cell block unit by merging and / or connecting the cells. Thus, a vertical memory device according to exemplary embodiments can be utilized for a highly integrated non-volatile memory device implementation with increased number of stacks in the vertical direction.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the present invention can be changed.

CB: Cell block CR: Connection area
CB1: first cell block CB2: second cell block
100: substrate 103: first impurity region
105: second impurity region 106: interlayer insulating film pattern
108: gate line 110: semiconductor pattern
120: dielectric film structure 130: channel
135: dummy channel 140: buried film pattern
150: pad 155: dummy pad
160, 161, and 162: a first isolation insulating film pattern
163: Third separation insulating film pattern
165, 166, 167, 168: the second separation insulating film pattern
171: first bit line contact
172: first bit line 173: second bit line contact
174: second bit line 175: first CSL contact
177: first upper insulating film 179: second CSL contact
180: first wiring 185: wiring contact
190: second wiring 183: second upper insulating film
195: Third upper insulating film

Claims (10)

Channels extending in a first direction perpendicular to an upper surface of the substrate;
Gate lines extending around the outer walls of the channels and spaced apart from each other along the first direction;
First isolation insulating film patterns penetrating the gate lines along the first direction; And
And a second isolation insulating film pattern formed between the first isolation insulating film patterns facing each other and penetrating a part of the gate lines. The method of claim 1, wherein the first isolation insulating film patterns are spaced apart from each other along a second direction parallel to an upper surface of the substrate,
And the cell block includes the plurality of the channels and the gate lines partially separated by the first isolation insulating film patterns. 3. The semiconductor device according to claim 2, further comprising: a connection region in which the gate lines of adjacent cell blocks are connected to each other between the first isolation insulating film patterns which are parallel to an upper surface of the substrate and face in a third direction perpendicular to the second direction, Is formed. The vertical memory device according to claim 3, wherein the second isolation insulating film pattern is disposed in the connection region. 3. The method of claim 2, wherein the gate lines include a ground selection line (GSL), a word line, and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate along the first direction,
And the second isolation insulating film pattern penetrates the string selection line. 6. The semiconductor memory device according to claim 5, wherein the string selection lines of the cell blocks are separated from each other by the second isolation insulating film pattern,
Wherein the word lines and the ground selection lines of the cell blocks extend in connection with each other. 3. The vertical memory device according to claim 2, further comprising a third isolation insulating film pattern completely separating the gate lines of the adjacent part of the cell blocks. The vertical memory device of claim 1, further comprising dummy channels passing through the second isolation dielectric film pattern. The vertical memory device according to claim 1, further comprising an impurity region formed on the substrate below the first isolation insulating film pattern. 10. The method of claim 9, wherein the impurity region functions as a common source line (CSL)
And a CSL connection structure connecting the impurity regions separated from each other to each other,

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