KR20150116308A - Semiconductor package and method for packaging semicomductor device - Google Patents

Semiconductor package and method for packaging semicomductor device Download PDF

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Publication number
KR20150116308A
KR20150116308A KR1020140041407A KR20140041407A KR20150116308A KR 20150116308 A KR20150116308 A KR 20150116308A KR 1020140041407 A KR1020140041407 A KR 1020140041407A KR 20140041407 A KR20140041407 A KR 20140041407A KR 20150116308 A KR20150116308 A KR 20150116308A
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South Korea
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die
passivation layer
die pad
ubm
semiconductor
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KR1020140041407A
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Korean (ko)
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KR101622455B1 (en
Inventor
유지연
김병진
심재범
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020140041407A priority Critical patent/KR101622455B1/en
Publication of KR20150116308A publication Critical patent/KR20150116308A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

The present invention relates to a semiconductor package and a method of packaging semiconductor devices, and more particularly, to a wafer level chip scale package (WLCSP) and a packaging method thereof.
For example, a semiconductor die having a plurality of die pads formed on one surface thereof; A passivation layer formed on one surface of the semiconductor die and having openings for exposing at least a part of the die pad; A plurality of UBMs respectively contacting the at least a portion of the die pad through the opening and being formed to have a certain thickness in a direction perpendicular to the die pad from at least a portion of the die pad and exposed to the outside of the passivation layer; And a plurality of solder bumps respectively connected to the UBM.

Description

[0001] DESCRIPTION [0002] SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING SEMICOMDUCTOR DEVICE [

The present invention relates to a semiconductor package and a method of packaging semiconductor devices, and more particularly, to a wafer level chip scale package (WLCSP) and a packaging method thereof.

BACKGROUND ART [0002] In recent years, portable electronic devices such as portable telephones have been rapidly developed, and fusion and compounding among electronic devices are rapidly progressing. For example, various functions such as camera function, MP3 play function, and DMB function are complex and high-performance in a mobile phone.

However, portable electronic devices are small and light and should be easy to carry. In other words, as the functions and the complexity are advanced, the size of the portable electronic device is inevitably enlarged. In order to solve this problem, miniaturization of parts can contribute the most.

A chip scale package (CSP) refers to a package whose size is within 1.2 times the size of the semiconductor chip.

A typical CSP manufacturing method involves singulation of a wafer, which has been completed through a semiconductor process, into individual semiconductor chips, and packages the wafer. A wafer level chip scale package (hereinafter referred to as WLCSP) is emerging in accordance with miniaturization of components and mass production trends.

The WLCSP is completed as a package by performing the packaging process in the wafer state to redistribute the circuit or perform flip-chip bumping to complete the package structure and then individualize the package structure. Therefore, the WLCSP is almost the same size as the semiconductor chip, and all the packaging processes are performed at the wafer level, which enables mass production, thereby reducing the manufacturing cost.

In general, the WLCSP includes a semiconductor die having a die pad, a re-wiring layer electrically connected to the die pad, an under bump metal (UBM) electrically connected to the re-wiring layer and electrically connected to the solder bump, And the solder bump to be bonded. The re-wiring layer and the UBM may be formed on the basis of openings of the passivation layer for protecting the WLCSP.

In such a WLCSP manufacturing method, a four-step photomask process is basically required. For example, a first passivation layer is formed on the top surface of a semiconductor die having a die pad formed thereon, and the first passivation layer is patterned through a first photomask process to form a predetermined circuit pattern connected to the die pad. Thereafter, a re-wiring layer is formed on the circuit pattern by using a second photomask process. In addition, a second passivation layer is formed on the first passivation layer and the re-wiring layer, and then the second passivation layer is patterned using a third photomask process. Thereafter, the UBM is formed through a fourth photomask process.

In order to manufacture the WLCSP, the photomask process must be performed in several steps, which is not only burdensome in terms of manufacturing cost, but also may require a considerable manufacturing time.

The present invention provides a semiconductor package and a method of packaging the semiconductor device, the manufacturing cost and the production time being saved by minimizing the photomask processing step.

According to an aspect of the present invention, there is provided a semiconductor package comprising: a semiconductor die having a plurality of die pads formed on a surface thereof; A passivation layer formed on one surface of the semiconductor die and having openings for exposing at least a part of the die pad; A plurality of UBMs respectively contacting the at least a portion of the die pad through the opening and being formed to have a certain thickness in a direction perpendicular to the die pad from at least a portion of the die pad and exposed to the outside of the passivation layer; And a plurality of solder bumps respectively connected to the UBM.

A die passivation layer may further be formed on one surface of the semiconductor die except for the die pad.

Further, the die passivation layer may be formed in the same layer as the die pad.

The thickness of the UBM may be greater than the thickness of the passivation layer.

Also, the thickness of the UBM may be 9 to 13 탆.

Further, at least a part of the die pad and the opening may overlap each other.

The upper portion of the UBM exposed to the outside of the passivation layer may be wider than the opening.

A method of packaging a semiconductor device according to another embodiment of the present invention includes: preparing a semiconductor die having a plurality of die pads formed therein; Forming a passivation layer on the semiconductor die, each passivation layer having an opening exposing at least a portion of the die pad, respectively; Forming a plurality of UBMs each having a certain thickness in a direction perpendicular to the die pad from at least a portion of the die pad, each of the UBMs contacting at least a portion of the die pad through the opening; And forming a plurality of solder bumps respectively bonded to the UBM.

The semiconductor die may further include a die passivation layer on one side of the semiconductor die except for the die pad.

Further, the die passivation layer may be formed on the same layer as the die pad.

Further, the opening may be formed so that at least a part of the opening overlaps with the die pad.

In addition, the thickness of the UBM may be thicker than that of the passivation layer.

The UBM may have a thickness of 9 to 13 탆.

In addition, an upper portion of the UBM exposed to the outside of the passivation may be formed wider than the opening.

The opening of the passivation layer and the UBM may be formed using a photomask process.

According to the present invention, it is possible to provide a semiconductor package that minimizes the photomask processing steps and saves manufacturing cost and production time, and a method of packaging the semiconductor device.

1 is a plan view showing a configuration of a semiconductor package according to an embodiment of the present invention.
2 is a cross-sectional view taken along line I-I 'of FIG.
3 is a cross-sectional view taken along line II-II 'of FIG.
4 is a flowchart illustrating a method of packaging a semiconductor device according to another embodiment of the present invention.
5A to 5D are views showing a packaging procedure of a semiconductor device according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Hereinafter, the structure of a semiconductor package according to an embodiment of the present invention will be described.

1 is a plan view showing a configuration of a semiconductor package according to an embodiment of the present invention. 2 is a cross-sectional view taken along line I-I 'of FIG. 3 is a cross-sectional view taken along line II-II 'of FIG.

1 to 3, a semiconductor package 100 according to an exemplary embodiment of the present invention includes a semiconductor die 110, a passivation layer 120, a plurality of UBMs 130 and 130 ' And a plurality of solder bumps 140, 140 '.

The semiconductor die 110 is mainly made of a silicon material, and a plurality of semiconductor elements are formed in the semiconductor die 110. A die pad 111 and a die passivation layer 113 are formed on the semiconductor die 110.

The die pad 111 is a portion for receiving and outputting electrical signals to and from the semiconductor die 110, and is provided on the upper surface of the semiconductor die 110. The die passivation layer 113 is formed on the upper surface of the semiconductor die 110 and has a plurality of die passivation layer openings 113a for exposing the die pad 111, respectively. The die passivation layer 113 protects the semiconductor die 110 from external impact and insulates the upper surface of the semiconductor die 110 except for the die pad 111. [ The die passivation layer 113 is formed on the upper surface of the semiconductor die 110 except for the die pad 111 and may be formed on the same layer as the die pad 111. [

The passivation layer 120 is formed on the semiconductor die 110 and has a plurality of passivation layer openings 120a that expose at least a portion of the die pad 111, respectively. The positions where the passivation layer openings 120a are formed correspond to the positions of the solder bumps 140. The regions where the die pads 111 are exposed from the passivation layer 120 are formed in the passivation layer openings 120a, The die passivation layer opening 113a may be formed in a region where the die passivation layer opening 113a partially or entirely overlaps. For example, as shown in Fig. 2, the passivation opening 120a and the die passivation opening 113a may have a partially overlapping region C1, and the passivation opening 120a, as shown in Fig. 3, And the die passivation opening 113a 'are entirely overlapped with each other.

The passivation layer 120 allows the semiconductor die 110 to be electrically insulated in a region other than the die pad 111 and the passivation opening 120a is a space in which the UBMs 130 and 130 ' So that the UBMs 130 and 130 'and the die pads 111 and 111' are in electrical contact with each other through the overlapping regions C1 and C2.

The material of the passivation layer 120 may be selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BTO), phenolic resin, epoxy, (SiO 2), a nitride (Si 3 N 4), and the like. However, the material of the passivation layer 120 is not limited in one embodiment of the present invention.

The UBMs 130 and 130'are formed in electrical contact with at least portions of the die pads 111 and 111 'in the overlapping regions C1 and C2 via the passivation opening 120a, respectively. The UBMs 130 and 130 'are formed to have a predetermined thickness D1 and D2 from the die pads 111 and 111' in a direction perpendicular to the die pads 111 and 111 ' 131, 131 'may be formed to be exposed to the upper portion of the passivation layer 120.

Here, the thickness of the UBM 130 and 130 'may be about 9 to 13 μm. If the thickness of the UBM 130 or 130 'is less than 9 袖 m, it may be difficult to connect the UBM 130 and the solder bump 140 or 140' 130, and 130 'may excessively protrude above the passivation layer 120 to increase the overall thickness of the semiconductor package 100. Therefore, the UBM 130 and 130 'are formed to be slightly thicker than the passivation layers 120 and 120' so that the solder bumps 140 and 140 'do not contact the passivation layers 120 and 120' It is appropriate. The upper portions 131 and 131 'of the UBMs 130 and 130' are formed to be wider than the passivation layer openings 120a so that they can correspond to various forming positions of the solder bumps 140 and 140 ' The reliability of bonding to the bumps 140 and 140 'can be enhanced.

The materials of the UBMs 130 and 130 'may be selected from the group consisting of Cr / Cr-Cu / Cu / Ti / W / Cu / Al / / Ni / Cu) or an equivalent thereof. However, the material of the UBM 130 or 130 'is not limited in one embodiment of the present invention. However, it is preferable that the UBMs 130 and 130 'are formed of copper to have a sufficient thickness.

The solder bumps 140 and 140 'are formed of a plurality of solder bumps 140 and 140', respectively, to be connected to the UBMs 130 and 130 '. The solder bumps 140 and 140 'form a path through which the semiconductor die 110 can be electrically connected to an external circuit. The solder bumps 140 and 140 'may be formed using an alloy such as tin (Sn), lead (Pb), silver (Ag), or the like. In an embodiment of the present invention, , 140 ').

Conventionally, a number of photomask processing steps have been required to form openings in the first passivation layer, rewiring layer, openings in the second passivation layer and UBM on the semiconductor die.

However, according to one embodiment of the present invention, the passivation layer openings and the die pads (or die passivation openings) are configured to partially (or wholly) overlap, and the UBMs in the overlapped regions are formed thick The number of passivation layers can be reduced by omitting the conventional rewiring layer. By omitting the redistribution layer and reducing the number of passivation layers, it is possible to reduce the number of steps of the photomask process, thereby reducing the manufacturing cost of the semiconductor package and reducing the production time.

Hereinafter, a method of packaging a semiconductor device according to another embodiment of the present invention will be described.

4 is a flowchart illustrating a method of packaging a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 4, a semiconductor device packaging method (S400) according to another embodiment of the present invention includes a semiconductor die preparing step S410, a passivation layer forming step S420, a UBM forming step S430, (S440).

5A to 55 are views showing a manufacturing procedure of a semiconductor package according to another embodiment of the present invention. A method of packaging a semiconductor device (S400) according to another embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5D.

5A, the semiconductor die preparation step S410 includes a semiconductor die 510 having a die pad 511 and a die passivation 513 formed on one surface thereof.

The semiconductor die 510 is mostly made of a silicon material, and a plurality of semiconductor elements are formed in the semiconductor die 510. The die pad 511 is a portion for receiving and outputting electrical signals to and from the semiconductor die 510, and is provided on the upper surface of the semiconductor die 510. The die passivation layer 513 is formed on the upper surface of the semiconductor die 510 and has a plurality of die passivation layer openings 513a for exposing the die pad 511, respectively. This die passivation layer 513 protects the semiconductor die 510 from external impact and insulates the upper surface of the semiconductor die 510 except for the die pad 511. [ The die passivation layer 513 is formed on the upper surface of the semiconductor die 510 except for the die pad 511 and may be formed on the same layer as the die pad 511. [

In the passivation layer forming step S420, a passivation material layer is formed on the semiconductor die 510 so that the die pad 511 and the die passivation layer 513 are covered with the passivation layer, Passivation layer openings 520a and 520a 'are formed to expose at least a portion of the die pad 511 to form a passivation layer 520, as shown in FIGS. 5A and 5B.

The location where the passivation layer openings 520a and 520a 'are formed corresponds to the location of the subsequent solder bumps 540 and the area from which the die pad 511 is exposed from the passivation layer 520, May be formed in a region where the opening 520a and the die passivation layer opening 513a partially or wholly overlap. For example, as shown in the right portion of FIG. 5B, the passivation opening 520a and the die passivation opening 513a may have an area C1 in which they partially overlap, as shown in the left part of FIG. 5B Similarly, the passivation opening 520a 'and the die passivation opening 513a' may have a region C2 in which the passivation opening 520a 'and the die passivation opening 513a' are entirely overlapped.

The passivation layer 520 allows the semiconductor die 510 to be electrically insulated in areas other than the die pad 511 and the passivation openings 520a and 520a ' So that the UBM 530 and the die pad 511 are in electrical contact with each other through the overlap regions C1 and C2.

The material of the passivation layer 520 may be selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BTO), phenolic resin, epoxy, silicon oxide, silicon oxide (SiO2), nitride film (Si3N4), and the like, but the material of the passivation layer 520 is not limited in other embodiments of the present invention.

In the UBM formation step S430, as shown in FIG. 5C, the UBM is formed in contact with the die pad 511 through the passivation layer opening 520a, and the UBM is formed from the die pad 511 to the die pad 511 UBMs 530 and 530 'are formed to have a predetermined thickness in the vertical direction. The UBMs 530 and 530 'may be formed through a conventional photomask process.

The UBMs 530 and 530 'are formed in electrical contact with at least a portion of the die pads 511 and 511' in the overlapping regions C1 and C2 via the passivation opening 520a, respectively. The UBMs 530 and 530 'are formed to have a predetermined thickness D in a direction perpendicular to the die pads 511 and 511' from the die pads 511 and 511 ' 531 'may be formed to be exposed to the upper portion of the passivation layer 520.

Here, the thickness of the UBM 530 and 530 'may be approximately 9 to 13 μm. If the thickness of the UBM 530 and 530 'is less than 9 μm, it may be difficult to bond the UBM 530 and 530' to the solder bumps 540 and 540 '. If the UBM 530 and 530' 530 and 530 'may excessively protrude above the passivation layer 520 to increase the overall thickness of the semiconductor package. Accordingly, the UBMs 530 and 530 'may be formed to be slightly thicker than the passivation layers 520 and 520' so that the solder bumps 540 and 540 'do not contact the passivation layers 520 and 520' It is appropriate. The upper portions 531 and 531 'of the UBMs 530 and 530' are formed to be wider than the passivation layer openings 520a to correspond to various positions of the solder bumps 540 and 540 ' The bonding reliability to the bumps 540 and 540 'can be increased.

The UBMs 530 and 530 'may be made of a material selected from the group consisting of Cr / Cr-Cu / Cu / Ti / / Ni / Cu) or an equivalent thereof. However, the material of the UBM 530 and 530 'is not limited in the embodiment of the present invention. However, it is preferable that the UBMs 530 and 530 'are formed of copper to have a sufficient thickness.

In the solder bump forming step S440, as shown in FIG. 5D, a plurality of solder bumps 540 and 540 'may be formed to be bonded to the UBMs 530 and 530', respectively. The solder bumps 540 and 540 'are formed by placing solder material on top of the UBM 530 and 530' respectively and fusing the solder material to the UBM 530 and 530 'through a reflow process .

The solder bumps 540 and 540 'may be formed using an alloy such as tin (Sn), lead (Pb), silver (Ag), or the like. In an embodiment of the present invention, the solder bumps 540 and 540' , 540 'are not limited.

Conventionally, a number of photomask processing steps have been required to form openings in the first passivation layer, rewiring layer, openings in the second passivation layer and UBM on the semiconductor die.

However, according to another embodiment of the present invention, the passivation layer openings and the die pads (or die passivation openings) are configured to partially (or wholly) overlap, and the UBMs in the overlapped regions are formed thick The number of passivation layers can be reduced by omitting the conventional rewiring layer. By omitting the redistribution layer and reducing the number of passivation layers, it is possible to reduce the number of steps of the photomask process, thereby reducing the manufacturing cost of the semiconductor package and reducing the production time.

Although the present invention has been described in connection with certain exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made therein without departing from the spirit and scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention.

100: semiconductor package
110: semiconductor die
111, 111 ': die pad
113: die passivation layer
113a, 113a ': die passivation layer opening
120: passivation layer
120a: Passivation layer opening
130, 130 ': UBM
131, 131 ': upper part of UBM
140: solder bump
C1, C2: overlapping area
D1, D2: Thickness of UBM

Claims (15)

A semiconductor die having a plurality of die pads formed on one surface thereof;
A passivation layer formed on one surface of the semiconductor die and having openings for exposing at least a part of the die pad;
A plurality of UBMs respectively contacting the at least a portion of the die pad through the opening and being formed to have a certain thickness in a direction perpendicular to the die pad from at least a portion of the die pad and exposed to the outside of the passivation layer; And
And a plurality of solder bumps respectively connected to the UBM. The method according to claim 1,
Wherein a die passivation layer is further formed on one surface of the semiconductor die except for the die pad. 3. The method of claim 2,
Wherein the die passivation layer is formed in the same layer as the die pad. The method according to claim 1,
Wherein a thickness of the UBM is greater than a thickness of the passivation layer. The method according to claim 1,
Wherein the UBM has a thickness of 9 to 13 占 퐉. The method according to claim 1,
Wherein at least a portion of the die pad and the opening overlap each other. The method according to claim 1,
Wherein an upper portion of the UBM exposed to the outside of the passivation layer is formed wider than the opening. Preparing a semiconductor die having a plurality of die pads formed therein;
Forming a passivation layer on the semiconductor die, each passivation layer having an opening exposing at least a portion of the die pad, respectively;
Forming a plurality of UBMs each having a certain thickness in a direction perpendicular to the die pad from at least a portion of the die pad, each of the UBMs contacting at least a portion of the die pad through the opening; And
And forming a plurality of solder bumps respectively bonded to the UBMs. 9. The method of claim 8,
Wherein the semiconductor die further comprises a die passivation layer formed on one side of the semiconductor die except for the die pad. 10. The method of claim 9,
Wherein the die passivation layer is formed on the same layer as the die pad. 9. The method of claim 8,
Wherein the opening is formed to overlap at least a part of the die pad. 9. The method of claim 8,
Wherein the thickness of the UBM is greater than the thickness of the passivation layer. 9. The method of claim 8,
Wherein the UBM has a thickness of 9 to 13 mu m. 9. The method of claim 8,
Wherein an upper portion of the UBM exposed to the outside of the passivation is formed wider than the opening. 9. The method of claim 8,
Wherein the opening of the passivation layer and the UBM are formed using a photomask process.
KR1020140041407A 2014-04-07 2014-04-07 Semiconductor package and method for packaging semicomductor device KR101622455B1 (en)

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Cited By (2)

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US10734342B2 (en) 2017-12-19 2020-08-04 Samsung Electronics Co., Ltd. Semiconductor package for reducing stress to redistribution via
KR20240001888A (en) 2022-06-28 2024-01-04 주식회사 실리콘마이터스 Wafer level chip scale package with rhombus shape

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Publication number Priority date Publication date Assignee Title
US20180076151A1 (en) 2016-09-12 2018-03-15 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor package

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Publication number Priority date Publication date Assignee Title
US7005752B2 (en) * 2003-10-20 2006-02-28 Texas Instruments Incorporated Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10734342B2 (en) 2017-12-19 2020-08-04 Samsung Electronics Co., Ltd. Semiconductor package for reducing stress to redistribution via
US11742308B2 (en) 2017-12-19 2023-08-29 Samsung Electronics Co., Ltd. Semiconductor package for reducing stress to redistribution via
KR20240001888A (en) 2022-06-28 2024-01-04 주식회사 실리콘마이터스 Wafer level chip scale package with rhombus shape

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