KR20150115634A - A method and apparutus for predicting a central processing unit idle pattern for power saving in a modem system on chip - Google Patents

Abstract

A method and a system for providing power management in a system employing a central processing unit (CPU) and an operating system are provided. The method includes the following steps: monitoring idle times of the CPU; predicting an idle pattern based on the monitored idle times; and determining a selective sleep of a peripheral device based on the predicted CPU idle pattern.

Description

Field of the Invention [0001] The present invention relates to a method and apparatus for predicting a central processing unit idle pattern for power saving in a modem system on chip,

The present invention relates to a method and apparatus for predicting a central processing unit (CPU) idle pattern for power saving in a modem on-chip (SoC).

System on Chip (SoC) is an integrated circuit (IC) that is commonly used in embedded devices that integrate all the components of a computer or other electronic system into a single chip. In electronic and embedded devices, reducing power consumption can be a difficult task. The reason for this is that the microcontroller / microprocessor of the embedded device must remain in the boundary state to execute the processes as soon as possible and to provide the output to the user. Accordingly, various improvements have been proposed to reduce the power consumption of the devices without affecting the performance of the embedded devices.

This disclosure is directed to addressing the problems and drawbacks discussed above and at least providing the advantages described below.

In an embodiment of the disclosure, there is provided a method of providing power management in a system using a central processing unit (CPU) and an operating system, the method comprising: monitoring idle times of the CPU; Predicting an idle pattern of the CPU based on the monitored idle times; And determining an optional sleep of the peripheral based on the predicted CPU idle pattern.

In another embodiment of the present disclosure, there is provided an apparatus for performing power management in a system using a central processing unit (CPU) and an operating system, the apparatus comprising: a monitoring unit for monitoring idle times of the CPU; A predictor for predicting a CPU idle pattern based on the predicted CPU idle pattern, and a controller for determining an optional sleep of the peripheral based on the predicted CPU idle pattern.

These and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
1 is a schematic diagram illustrating a CPU idle implementation in a sleep mode in an SoC of an existing system,
2 is a schematic diagram illustrating a "selective sleep" mode of peripherals and subsystems of an SoC according to the existing system;
3 is a timing diagram illustrating variation of an existing CPU idle period that varies due to hardware transient response mode,
FIG. 4 is a timing chart illustrating a variation of an existing CPU idle period that varies due to PDCCH reception,
5 is a timing diagram illustrating a CPU idle time that has been previously distributed due to a short DRX in long DRX cycles,
6 is a schematic diagram illustrating a model of a device learning process for predicting CPU idle time, in accordance with one embodiment of the present disclosure;
7 is a schematic diagram illustrating a time-based decision method based on trend prediction, in accordance with one embodiment of the present disclosure;
8 is a schematic diagram illustrating an event fingerprinting method for time-based determination based on trend prediction, in accordance with one embodiment of the present disclosure;

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the above-described embodiments. In the following description, the same or similar reference numerals are used to denote the same or similar elements in the accompanying drawings. Detailed descriptions of known functions and configurations may be omitted so as to avoid obscuring the subject matter of this disclosure.

In an embedded microprocessor / microcontroller-based device, one way to reduce power consumption is to turn off gating clocks to external components of the system and peripheral units based on system operation. These power saving procedures can be initiated and implemented when the CPU of the device is in an idle state.

1 is a schematic diagram illustrating the implementation of a CPU idle state in a sleep mode in an SoC of an existing system.

Referring to method 100b of FIG. 1, the sleep mode is used to trigger the CPU idle state when the conditions are satisfied. The embodiment of FIG. 1 is based on interoperations between peripheral units and the CPU of the device, or procedures performed in peripherals caused by CPU actions such as direct memory access (DMA) or device driver calls. In accordance with an embodiment of the present invention, when the CPU enters the idle state (step 101), it is checked whether all of the peripheral units and subsystems are in a busy state (step 105). Such peripheral units and subsystems include, but are not limited to, a Universal Serial Bus (USB) 121, a Universal Asynchronous Receiver / Transmitter (UART) 123, a watchdog 125, an Inter- Integrated Circuit (I2C) 127, a Serial Peripheral Interface 129, a coprocessor 131, a Universal Subscriber Identifier Module (USIM) 133, and the like. If the CPU determines that either peripheral units or subsystems are busy (step 105), the CPU will enter a Wait For Interrupt (WFI) (step 109). When the CPU enters the WFI state, the CPU will be in the idle state and no process will be in the running state. When the CPU receives an arbitrary process to be executed (step 111), the interrupt service routine is started (step 113).

If the CPU determines in step 105 that none of the peripheral units and subsystems are busy, the CPU enters step 107. The CPU stores the current states of the peripheral units and subsystems, Thereby shutting down the power of the systems (step 107a). When the power of the peripheral units and subsystems is interrupted, the CPU enters the WFI state (step 107b), in which the CPU will be in the idle state and no process will be running. When the CPU receives an arbitrary process to be executed (step 111), an interrupt signal will be received and the CPU will be energized and the conditions of both the peripherals and subsystems will be restored for execution (step 107c). Once the peripherals and subsystems are restored and powered on, the CPU initiates an interrupt service routine to process the process execution (step 113). A schematic graph 100a of FIG. 1 illustrates the CPU utilization of busy state 151 and idle state 153, in accordance with the power saving routine described above.

Figure 2 includes a schematic 200a illustrating a "selective sleep " mode of peripherals and subsystems in a SoC of an existing system and a flowchart 200b of a corresponding method. The steps of method 200b of FIG. 2 are similar to the corresponding steps of method 100b of FIG. 1, except for the addition of steps 208, 208a, 208b, and 211, which will be described in detail below. Further descriptions of the steps of the method 200b corresponding to similar steps of the method 100b of FIG. 1 are omitted for clarity and brevity. The "selective sleep " mode of peripherals and subsystems is generated during a CPU idle state in which a list of certain conditions is satisfied (step 208). The optional sleep mode of peripherals and subsystems is similar to the sleep mode as described in FIG. 1, but instead of sending both peripherals and subsystems in sleep mode during the idle period of the CPU, the CPU is not activated during the CPU idle period And detect and select only those peripherals and subsystems (step 208a). Then, the CPU transitions only selected peripheral devices and subsystems to the sleep mode (step 208b). After entering the selective sleep mode (step 208) and entering the WFI state (step 209), power is applied / restored to selected peripherals and subsystems (step 212) when an interrupt occurs (step 211) . After the power injection / recovery is performed (step 212), an interrupt service routine is performed (step 213).

The sleep mode as described with reference to FIG. 1 and the selective sleep mode as described with reference to FIG. 2 share the same drawbacks. Powering off external components or gating clocks to peripherals and recovering them in a short time when the CPU idle state is not maintained for a long time (ie, short CPU idle time) results in more power consumption than power saving do. This increase is caused by an additional current surge during the OFF-to-ON transition state of the CPU before the CPU stabilizes, thereby consuming more power than usual. Even though the power consumed by peripherals and subsystems in the selective sleep mode is less than the consumption in the general sleep mode, the power consumption of the selective sleep mode is still an issue, and there is a need to improve the performance of such systems.

The CPU idle period of the system may have a specified pattern for a particular scenario. For example, for a given scenario, the CPU idle period may follow a particular pattern constantly after the execution of a particular interrupt or task. The length of the CPU idle period can vary each time a CPU idle pattern occurs, but its CPU idle period can be predicted to some extent. However, static estimation of the CPU idle period based on protocol, design, or architecture may not be feasible. The CPU idle period should be predicted during runtime since the CPU idle period may vary based on the actual implementation. For example, when a modem is in a Long Term Evolution (DRX) (Discontinuous Reception (LTE)) specification of the 3rd Generation Partnership Project (3GPP) specification, which is a process of turning off a radio frequency (RF) ) Can be considered. The DRX cycle is configured to allow the modem to periodically enter the sleep state and awaken to read the control channel information of the PDCCH (Physical Downlink Control Channel).

Although the DRX cycle is periodic, according to the 3GPP specification, the CPU ON time and the idle time accordingly can be varied according to the following conditions.

A: Due to hardware transient response and processing offload:

3 is a timing diagram illustrating variation of an existing CPU idle period due to a hardware transient response mode.

Referring to FIG. 3, a graph 300 represents a DRX cycle pattern according to the 3GPP specification and shows durations 301 and 303, respectively, in which the device will be in an ON state and a DRX state. During the DRX state, the device will perform airwave communication and the CPU will be in the idle state. However, in an actual implementation, the durations 305 and 307 of the device ON state and the CPU idle state, respectively, are variable because, during the device ON state, the system takes some time to awaken and recover the peripherals when considering hardware stabilization Because the system requires some time to turn off the peripherals before entering the CPU idle period. The additional time it takes to awaken and restore the peripherals is referred to as "early wake up" time 309. In Figure 3, the additional time taken by the system to awaken (309) the peripherals and turn off (311) the peripherals is indicated by circles drawn with dashed lines on both sides of the device on period (305). The additional time taken by the system during the awakening period 309 and the CPU idle period 309 may vary.

B: during PDCCH reception:

4 is a timing diagram 400 illustrating the variation of existing CPU idle periods that vary due to PDCCH reception.

Referring to FIG. 4, as shown in the graph 400, during the CPU ON state, a downlink allocation is received on the PDCCH at a point of view 401. Downlink allocation sets an NDI (New Data Indicator) for finding incoming data , So that the DRX inactivity timer is started during the period 403. The NDI may consume a portion of the CPU idle duration and thereby reduce the CPU idle duration 405 for the DRX cycle 407. [

C: Short DRX cycles are configured:

Figure 5 is a timing diagram 500 illustrating the CPU Idle time previously distributed due to a short DRX in long DRX cycles.

5, the configuration of short DRX cycles is an optional feature, during which DRX cycles 505 (including cycles 505a and 505b) are long DRX cycles 507, Off periods 503 (including cycles 503a, 503b, and 503c). The long DRX cycle OFF periods 503 identify the actual CPU idle periods. However, since several short DRX cycles 505 are implemented during a long DRX cycle 507, the short DRX cycles 505 can reduce the CPU idle period, thereby affecting the CPU idle period of the system .

Therefore, there is a need for an effective method and system for device learning prediction of CPU idle patterns for power saving in a modem SoC.

Thus, various embodiments herein disclose a method and system for providing power management in a computing system by predicting a CPU idle pattern for power savings in a modem SoC.

The specification may refer to "one", "one", or "some" embodiments (s) in various places. This does not necessarily imply that such reference is made to the embodiment (s) or that the corresponding features apply only to one embodiment. The individual characteristics of the different embodiments may be combined to provide other embodiments.

As used herein, the singular forms are intended to include the plural forms unless the context clearly dictates otherwise. The terms " comprising, "" comprising," " including, "and / or" comprising " But does not preclude the presence or addition of one or more other features, integers, steps, operations, components, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations and arrangements of one or more of the listed listed related.

Unless otherwise defined, all terms (technical and / or scientific terms) used herein have the same meaning as is typically understood by those skilled in the art to which this disclosure belongs. Terms such as those defined in the generic use dictionaries have meanings consistent with the corresponding meaning according to the context of the related art unless clearly defined in this specification.

For the purpose of achieving improved power savings in a modem SoC during a CPU idle period, the present disclosure describes the prediction of a CPU idle pattern and the application of selective sleep during a CPU idle period.

6 is a schematic diagram illustrating a model of a device learning process for predicting CPU idle time, in accordance with one embodiment of the present disclosure;

According to Figure 6, a model of a process according to one embodiment of the present disclosure includes the following three steps:

(a) Monitor CPU children during runtime to understand trending patterns of CPU idle time (step 602);

(b) Predicting and determining a trending pattern of CPU idle periods (step 604); And

(c) The predicted results are applied to the system (step 606) so that the selective sleep can be made at the corresponding time, thereby enhancing the power saving efficiency of the system.

At step 602, the CPU idle period is monitored during the runtime of the system to understand the trending patterns of CPU idle periods in which the execution of processes and entry of the CPU into the idle period are observed. Along with observing process execution, the duration of the CPU idle period after the execution of a particular type of process is also observed, which can be used to identify and imply that the CPU can enter the idle state for a certain period of time after the execution of that particular type of process have. For example, the CPU may take n1 seconds to execute process A, and may remain in the idle state for m1 seconds after execution of process A. Likewise, to execute process B, the CPU may take n2 seconds to execute and may be in the idle state for m2 seconds after execution of process B. [ After observing the execution pattern, the system estimates that every time another process similar to Process A or Process A is executed, the CPU idle period after the process execution will be m1 seconds.

According to one embodiment of the present disclosure, monitoring of the CPU idle period of the system may be performed in connection with any fixed period of time. According to another embodiment of the present disclosure, the monitoring of the CPU idle period of the system may be based on the frame sync rate.

At step 604, a trending pattern is identified, a CPU idle pattern is determined for a particular scenario that indicates how the CPU behaves during and after execution of a particular type of process. The trending pattern of the CPU can be recorded, and the decision to apply the selective sleep mode can be performed based on that record. The decision to apply the selective sleep mode may be taken in two different ways: (1) a prediction over time and (2) a prediction based on an event fingerprint, which will be described with reference to Figures 7 and 8, respectively will be.

In step 606, based on the obtained determination, the calculation results are applied to the system. The obtained results indicate which CPU idle time period is suitable for applying the selective sleep mode to the system in order to increase the power saving efficiency of the system. According to the obtained decision, the selective sleep mode is applied only during the specific CPU idle time period, and the selected peripheries and subsystems are sent to the sleep mode. Other peripherals and subsystems may be in active mode while the CPU is idle. Other peripherals and subsystems may be in a sleep mode based on CPU idle duration, observed trend pattern, running process, etc., but the embodiments of the present disclosure are not limited thereto. Since the selected peripherals and subsystems are in the sleep mode for the duration of the CPU idle, the power consumption of the system may be reduced and the power saving efficiency accordingly increased.

7 is a schematic diagram illustrating a time-based determination method based on trend prediction, in accordance with one embodiment of the present disclosure;

Referring to method 700b of FIG. 7, according to the method, each instance of the CPU idle period may be monitored during runtime of the system at step 702. [ The CPU idle period may be monitored for 'n' instances that identify scenarios of different CPU idle periods. At step 704, based on the different CPU idle period scenarios obtained during monitoring, the start of a CPU idle time longer than the defined threshold can be predicted. At step 706, future timestamps corresponding to future CPU idle times predicted to be longer than the threshold are displayed in the timer frame as selected locations where the power saving process can be initiated if the system is in the CPU idle state, (I.e., prediction) can be applied.

The graph 700a in Fig. 7 shows an example in which a part of the time frame is considered for the execution of the process by the CPU. During the first period 751, every 20 microseconds, a long CPU idle period is monitored to determine the maximum possible long idle period during which the CPU enters the idle period. In graph 700a, when a CPU is occupied by a process, the duration in which the CPU is busy is shaded as shown in the shaded portion 761, and the duration in which the CPU is idle is skewed to the left. If the CPU is busy for a short period of time, its busy time can also be observed and reported as shown in the hatched period 763.

In a manner similar to performing monitoring every 20 microseconds for long CPU idle states, long CPU idle can be monitored every 40 microseconds, or every 60 microseconds. Based on the observation results obtained every 20 microseconds, during the second period 753, a long CPU idle period can be predicted and an idle period for applying the selective sleep mode for the selected peripherals and subsystems Can be estimated. If a long CPU idle period is predicted, an optional sleep mode may be applied for a period of every 20 microseconds that comes in, such as periods 756a and 756b. Monitoring and prediction of long CPU idles can also be performed while applying the optional sleep mode for each upcoming 20 microsecond period, since that trend and CPU idle pattern can be detected by the user's input process execution request, Because it can be based on various situations such as emergency processes.

8 is a schematic diagram illustrating an event fingerprinting method for time-based determination based on trend prediction, in accordance with one embodiment of the present disclosure; Referring to method 800b of FIG. 8, each instance of the CPU idle period may be monitored at step 802 during the runtime of the system for various tasks. The CPU idle period may be monitored for " n " instances of different n jobs identifying scenarios of different CPU idle periods. At step 804, based on different CPU idle period scenarios obtained during monitoring, a prediction of an interrupt or task that is executed before the CPU idle pattern and is longer than the threshold is performed. In step 806, the estimated hypothesis can be applied by marking such predicted future interrupts or tasks in the prediction table, so that whenever the system enters the CPU idle state after such a task or interrupt occurs, The process can be started.

In FIG. 8, a graph 800a shows an example in which a part of a time frame is considered for execution of Job 1, Job 2, Job 3, ..., job n by the CPU. During the first period 851, a long CPU idle period, such as period 855, is monitored to determine the maximum usable long idle period for the CPU to enter the idle period for tasks 1, 2, 3, ..., n . Based on the monitoring, a prediction is made of which interrupts or tasks should be executed before the CPU idle pattern is executed, and interrupts or tasks to be executed that are longer than the threshold are observed.

Such interrupts or tasks may be displayed in the prediction table. During the second period 853, the estimated and observed pattern can be applied to tasks after a predetermined interval so that whenever a system enters the CPU idle state after a displayed job or interrupt, a power saving optional sleep mode can be initiated have. The displayed interrupt or task may be a single event or event fingerprint where the sequential execution of certain events resulted in a longer CPU idle state. Monitoring and prediction of long CPU idles may also be performed while applying the optional sleep mode for interrupts or tasks displayed during the CPU idle state because the trend and the CPU idle pattern may be requested by the user's input process execution, Because it can vary based on a number of situations, such as some other emergency process to run.

According to the present disclosure, prediction of the CPU idle state may fail for certain scenarios in which the execution process changes abruptly over time and the frequency of repetitive execution patterns is reduced. Such scenarios may be intermittent and may exist for a limited time. Predictions during this phenomenon may be inaccurate and may result in selective sleep for short CPU idle states. As discussed above, implementing an optional sleep mode during a short CPU idle state can consume slightly more power than usual. The additional power consumption caused by such prediction failure can be overcome by updating the prediction table based on the current execution patterns.

The present disclosure utilizes a negative feedback mechanism for the prediction process and will automatically update the prediction table with any change in the system execution pattern that is adhered to by the monitoring operation, thereby correcting the hypothesis. Thus, the prediction table update is self-regulated and is recovered from any prediction failure.

Although certain examples have been used in the foregoing embodiments, it will be apparent that various modifications and changes may be made to such embodiments without departing from the broader spirit and scope of such embodiments. Also, the various devices, modules, etc. described herein may be implemented in hardware circuits, such as CMOS (complementary metal oxide semiconductor) based logic circuits, firmware, software, and / or any combination of software implemented on hardware, firmware, and / And can be operated and used. For example, various electrical structures and methods may be implemented using electrical circuits such as transistors, logic gates, and application specific integrated circuits (ASICs).

Although the present disclosure includes references to certain embodiments, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure, as defined by the following claims and equivalents thereof You can see that you can.

Claims (16)

A method for providing power management in a system using a central processing unit (CPU) and an operating system,
Monitoring idle times of the CPU;
Predicting an idle pattern of the CPU based on the monitored idle times; And
And determining an optional sleep of the peripheral based on the predicted idle pattern.
2. The method of claim 1, wherein the monitored idle times are idle times of a task longer than a predefined threshold value to trigger power saving.
The method of claim 1, wherein the monitoring comprises:
And monitoring the idle times based on at least one of a fixed duration and a frame sync rate.
The method of claim 3,
Estimating an idle time longer than the predefined threshold value for a selected time frame when the idle pattern is predicted based on the fixed period; And
And displaying, within the selected time frame, a timestamp corresponding to the idle time as a location where the computing system causes power savings when the CPU is in the idle mode.
The method of claim 3,
Identifying one of a task and an interrupt to be executed before the idle pattern when predicting the idle pattern based on the frame synchronization rate;
Determining whether the idle pattern corresponding to the execution of the identified ones of the tasks and interrupts is longer than the predefined threshold; And
And displaying said identified ones of said operations and interrupts in a prediction table to trigger power savings for a next idle state.
6. The method according to claim 5,
A single event, or an event fingerprint of selected events that resulted in an idle time of the CPU for which sequential execution of the selected events has been increased.
The method according to claim 6,
Wherein the prediction table is updated according to a change in the execution pattern of the single event or the selected fingerprint.
2. The method of claim 1, wherein determining the selective sleep mode comprises:
And turning off the non-operational peripheral of the monitored idle times.
1. An apparatus for performing power management in a system using a central processing unit (CPU) and an operating system,
A monitoring unit for monitoring idle times of the CPU,
A predictor for predicting an idle pattern of the CPU based on the monitored idle times;
And a controller for determining an optional sleep of the peripheral based on the predicted idle pattern.
10. The apparatus of claim 9, wherein the monitored CPU idle times are idle times of a task longer than a predefined threshold value to trigger power saving.
10. The apparatus according to claim 9,
A fixed predetermined period of time, and a frame synchronization rate.
12. The apparatus of claim 11,
Estimating an idle time longer than the predefined threshold value for a selected time frame when predicting the idle pattern based on the fixed period,
Wherein the computing system displays, within the selected time frame, a timestamp corresponding to the idle time as a location where the computing system causes power savings when the CPU is in the idle mode.
12. The method of claim 11, wherein, in predicting the idle pattern based on the frame synchronization rate,
Identifying one of an action and an interrupt to be executed before the idle pattern,
Determining whether the idle pattern corresponding to the execution of the identified ones of the tasks and interrupts is longer than the predefined threshold,
And to display said identified ones of said tasks and interrupts in a prediction table to trigger power savings for a next idle state.
14. The method of claim 13,
A single event, or an event fingerprint of selected events that resulted in an idle time of the CPU for which sequential execution of the selected events has been increased.
15. The apparatus of claim 14, wherein the prediction table is updated according to a change in an execution pattern of the single event or the selected fingerprint.
10. The apparatus according to claim 9,
And turns off peripheral devices that do not operate during the monitored CPU idle times.

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