KR20150111456A - Display apparatus and method of manufacturing the same - Google Patents

Abstract

A display apparatus includes a first substrate and a second substrate facing the first substrate. The first substrate includes a first base substrate, a wiring part, and a pad part connected to the wiring part. The second substrate includes a second base substrate and an encapsulation part. The encapsulation part is disposed on top of the pad part.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of manufacturing the same,

The present invention relates to a display device and a method of manufacturing the same.

BACKGROUND ART [0002] Recently, a liquid crystal display (LCD), an organic light emitting diode, an electro wetting display device, a plasma display panel (PDP), an electrophoretic display Display Device) are being developed.

Generally, the display apparatus includes a display panel including two substrates facing each other. The display panel includes an image display unit interposed between the two substrates. The planar region of the two substrates includes a display region and a non-display region. The image display unit for displaying an image is disposed in the display area. An encapsulating material is formed in the non-display area. The two substrates are bonded by the sealing material.

The display device includes a driving unit for driving the display panel, and the driving unit is provided on at least one side of the display panel and is electrically connected to the display panel.

It is an object of the present invention to provide a light-weighted display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a display device in which cost is reduced and weight is reduced.

A display apparatus according to an embodiment of the present invention includes a display panel and a driver for driving the display panel.

Wherein the display panel includes a first substrate including a display region in which pixels are formed and a non-display region except for the display region, a second substrate facing the first substrate, and a display disposed between the first substrate and the second substrate Layer.

The first substrate includes a first base substrate, a wiring portion provided on the first base substrate, and a pad portion connected to the wiring portion and connected to external wiring

The wiring section includes a gate line provided in the non-display area and a data line crossing the gate line, a thin film transistor driving the pixel, a pixel electrode connected to the thin film transistor, and a common voltage Line.

The common voltage line may be provided along at least a part of the edges of the display area in the non-display area when viewed in plan view.

The pad portion may include a gate pad portion connected to the gate line, a data pad portion connected to the data line, and a common voltage pad portion connected to the common voltage line.

The gate pad portion includes a gate pad and a gate pad electrode connected to the gate pad. The gate pad is connected corresponding to the gate line.

The data pad unit includes the data pad and a data pad electrode connected to the data pad. The data pads are connected corresponding to the data lines.

The common voltage pad portion includes the common voltage pad and a common voltage pad electrode connected to the common voltage pad. The common voltage pad is connected corresponding to the common voltage line.

The second substrate may include a second base substrate, a color filter, a black matrix, a common electrode, and an encapsulant provided along an edge of the second base substrate.

The sealing part serves to bond the first substrate and the second substrate together. The sealing portion may be made of a compound including a polymer resin. The sealing portion is located on the pad portion when the first substrate and the second substrate are bonded together.

The driving unit may apply a signal to each of the gate line and the data line. The driving unit may include a flexible printed circuit board and a printed circuit board.

The flexible printed circuit board may be attached on at least a portion of the pad portion on the pad portion to connect the pad portion and the external wiring. The printed circuit board may be provided on at least one side of the first substrate and may be electrically connected to the pad unit through the flexible printed circuit board.

According to an embodiment of the present invention, the sealing portion may be disposed to overlap with the pad portion and the flexible printed circuit board. The flexible printed circuit board may be disposed between the sealing portion and the pad portion.

In another embodiment of the present invention, the sealing portion may overlap with the common eyepiece portion. Here, the sealing portion includes a conductive material.

In an embodiment of the present invention, the size of the first substrate is larger than the size of the second substrate, but the present invention is not limited thereto. In another embodiment of the present invention, the size of the first substrate, Can be provided equally.

In one embodiment of the present invention, the second substrate includes, but is not limited to, the black matrix and the color filter formed on the second base substrate. In another embodiment of the present invention, The black matrix and the color filter may be formed and included in the first substrate.

In an embodiment of the present invention, the display layer may be a liquid crystal layer.

A method of manufacturing a display device according to an embodiment of the present invention includes the steps of forming a wiring portion on a first base substrate and a pad portion connected to the wiring portion, attaching a flexible printed circuit board on the pad portion, A method of manufacturing a flexible printed circuit board, comprising: forming a display layer on a first base substrate; forming an encapsulation on the second base substrate; bonding the first base substrate and the second base substrate together; And attaching the printed circuit board.

The sealing portion is formed along an edge of the second base substrate. The sealing portion may overlap the pad portion with the flexible printed circuit board interposed therebetween.

The display layer may be a liquid crystal layer. The liquid crystal layer may be formed by dropping liquid crystals on the first base substrate.

The display device according to an embodiment of the present invention can reduce the weight of the display device by reducing the width of the bezel. Thus, the manufacturing cost of the display device can be reduced.

1 is a block diagram of a display device according to an embodiment of the present invention.
2 is a perspective view of a display panel according to an embodiment of the present invention.
3 is an enlarged plan view of a pixel according to an embodiment of the present invention.
4 is a cross-sectional view along II 'and III-III' of FIG. 3;
5 is a cross-sectional view taken along II-II 'of FIG. 2 and III-III' of FIG. 3;
6 is a cross-sectional view of a display device according to another embodiment of FIG.
7 is a cross-sectional view of a display device according to another embodiment of the present invention.
8 is a cross-sectional view of a display device according to another embodiment of the present invention.
9A to 9D are perspective views illustrating a method of manufacturing a display device according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, where a section such as a layer, a film, an area, a plate, or the like is referred to as being "on" another section, it includes not only the case where it is "directly on" another part but also the case where there is another part in between. On the contrary, where a section such as a layer, a film, an area, a plate, etc. is referred to as being "under" another section, this includes not only the case where the section is "directly underneath"

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are shown enlarged from the actual for the sake of clarity of the present invention. The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by terms. Terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a display apparatus according to an embodiment of the present invention, and FIG. 2 is a perspective view of a display panel according to an embodiment of the present invention. FIG. 3 is an enlarged plan view of a pixel according to an embodiment of the present invention, and FIG. 4 is a sectional view taken along line I-I 'and III-III' of FIG. 5 is a cross-sectional view taken along II-II 'of FIG. 2 and III-III' of FIG. 3;

1 to 5, a display device according to an exemplary embodiment of the present invention includes a display panel PNL having a plurality of pixels PX and a driver electrically connected to the display panel PNL do.

The display panel PNL may be a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, an electrowetting display panel, , A MEMS display panel (microelectromechanical system display panel), or the like, and is not particularly limited.

Hereinafter, a liquid crystal display panel among the display panels will be described as an example in the embodiment of the present invention. In addition, since the plurality of pixels have the same structure, only one pixel will be described as an example for convenience of explanation. Here, the pixel has a rectangular shape elongated in one direction, but is not limited thereto. The shape of the pixel may be variously formed in a V-shape, a Z-shape, or the like when viewed in a plan view.

The display panel PNL includes a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1, and a second substrate SUB2 between the first substrate SUB1 and the second substrate SUB2. And a liquid crystal layer (LCL) interposed therebetween.

The first substrate SUB1 includes a first base substrate BS1, a wiring portion provided on the first base substrate BS1, and a pad portion connected to the wiring portion.

The first substrate SUB1 is divided into a pixel region in which a plurality of pixels PX are provided and a pad region provided in at least one side of the pixel region. The pixel region is divided into a display region DA corresponding to each pixel PX on a one-to-one basis and a non-display region NDA provided on at least one side of the display region DA and not displaying an image.

The first base substrate BS1 may be a transparent or opaque insulating substrate, such as a silicon substrate, a glass substrate, a plastic substrate, or the like.

The wiring portion may include a plurality of gate lines GL ₁ to GL _{n +1} provided in the non-display region NDA, a plurality of data lines DL ₁ to DL _{m +1} , a pixel PX, TFT, a pixel electrode PE, and a common voltage line CML.

The gate lines (GL _1, GL ~ _{n +1)} may be arranged in parallel with each other and extend in the first direction (D1) on the first base substrate (BS1).

A first insulating film (INS1) formed on the gate lines (GL _1, GL ~ _{n +1),} is provided. The first insulating layer INS1 may be formed of an insulating material, for example, silicon nitride or silicon oxide.

The data lines DL ₁ to DL _{m +1} are provided on the first insulating layer INS 1. The data lines DL ₁ to DL _{m +1} extend in a second direction D 2 intersecting the first direction D 1 and may be arranged in parallel with each other.

The pixel PX is connected to a corresponding one of the gate lines GL and the data lines DL ₁ to DL _{m +1} of the gate lines GL ₁ to GL _{n +1} Can be connected to provide images.

The thin film transistor TFT is connected to the gate line GL and the data line DL and includes a gate electrode GE, a semiconductor layer SM, a source electrode SE, and a drain electrode DE do.

The gate electrode GE may protrude from the gate line GL or may be provided in a part of the gate line GL. The gate line GL and the gate electrode GE may be formed of a metal. The gate electrode GE may be formed of nickel, chromium, molybdenum, aluminum, titanium, copper, tungsten, or an alloy containing them. The gate electrode GE may be formed of a single film or multiple films using the metal. For example, the gate electrode GE may be a triple film in which molybdenum, aluminum, and molybdenum are sequentially laminated, or a double film in which titanium and copper are sequentially laminated. Or a single film of an alloy of titanium and copper.

The first insulating layer INS1 is provided on the front surface of the first base substrate BS1 to cover the gate electrode GE.

The semiconductor layer SM may be formed on the first insulating layer INS1 and may be provided to overlap at least a portion of the gate line GL.

The source electrode SE may be branched from the data line DL and may be formed on the semiconductor layer SM to overlap with the semiconductor layer SM at least partially.

The drain electrode DE is provided to be spaced apart from the source electrode SE. The drain electrode DE may be formed on the semiconductor layer SM so as to overlap with the semiconductor layer SM at least partially. Here, the semiconductor layer SM forms a conductive channel between the source electrode SE and the drain electrode DE.

Each of the source electrode SE and the drain electrode DE may be formed of a conductive material such as a metal. Each of the source electrode SE and the drain electrode DE may be formed of a single metal, but may be formed of two or more kinds of metals, or an alloy of two or more kinds of metals. For example, the source electrode SE and the drain electrode DE may be formed of nickel, chromium, molybdenum, aluminum, titanium, copper, tungsten, or an alloy thereof. Each of the source electrode SE and the drain electrode DE may be formed as a single layer or a multilayer. For example, each of the source electrode SE and the drain electrode DE may be formed of a double layer made of titanium and copper.

The thin film transistor TFT switches the driving signal provided to the corresponding pixel electrode PE. A protective layer (PSV) for protecting the thin film transistor (TFT) is formed on the thin film transistor TFT.

The pixel electrode PE is connected to the drain electrode DE via the protective layer PSV. The protective layer PSV has a first contact hole CH1 exposing a part of the drain electrode DE and the pixel electrode PE is electrically connected to the drain electrode DE through the first contact hole CH1. ). The pixel electrode PE may be formed of a conductive material such as a metal. A second insulating layer INS2 for protecting the pixel electrode PE may be provided on the pixel electrode PE, but this may be omitted. The second insulating layer INS2 may be formed of an inorganic insulating material or an organic insulating material.

The common voltage line CML may be formed along at least a part of the edge of the pixel region in the non-display region NDA, and may be provided in a form surrounding the pixel region. The common voltage line CML may be formed of the same material as the gate line GL. The common voltage line CML serves to provide a common voltage to the common electrode CE, which will be described later.

The pad portion includes a gate pad portion GPP connected to the gate line GL, a data pad portion DPP connected to the data line DL, and a common voltage pad portion CMPP connected to the common voltage line CML. . ≪ / RTI >

The gate pad portion GPP, the data pad portion DPP, and the common voltage pad portion CMPP are provided in the pad region.

The gate pad portion GPP includes a gate pad GP and a gate pad electrode GPE connected to the gate pad GP. The gate pad GP is connected to the gate line GL on the first base substrate BS1. The gate pad electrode GPE is connected to the gate pad GP through a second contact hole CH2 formed in the first insulating layer INS1.

The data pad unit DPP includes a data pad DP and a data pad electrode DPE connected to the data pad DP. The data pad DP is connected to the data line DL on the first insulating layer INS1. The data pad electrode DPE may be provided in direct contact with the data pad DP.

The common voltage pad unit CMPP includes a common voltage pad CMP and a common voltage pad electrode CMPE connected to the common voltage pad CMP. The common voltage pad CMP is connected to the common voltage line CML on the first insulating layer INS1. The common voltage pad electrode CMPE may be provided in direct contact with the common voltage pad CMP.

A connection part CL made of a conductive material may be provided on the common voltage line CML and the common voltage pad electrode CMPE. The common voltage may be applied to the common electrode CE through the connection portion CL.

Although not shown, in another embodiment of the present invention, the data pad electrode or the common voltage pad electrode may not be provided. In another embodiment of the present invention, an additional insulating layer may be provided on the data pad and the common voltage pad. In this case, the data pad electrode and the common voltage pad may be formed on the additional insulating layer, To the data pad and to the common voltage pad.

According to an embodiment of the present invention, the gate pad unit GPP and the data pad unit DPP may be electrically connected to external wiring.

Although not shown, in another embodiment of the present invention, a gate driver mounted on the first base substrate may be provided instead of the gate pad portion. The gate driver may include a plurality of amorphous silicon transistors. The amorphous silicon transistors may be formed directly on the pad region of the first base substrate through the thin film transistor manufacturing process.

Also, a data driver mounted on the first base substrate may be provided instead of the data pad. The data driver may include a plurality of amorphous silicon transistors. The amorphous silicon transistors may be formed directly on the pad region of the first base substrate due to the thin film transistor manufacturing process.

The second substrate SUB2 faces the first substrate SUB1 and includes a second base substrate BS2, a color filter (not shown), a black matrix BM, a common electrode CE, SL).

The second base substrate BS2 may be a transparent or opaque insulating substrate, such as a silicon substrate, a glass substrate, a plastic substrate, or the like.

The color filter (not shown) may be disposed on the second base substrate BS2. The color filters may be any of red, green, and blue color filters that transmit only red, green, and blue light, respectively, for example. The color filters are provided in a plurality of, and are arranged in each corresponding pixel PX.

The black matrix BM is disposed on the second base substrate BS2 and shields light incident on the black matrix BM. Therefore, no image is displayed in the area corresponding to the black matrix BM. The black matrix BM is formed so as to surround the pixel PX and may be arranged in a lattice form when viewed in a plane to define a display area DA of the pixel PX. The black matrix BM may be formed by patterning a chromium (Cr) thin film, a chromium oxide (CrxOy) thin film, or a black organic film having a light transmittance substantially equal to that of the chromium thin film. Therefore, the aperture ratio of the pixel PX is determined according to the non-display area NDA in which the thin film transistor TFT is formed. That is, the smaller the non-display area NDA, the wider the display area DA and the greater the aperture ratio of the pixel PX.

The common electrode CE may be provided as a transparent electrode on the second base substrate BS2 and a voltage may be applied to the liquid crystal layer LCL together with the pixel electrode PE to form an electric field . However, the present invention is not limited thereto, and the common electrode CE may be included on the first substrate SUB1 to form an electric field with the pixel electrode PE.

The sealing portion SL may be provided along the edge of the second base substrate BS2. The sealing portion SL serves to bond the first substrate SUB1 and the second substrate SUB2 together. In addition, the sealing portion SL can seal the liquid crystal layer (LCL) to prevent liquid crystals from flowing out to the outside.

In an embodiment of the present invention, the sealing portion SL is positioned on the pad portion when the first substrate SUB1 and the second substrate SUB2 are attached to each other. In particular, the encapsulation unit SL may be provided so as to overlap with the gate pad unit GPP and the data pad unit DPP.

The sealing portion SL may be made of an acrylic resin, an epoxy resin, or the like. Here, the solid content of the epoxy resin can be improved to improve the adhesion of the sealing part SL.

The liquid crystal layer LCL controls light incident through the first substrate SUB1. The liquid crystal layer (LCL) includes a plurality of liquid crystal molecules having dielectric anisotropy. The liquid crystal molecules have, for example, a negative dielectric constant anisotropy, so that the applied electric field and the major axes of the liquid crystal molecules may be arranged in the perpendicular direction. Further, the liquid crystal molecules have a positive dielectric constant, and the long axis of the liquid crystal molecules can be arranged in a direction parallel to the applied electric field.

The liquid crystal molecules may be arranged by an alignment film (not shown) between the first substrate SUB1 and the second substrate SUB2 with the liquid crystal molecules interposed therebetween.

When an electric field is applied between the first substrate SUB1 and the second substrate SUB2, the liquid crystal molecules are rearranged in a specific direction between the first substrate SUB1 and the second substrate SUB2, Can be controlled.

The size of the second substrate SUB2 may be smaller than the size of the first substrate SUB1.

The driving unit may include a timing controller TC, a gate driving unit GD, and a data driving unit DD.

Referring again to FIG. 1, the timing controller TC receives control signals CTRL for controlling the display of an image signal RGB from the outside, for example, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, A data enable signal, and the like. The timing controller TC generates a data signal DAT and a second control signal CONT2 obtained by processing the video signal RGB according to the operation conditions of the display panel PNL based on the control signals CTRL. To the data driver DD and provides the first control signal CONT1 to the gate driver GD. The second control signal CONT2 includes a clock signal, a polarity inversion signal, and a line latch signal. The first control signal CONT1 may include a vertical synchronization start signal, an output enable signal, a gate pulse signal, have.

The gate driver (GD) is applied to the first and the gate-on voltage in response to a first control signal (CONT1) and the gate lines (GL _1, GL ~ _{n +1)} from the timing controller (TC).

The data driver DD is connected to the data lines DL ₁ to DL _{m +1} of the display panel PNL to apply a data voltage corresponding to the video signal to the pixels PX.

The data driver DD sequentially receives and shifts the data signals DAT for the pixels PX of one row in response to the second control signal CONT2 from the timing controller TC, And applies a data voltage corresponding to the signal DAT to the data lines DL ₁ to DL _{m +1} .

The gate driver GD and the data driver DD are mounted on a flexible printed circuit board (FPCB) and attached to the display panel PNL in the form of a TCP (tape carrier package) Can be provided. However, if necessary, the gate driver GD or the data driver DD may be directly mounted on the display panel PNL in a form of a plurality of drive IC chips, but is not limited thereto.

1 to 5, the gate driver GD according to an embodiment of the present invention may include a first printed circuit board PCB1 electrically connected to the gate pad unit GPP. The first printed circuit board PCB1 may extend in the second direction D2 along one side of the first substrate SUB1.

The gate driver GD may further include a first flexible printed circuit board (FPCB1) and a first driving chip IC1. The first flexible printed circuit board (FPCB1) connects the gate pad unit GPP and the first printed circuit board PCB1. The first driving IC IC1 may be mounted on the first flexible printed circuit board FPCB1 to provide the driving signal from the first printed circuit board PCB1 to the gate pad unit GPP.

The first flexible printed circuit board (FPCB1) may be arranged to overlap at least a part of the gate pad portion (GPP) on the gate pad portion (GPP). Accordingly, the first flexible printed circuit board (FPCB1) may be disposed between the gate pad portion (GPP) and the sealing portion (SL).

The first flexible printed circuit board (FPCB1) may be provided as a flexible film made of polyimide resin or the like. The first flexible printed circuit board FPCB1 may be formed of a material such as plasma or the like on the surface of the first flexible printed circuit board FPCB1 which is in contact with the sealing portion SL in order to enhance the adhesive force with the sealing portion SL. Plasma processing, ion beam processing, chemical processing, and the like.

The data driver DD may include a second printed circuit board PCB2 electrically connected to the data pad unit DPP. The second printed circuit board PCB2 may extend in the first direction D1 along another side of the first substrate SUB1.

The data driver DD may further include a second flexible printed circuit board (FPCB2) and a second driver chip IC2. The second flexible printed circuit board (FPCB2) connects the data driver (DD) and the second printed circuit board (PCB2). The second driving chip IC2 may be mounted on the second flexible printed circuit board FPCB2 to provide a driving signal to the data driving unit DD from the second printed circuit board PCB2.

The second flexible printed circuit board (FPCB2) may be disposed on the data driver (DD) so as to overlap with at least a part of the data driver (DD). Accordingly, the second flexible printed circuit board (FPCB2) may be disposed between the data driver (DD) and the sealing unit (SL).

The second flexible printed circuit board (FPCB2) may be provided as a flexible film made of polyimide resin or the like. The second flexible printed circuit board FPCB2 may be formed of a conductive material such as plasma or the like on the surface of the second flexible printed circuit board FPCB2 which is in contact with the sealing portion SL, Plasma processing, ion beam processing, chemical processing, and the like.

As described above, in the display device according to an embodiment of the present invention, since the sealing portion is disposed on the pad portion, the sealing portion of the non-display region of the first substrate, which is required for connecting the printed circuit board to the pad portion, Some areas can be reduced.

In an embodiment of the present invention, a gate pad portion and a data pad portion are provided, respectively, and a first printed circuit board and a second printed circuit board are connected to the first flexible printed circuit board and the second flexible printed circuit board But is not limited thereto.

For example, instead of the gate pad portion, the second printed circuit board may be provided to the gate driver mounted on the first base substrate. Or may be provided to the data driver mounted on the first base substrate instead of the data pad portion, so that the first printed circuit board may be omitted.

6 is a cross-sectional view of a display device according to another embodiment of FIG.

In an embodiment of the present invention, the encapsulant is made of an insulating material, but the present invention is not limited thereto. The encapsulant may be made of a conductive material.

Referring to FIG. 6, the common voltage pad unit CMPP includes a common voltage pad CMP and a common voltage pad electrode CMPE connected to the common voltage pad CMP. The common voltage pad CMP is connected to the common voltage line on the first insulating layer INS1. The common voltage pad electrode CMPE may be provided in direct contact with the common voltage pad CMP.

An encapsulant SL made of a conductive material may be provided on the common voltage line and the common voltage pad electrode CMPE. The common voltage may be applied to the common electrode CE through the encapsulation unit SL. Accordingly, a connecting portion (CL in FIG. 5) which is separately required for applying the common voltage to the common electrode line and the common voltage pad electrode CMPE can be omitted.

7 is a cross-sectional view of a display device according to another embodiment of the present invention.

In an embodiment of the present invention, the size of the first substrate is larger than that of the second substrate. However, the present invention is not limited thereto. In another embodiment of the present invention, The same size can be provided.

Referring to FIGS. 2 and 7, the first substrate SUB1 and the second substrate SUB2 may have the same size. As the first flexible printed circuit board (FPCB1) and the second flexible printed circuit board (FPCB2) are provided between the pad portion and the sealing portion SL, the first flexible printed circuit board (FPCB1) It is possible to reduce a part of the non-display area that is required for attaching the circuit board FPCB1 and the second flexible printed circuit board FPCB2. As a result, the display device can reduce the edge portion of the outer frame, that is, a bezel, and can realize a large screen easily compared with the conventional display device.

8 is a cross-sectional view of a display device according to another embodiment of the present invention.

Although the black matrix is included in the second substrate in one embodiment of the present invention, the present invention is not limited thereto. In another embodiment of the present invention, the black matrix may be included in the first substrate.

3 and 8, the first substrate SUB1 may include a first base substrate BS1, a color filter portion provided on the first base substrate BS1, and a pixel PX .

The color filter portion may be provided on a thin film transistor (TFT). The color filter unit may include a color filter (not shown) and a black matrix (BM).

The color filter is for providing color to light transmitted through each pixel. The color filter may be any one of a red color filter, a green color filter, and a blue color filter, and may be provided corresponding to each pixel region.

A first contact hole CH1 for exposing a part of the drain electrode DE of the thin film transistor TFT may be formed in the color filter portion. The pixel electrode PE is connected to the thin film transistor TFT through the first contact hole CH1.

Although not shown, a protective film for protecting the channel portion of the thin film transistor (TFT) may be provided between the color filter portion and the thin film transistor (TFT). The protective layer may cover the upper portion of the exposed semiconductor layer SM.

The pixel electrode PE is provided on the color filter portion. The pixel electrode PE is connected to the thin film transistor TFT through the first contact hole CH1 of the color filter portion.

 In the present embodiment, the first contact hole CH1 is formed by opening the region where the black matrix BM is formed, but the present invention is not limited thereto. In another embodiment, the first contact hole may open an area where the color filter CF is formed to connect the pixel electrode PE to the thin film transistor TFT.

Hereinafter, a method of manufacturing the display device in the display device according to the embodiment of the present invention will be described in detail. For the sake of convenience of explanation, the description overlapping with the description of the display device described above will be omitted.

9A to 9D are perspective views illustrating a method of manufacturing a display device according to an embodiment of the present invention. Hereinafter, for convenience of explanation, a manufacturing method of a display device will be described with reference to Figs. 2 to 5. Fig.

A method of manufacturing a display device according to an embodiment of the present invention includes the steps of forming a wiring portion on a first base substrate and a pad portion connected to the wiring portion, attaching a flexible printed circuit board on the pad portion, A method of manufacturing a flexible printed circuit board, comprising: forming a display layer on a first base substrate; forming an encapsulation on the second base substrate; bonding the first base substrate and the second base substrate together; And attaching the printed circuit board.

Referring to FIG. 9A, a wiring portion and a pad portion located at the end of the wiring portion may be formed on the first base substrate BS1.

The wiring portion includes a gate wiring portion and a data wiring portion.

The gate wiring portion includes a gate line GL, a gate electrode GE, a gate pad GP, and a common voltage line CML.

The gate wiring portion may be formed of a conductive material, for example, a metal. For example, the gate wiring portion may be formed as a single process by forming a metal layer on the entire surface of the first base substrate BS1 and patterning the metal layer by a photolithography process. The gate wiring portion may be formed of a single layer made of a single metal or an alloy, but not limited thereto, and may be formed of multiple layers of two or more kinds of metals and / or alloys thereof.

A first insulating layer INS1 is formed on the gate wiring portion, and a semiconductor layer SM is formed on the first insulating layer INS1. The semiconductor layer SM is provided on top of the gate electrode GE and overlaps with at least a part of the gate electrode GE when viewed in plan view. The semiconductor layer SM may be doped or undoped silicon, or an oxide semiconductor.

The data wiring portion is formed on the semiconductor layer SM. The data wiring portion includes a data line DL, a source electrode SE, a drain electrode DE, and a data pad DP.

The data wiring portion may be formed of a conductive material, for example, a metal. For example, the data wiring portion may be formed as a single process by forming a metal layer on the entire surface of the first base substrate BS1 and patterning the metal layer by a photolithography process. The data wiring portion may be formed of a single layer made of a single metal or an alloy, but not limited thereto, and may be formed of multiple layers of two or more kinds of metals and / or alloys thereof.

The gate electrode GE, the source electrode SE, the drain electrode DE, and the semiconductor layer SM formed in the above process form a thin film transistor (TFT).

A pixel electrode PE, a gate pad electrode GPE, and a data pad electrode DPE are formed on the thin film transistor TFT.

The pixel electrode PE, the gate pad electrode GPE and the data pad electrode DPE may be formed by forming a conductive layer on the first base substrate BS1 with a conductive material and then using a photolithography process, And then patterning the conductive layer. The pixel electrode PE is connected to the drain electrode DE through the first contact hole CH1. The gate pad electrode GPE is connected to the gate pad GP through a second contact hole CH2 to form a gate pad portion GPP. The data pad electrode DPE may be provided on the data pad DP to directly contact the data pad DP to form a data pad portion DPP.

A second insulating layer INS2 may be provided on the pixel electrode PE to protect the pixel electrode PE and the second insulating layer INS2 may be formed on the gate pad electrode GPE and the data pad electrode DPE). ≪ / RTI >

The flexible printed circuit board (FPCB) may be attached on the gate pad electrode GPE and the data pad electrode DPE.

A display layer is formed on the first base substrate BS1. In an embodiment of the present invention, the display layer may be a liquid crystal layer (LCL). However, the display layer is not limited thereto, and may be variously provided, such as an organic light emitting layer.

The liquid crystal layer LCL may be formed by dropping liquid crystals directly on the first base substrate BS1. In this case, since the liquid crystal is directly dropped on the substrate, it is possible to form the liquid crystal layer (LCL) of the large-area display device in a short time. In addition, since only a required amount of liquid crystal is directly dropped onto the substrate, consumption of liquid crystal can be minimized.

Referring to FIG. 9B, an encapsulation unit SL may be formed on the second base substrate BS2 along the edge of the second base substrate BS2.

The sealing portion SL may be formed of a semi-hardened polymer material. The polymeric material has a certain degree of fluidity before it is fully cured. The sealing portion SL can provide the polymer material to the edge of the second base substrate BS2 with a predetermined thickness. The sealing portion SL is formed at a position overlapping with the pad portion when the second base substrate BS2 and the first base substrate BS1 to be described later coalesce.

Referring to FIG. 9C, the first base substrate BS1 and the second base substrate BS2 are bonded together with the liquid crystal layer LCL and the sealing portion SL interposed therebetween. The sealing portion SL may be disposed to overlap with a pad portion and a portion of the flexible printed circuit board (FPCB) attached on the pad portion. The sealing portion SL may overlap the pad portion with the flexible printed circuit board (FPCB) interposed therebetween.

Referring to FIG. 9D, a printed circuit board (PCB) can be attached to the flexible printed circuit board (FPCB). The printed circuit board (PCB) may be electrically connected to the first substrate (SUB1) through the flexible printed circuit board (FPCB).

As described above, in the method of manufacturing a display device according to an embodiment of the present invention, a flexible printed circuit board is attached on a pad portion formed on a first substrate, and then a first substrate and a second substrate are bonded together. Then, the printed circuit board is attached to the flexible printed circuit board. Thus, a part of the non-display area required for attaching the flexible printed circuit board to the first substrate can be removed.

Conventionally, since the flexible printed circuit board is attached to the first substrate after attaching the first substrate and the second substrate, the first substrate requires a separate space to which the flexible printed circuit board is attached . Accordingly, the first substrate requires a larger area than the second substrate, and the flexible printed circuit board is attached to a portion of the area of the first substrate that exceeds the area of the second substrate.

However, in the display device according to an embodiment of the present invention, it is possible to reduce the size of the first substrate by at least the size of the second substrate. Accordingly, by reducing the width of the bezel of the display device, it is possible to provide a light-weighted display device. In addition, the cost for manufacturing the display device can be reduced.

The display device can easily realize a large screen by reducing the width of a bezel.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. It will be understood that various modifications and changes may be made thereto without departing from the scope of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: display panel SUB1: first substrate
SUB2: second substrate BS1: first base substrate
BS2: second base substrate LCL: liquid crystal layer
SL: Encapsulation PCB: Printed circuit board
FPCB: flexible printed circuit board GPP: gate pad part
DPP: data pad unit CMPP: common voltage pad unit
GP: Gate pad GPE: Gate pad electrode
DP: Data pad DPE: Data pad electrode
CMP: common voltage pad CMPE: common voltage pad electrode

Claims (20)

A first substrate including a display region in which pixels are formed and a non-display region excluding the display region, a second substrate facing the first substrate, and a display layer disposed between the first substrate and the second substrate, ,
The first substrate
A first base substrate;
A wiring portion provided on the first base substrate; And
And a pad portion connected to the wiring portion and connected to the external wiring,
The second substrate
A second base substrate; And
And an encapsulant provided along an edge of the second base substrate,
And the sealing portion is disposed on the pad portion. The method according to claim 1,
Wherein the second substrate further comprises a common electrode, a black matrix, and a color filter provided on the second base substrate. 3. The method of claim 2,
Wherein the wiring portion includes a gate line, a data line intersecting the gate line, a thin film transistor for driving each pixel, a pixel electrode connected to the thin film transistor, and a common voltage line for providing a common voltage to the common electrode. The method of claim 3,
Wherein the common voltage line is provided along at least a part of edges of the display region when viewed in plan. 5. The method of claim 4,
Wherein the pad portion includes a gate pad portion connected to the gate line, a data pad portion connected to the data line, and a common voltage pad portion connected to the common voltage line. 6. The method of claim 5,
And a flexible printed circuit board attached on the pad portion and connecting the pad portion and the external wiring. The method according to claim 6,
Further comprising a printed circuit board provided on at least one side of the first substrate and electrically connected to the pad portion via the flexible printed circuit board. 8. The method of claim 7,
Wherein the flexible printed circuit board overlaps at least a part of the pad portion on the pad portion. 9. The method of claim 8,
Wherein the sealing portion overlaps the pad portion with the flexible printed circuit board interposed therebetween. 10. The method of claim 9,
Wherein the sealing portion is a compound containing a polymer resin. The method according to claim 1,
And the sealing portion overlaps with the common voltage pad portion. 12. The method of claim 11,
Wherein the sealing portion is made of a conductive material. The method according to claim 1,
Wherein the first substrate is larger than or equal to the second substrate. The method according to claim 1,
Wherein the first substrate further comprises a black matrix and a color filter formed on the first base substrate. The method according to claim 1,
Wherein the display layer is a liquid crystal layer. Forming a wiring portion on the first base substrate and a pad portion connected to the wiring portion;
Attaching a flexible printed circuit board on the pad portion;
Forming a display layer on the first base substrate;
Forming an encapsulant on the second base substrate;
Attaching the first base substrate and the second base substrate together so that the sealing portion is disposed on the pad portion; And
And attaching a printed circuit board to the flexible printed circuit board. 17. The method of claim 16,
Wherein the encapsulating portion is formed along an edge of the second base substrate in the step of forming the encapsulation portion. 18. The method of claim 17,
Wherein the sealing portion overlaps the pad portion with the flexible printed circuit board interposed therebetween. 19. The method of claim 18,
Wherein the display layer is a liquid crystal layer. 20. The method of claim 19,
Wherein the liquid crystal layer is formed by dropping liquid crystals on the first base substrate.

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