KR20150095571A - Modulator using non-uniform 16-symbol signal constellation for low density parity check codeword with 4/15 code rate, and method using the same - Google Patents

Abstract

Disclosed are a modulator and a modulation method using a non-uniform 16-symbol signal constellation. The modulator using a non-uniform 16-symbol signal constellation according to an embodiment of the present invention comprises: a memory receiving a code word corresponding to an LDPC code having code rate of 4/15; and a processor mapping the code word on 16 symbols of the non-uniform 16-symbol signal constellation in four bits unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a modulator using an unequal 16-symbol signal constellation for an LDPC codeword having a code rate of 4/15 and a modulating method using the same. , AND METHOD USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to symbol mapping using non-uniform signal constellation, and more particularly, to a modulator for transmitting error-correction-encoded data in a digital broadcasting channel.

Bit-Interleaved Coded Modulation (BICM) is a bandwidth-efficient transmission technique that uses an error-correction coder, a bit-by-bit interleaver, and a high-order modulator It is a combined form.

The BICM uses a low-density parity check (LDPC) encoder or turbo encoder as an error correction encoder, and can provide excellent performance with a simple structure. In addition, the BICM provides a high level of flexibility because it can select a variety of modulation order, error correction code length, and coding rate. Because of these advantages, BICM is not only used in broadcast standards such as DVB-T2 or DVB-NGH, but is also likely to be used in other next-generation broadcast systems.

Despite these advantages, the BICM exhibits a significant difference from the Shannon limit in terms of capacity. In order to reduce the difference from the Shannon limit, modulation using a better signal constellation is essential.

It is an object of the present invention to provide a modulator and a modulation method using an unequal signal constellation that is more efficient than uniform signal constellation in order to transmit error-correction-encoded data in a broadcasting system channel.

It is also an object of the present invention to provide a modulator and a modulation method for unequal 16-symbol mapping, which is optimized for an LDPC encoder with a coding rate of 4/15 and can be applied to a next generation broadcasting system such as ATSC 3.0 .

According to an aspect of the present invention, there is provided a modulator using an unequal 16-symbol signal constellation, comprising: a memory for receiving a codeword corresponding to an LDPC code having a code rate of 4/15; And a processor for mapping the codeword to one of 16 symbols of unequal 16-symbol signal constellation in 4-bit units.

At this time, the 16 symbols are non-uniform in distance between the symbols, and are symmetric with respect to the first group of four symbols in the first quadrant, the four symbols in the first group, A fourth group of four symbols symmetric with respect to the origin, and a fourth group of four symbols symmetric with respect to the real axis with respect to the fourth group of four symbols, 4 groups.

In this case, a vector corresponding to four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group is w and four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) is -conj (w) (conj (w) is a function that outputs the complex conjugate of all elements of w), and the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) is-w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group may be conj (w) .

In this case, two of the four symbols of the first group may be symmetric with respect to the amplitude of the real component and the amplitude of the imaginary component.

In this case, the four symbols of the first group are w ₀ , w ₁ , w ₂ and w ₃ , and | real (w ₀ ) | _{= | Imaginary (w 1) |} (real (i) is a function that outputs a real component of the i, imaginary (i) is a function for outputting an imaginary component of the i, i is an arbitrary complex number) and, | real (w ₁ ) | = | imaginary (w ₀ ) |, and | real (w ₂ ) | = | imaginary (w ₃ ) |, and real (w ₃ ) | = | imaginary (w ₂ ) |.

At this time, the 16 symbols can be defined as shown in the following table.

[table]

Also, a modulation method using an unequal 16-symbol signal constellation according to the present invention includes: receiving a codeword corresponding to an LDPC code with a code rate of 4/15; Mapping the codeword in units of 4 bits to one of 16 symbols of unequal 16-symbol signal constellation; And adjusting at least one of an amplitude and a phase of a carrier corresponding to the mapping.

Also, the BICM apparatus according to the present invention includes an error correcting encoder for outputting an LDPC codeword with a coding rate of 4/15; A bit interleaver for interleaving the LDPC codeword in a bit group unit of a size corresponding to a parallel factor of the LDPC codeword and outputting an interleaved codeword; And a modulator for mapping the interleaved codeword to 16 symbols of unequal 16-symbol signal constellation in 4-bit units.

According to the present invention, a signal constellation for transmitting error-correction-encoded data in a next-generation broadcasting system is intentionally distorted, thereby achieving remarkably improved performance compared to the uniform signal constellation.

In addition, the present invention is optimized for an LDPC encoder with a coding rate of 4/15, and provides unequal 16-symbol signal constellations that can be applied to next generation broadcasting systems such as ATSC 3.0.

1 is a block diagram illustrating a system for transmitting / receiving a broadcast signal according to an embodiment of the present invention.
2 is a flowchart illustrating a method of transmitting / receiving a broadcast signal according to an exemplary embodiment of the present invention.
3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
4 is a diagram illustrating bit groups of an LDPC codeword having a length of 64,800.
FIG. 5 is a diagram illustrating bit groups of an LDPC codeword having a length of 16200.
6 is a diagram illustrating interleaving in units of bit groups according to an interleaving sequence.
7 is a diagram showing the signal constellation of 16-QAM.
8 is a diagram illustrating an unequal 16-symbol signal constellation optimized for an LDPC code with a code rate of 4/15.
FIG. 9 is a diagram showing the performance of the equal signal constellation shown in FIG. 7 and the uneven signal constellation shown in FIG. 8 for an LDPC code with a coding rate of 4/15.
10 is a block diagram illustrating a modulator using a 16-symbol unequal signal constellation according to an embodiment of the present invention.
11 is a flowchart illustrating a modulation method using a 16-symbol unequal signal constellation according to an embodiment of the present invention.

The present invention will now be described in detail with reference to the accompanying drawings. Hereinafter, a repeated description, a known function that may obscure the gist of the present invention, and a detailed description of the configuration will be omitted. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a system for transmitting / receiving a broadcast signal according to an embodiment of the present invention.

Referring to FIG. 1, it can be seen that the BICM device 10 and the BICM receiving device 30 perform communication via the wireless channel 20.

The BICM apparatus 10 generates k bits of information bits 11 by encoding the information bits 11 in the error correction coder 13 to form an n-bit codeword. At this time, the error correction encoder 13 may be an LDPC encoder or a turbo encoder.

The codeword is interleaved by the bit interleaver 14 to generate an interleaved codeword.

At this time, interleaving can be performed on a bit group basis. In this case, the error correction encoder 13 may be an LDPC encoder having a length of 16200 and a coding rate of 4/15, and a codeword having a length of 16200 may be divided into a total of 45 bit groups, And 360 bits, which is a parallel factor of the codeword.

In this case, the interleaving may be performed in units of bit groups in accordance with an interleaving sequence to be described later.

At this time, the bit interleaver 14 effectively dissociates the cluster error occurring in the channel, thereby preventing performance degradation of the error correction code. At this time, the bit interleaver 14 can be designed individually according to the length of the error correction code, the coding rate, and the modulation order.

The interleaved codeword is modulated by the modulator 15 and transmitted via the antenna 17.

At this time, the modulator 15 is a concept including a symbol mapping device. At this time, the modulator 15 may be a symbol mapping device that performs 16-symbol mapping that maps codes to 16 constellations.

At this time, the modulator 15 may be a uniform modulator such as a QAM (Quadrature Amplitude Modulation) modulator, or may be a non-uniform modulator.

In particular, the modulator 15 may be a symbol mapping device for performing NUC (Non-Uniform Constellation) symbol mapping with 16 constellations. That is, the modulator 15 can map the interleaved codeword to 16 symbols of the unequal 16-symbol signal constellation in 4-bit units.

The signal transmitted through the wireless channel 20 is received via the antenna 31 of the BICM receiving apparatus 30 and the BICM receiving apparatus 30 undergoes the reverse process of the process occurring in the BICM apparatus 10. [ That is, the received data is demodulated by the demodulator 33, deinterleaved by the bit deinterleaver 34, and decoded by the error correction decoder 35 to finally recover the information bits.

It will be apparent to those skilled in the art that the above-described transmission / reception process is described within the minimum range necessary to explain the features of the present invention, and that many other processes necessary for data transmission can be added.

2 is a flowchart illustrating a method of transmitting / receiving a broadcast signal according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a method for transmitting / receiving a broadcast signal according to an embodiment of the present invention first performs error correction coding of input bits (S210).

That is, in step S210, k bits of information bits are encoded by an error correction encoder to generate an n-bit codeword.

In this case, step S210 may be performed in the same manner as the LDPC coding method described later.

In addition, in the broadcast signal transmitting / receiving method, interleaved codewords are generated by interleaving n-bit codewords in bit group units (S220).

In this case, the n-bit codeword may be an LDPC codeword having a length of 16200 and a coding rate of 4/15, a codeword having a length of 16200 may be divided into a total of 45 bit groups, and each of the bit groups may be an LDPC codeword May include 360 bits corresponding to a parallel factor of < RTI ID = 0.0 >

In this case, the interleaving may be performed in units of bit groups in accordance with an interleaving sequence to be described later.

Also, the broadcasting signal transmitting / receiving method modulates the encoded data (S230).

That is, in step S230, the interleaved codeword is modulated by the modulator.

At this time, the modulator is a concept including a symbol mapping device. At this time, the modulator may be a symbol mapping device that performs 16-symbol mapping that maps codes to 16 constellations.

In this case, the modulator may be a uniform modulator such as a QAM (Quadrature Amplitude Modulation) modulator, or may be a non-uniform modulator.

In particular, the modulator may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping with 16 constellations. That is, the modulator can map the interleaved codewords to 16 symbols of unequal 16-symbol signal constellation in 4-bit units.

In addition, the broadcasting signal transmitting / receiving method transmits the modulated data (S240).

That is, in step S240, the modulated codeword is transmitted on the wireless channel through the antenna.

In addition, the broadcasting signal transmitting / receiving method demodulates the received data (S250).

That is, the step S250 receives the signal transmitted through the radio channel through the antenna of the receiver and demodulates the received data by the demodulator.

Also, the broadcasting signal transmitting / receiving method deinterleaves the demodulated data (S260). At this time, the deinterleaving in step S260 may correspond to an inverse process of step S220.

Also, the broadcasting signal transmitting / receiving method performs error correction decoding on the deinterleaved codeword (S270).

That is, in step S270, error correction decoding is performed through the error correction decoder of the receiver to finally recover the information bits.

In this case, step S270 may correspond to an inverse process of an LDPC encoding method to be described later.

The LDPC (Low Density Parity Check) code is known as a code close to the Shannon limit in an AWGN (Additive White Gaussian Noise) channel. The LDPC code is asymptotically superior to the turbo code, .

Generally, an LDPC code is defined by a randomly generated low density PCM (Parity Check Matrix). However, a randomly generated LDPC code not only requires a large amount of memory to store the PCM, but also takes a long time to access the memory. In order to solve such a problem, a quasi-cyclic LDPC (QC-LDPC) code has been proposed, and a QC-LDPC code composed of a zero matrix or a CPM (Circulant Permutation Matrix) Lt; RTI ID = 0.0 > PCM. ≪ / RTI >

[Equation 1]

Here, J is a CPM whose size is L x L and is given by the following equation (2). In the following, L may be 360.

&Quot; (2) "

In addition, J ⁱ is the L x L identity matrix I (= J ⁰ ) shifted to the right i (0 = i L) times, and J ^∞ is the L x L zero matrix. Therefore, in the QC-LDPC code, only the exponent ^{i needs} to be stored in order to store J ⁱ , so that the memory required to store the PCM is greatly reduced.

3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of the matrices A and C are g x K and (N-K-g) x (K + g), respectively. The matrix Z is a zero matrix whose magnitude is gx (NKg), the matrix D is an identity matrix whose magnitude is (NKg) x (NKg), the matrix B is a dual diagonal matrix of size gxg matrix. In this case, the matrix B may be a matrix in which all elements other than the diagonal elements and the elements neighboring the lower diagonal are 0, and may be defined as Equation (3).

&Quot; (3) "

Where I _LxL is an identity matrix of size L x L.

That is, the matrix B may be a general (bit-wise) diagonal diagonal matrix or a block-wise diagonal matrix as shown in Equation (3). A bit-wise double diagonal matrix is disclosed in detail in Korean Patent Publication No. 2007-0058438.

Particularly, when the matrix B is a bit-wise diagonal matrix, row permutation or column permutation is applied to the PCM of the structure shown in FIG. 3 including the matrix B It will be apparent to those skilled in the art that it may be converted to quasi-cyclic.

In this case, N is the length of the codeword, and K is the length of the information.

In the present invention, a newly designed QC-LDPC code with a code rate of 4/15 and a codeword length of 16200 is proposed as shown in Table 1 below. That is, we propose an LDPC code that receives information of length 4320 and generates an LDPC codeword of length 16200.

Table 1 shows the sizes of the A, B, C, D, and Z matrices of the QC-LDPC code of the present invention.

The newly designed LDPC code can be displayed in a sequence, and an equivalent relation between the sequence and the matrix (parity bit check matrix) is established, and the sequence can be expressed as shown in the following table.

[table]

Line 1: 19 585 710 3241 3276 3648 6345 9224 9890 10841

Second line: 181 494 894 2562 3201 4382 5130 5308 6493 10135

Third line: 150 569 919 1427 2347 4475 7857 8904 9903

4th line: 1005 1018 1025 2933 3280 3946 4049 4166 5209

5th line: 420 554 778 6908 7959 8344 8462 10912 11099

6th line: 231 506 859 4478 4957 7664 7731 7908 8980

Line 7: 179 537 979 3717 5092 6315 6883 9353 9935

*

* Line 8: 147 205 830 3609 3720 4667 7441 10196 11809

Ninth line: 60 1021 1061 1554 4918 5690 6184 7986 11296

Line 10: 145 719 768 2290 2919 7272 8561 9145 10233

11th line: 388 590 852 1579 1698 1974 9747 10192 10255

Line 12: 231 343 485 1546 3155 4829 7710 10394 11336

Line 13: 4381 5398 5987 9123 10365 11018 11153

Line 14: 2381 5196 6613 6844 7357 8732 11082

Line 15: 1730 4599 5693 6318 7626 9231 10663

The LDPC codes in the form of a sequence are widely used in the DVB standard.

를 생성한다. 여기서, M₁=g, M₂=N-K-g이다. 또한, M₁은 이중 대각행렬(dual diagonal matrix) B에 대응하는 패러티(parity)의 크기이며, M₂는 항등행렬 D에 대응하는 패러티의 크기이다. 부호화 과정은 다음과 같다.According to an embodiment of the present invention, an LDPC code denoted by a sequence is encoded as follows. Assume an information block S = (s ₀ , s ₁ , ..., s _{K - 1} ) with an information size _K. An LDPC encoder uses an information block S having a size K to generate a codeword having a size of N = K + M ₁ + M ₂ ,

. Here, M ₁ = g and M ₂ = NKg. Also, M ₁ is the parity size corresponding to the dual diagonal matrix B, and M ₂ is the parity size corresponding to the identity matrix D. The encoding process is as follows.

- initialization:

&Quot; (4) "

를 상기 테이블의 수열의 제1행에 명시된 패러티 비트 주소들(parity bit addresses)에서 누적(accumulate)한다. 예를 들어, 길이가 16200이며, 부호율이 4/15인 LDPC 부호에서의 누적 과정은 다음과 같다.-first

At the parity bit addresses specified in the first row of the table's sequence. For example, the accumulation process in an LDPC code having a length of 16200 and a code rate of 4/15 is as follows.

)은 GF(2)에서 일어난다.Here, add (

) Occurs in GF (2).

들에 대해서는, 하기 수학식 5에서 계산된 패러티 비트 주소들에서 누적한다.- the next L-1 information bits, i.

Are accumulated at the parity bit addresses calculated in Equation (5) below.

&Quot; (5) "

에 대응되는 패러티 비트 주소들, 즉 상기 테이블의 수열의 제1행에 표기된 패러티 비트 주소들을 나타내며, Q₁ = M₁/L, Q₂ = M₂/L, L = 360이다. 또한, Q₁과 Q₂는 하기 표 2에 정의된다. 예를 들어, 길이가 16200이며, 부호율이 4/15인 LDPC 부호는 M₁ = 1080, Q₁ = 3, M₂ = 10800, Q₂ = 30, L = 360이므로, 두 번째 비트

에 대해서는 상기 수학식 5를 이용하면 다음과 같은 연산이 수행된다.Where x is the first bit

Q ₁ = M ₁ / L, Q ₂ = M ₂ / L, and L = 360, which are the parity bit addresses corresponding to the parity bit addresses corresponding to the parity bits in the table. Q ₁ and Q ₂ are defined in Table 2 below. For example, the LDPC code having a length of 16200 and a coding rate of 4/15 is M ₁ = 1080, Q ₁ = 3, M ₂ = 10800, Q ₂ = 30 and L =

Using Equation (5), the following operation is performed.

Table 2 shows the sizes of M ₁ , M ₂ , Q ₁ and Q ₂ of the designed QC-LDPC code.

부터

까지의 새로운 360개의]-the next

from

Up to 360 new]

The information bits calculate and accumulate the addresses of the parity bit accumulators from Equation (5) using the second row of the sequence.

Similarly, for all groups of new L information bits, the address of the parity bit accumulators from Equation (5) is calculated and accumulated using a new row of the sequences.

에서

까지의 모든 정보비트들이 사용된 후, i = 1부터 시작하여 하기 수학식 6의 연산을 순차적으로 수행한다.-

in

All the information bits up to i = 1 are used, and then the operation of Equation (6) is sequentially performed starting from i = 1.

&Quot; (6) "

Next, when parity interleaving is performed as shown in Equation (7), parity generation corresponding to the diagonal diagonal matrix B is completed.

&Quot; (7) "

)를 이용하여 이중 대각행렬 B에 대응하는 패러티 생성이 완료되면, M₁개의 생성된 패러티(

)을 이용하여, 항등행렬 D에 대응하는 패러티를 생성한다.K information bits (

), When parity generation corresponding to the diagonal diagonal matrix B is completed, M ₁ generated parity (

), And generates a parity corresponding to the identity matrix D.

에서

까지의 L개의 비트들로 구성된 모든 그룹(group)들에 대해서, 상기 수열들의 새로운 행(이중 대각행렬 B에 대응하는 패러티를 생성할 때 이용한 마지막 행의 바로 다음 행부터 시작)과 상기 수학식 5를 이용하여 패러티 비트 누적기들의 주소를 계산하고, 관련 연산을 수행한다.-

in

For each group consisting of L bits from the first diagonal matrix B to the new row of the series (starting from the immediately following row of the last row used to generate the parity corresponding to the diagonal diagonal matrix B) To calculate the addresses of the parity bit accumulators, and to perform related calculations.

에서

까지의 모든 비트들이 사용된 후, 하기 수학식 8과 같은 패러티 인터리빙을 수행하면, 항등행렬 D에 대응하는 패러티 생성이 완료된다.-

in

And parity interleaving as shown in Equation (8) below is performed, parity generation corresponding to the identity matrix D is completed.

&Quot; (8) "

4 is a diagram illustrating bit groups of an LDPC codeword having a length of 64,800.

Referring to FIG. 4, it can be seen that an LDPC codeword having a length of 64800 is divided into 180 bit groups (0 ^th to 179 ^th groups).

In this case, 360 may be a parallel factor (PF) of an LDPC codeword. That is, since the PF is 360, the LDPC codeword having a length of 64800 is divided into 180 bit groups as shown in FIG. 4, and each bit group includes 360 bits.

FIG. 5 is a diagram illustrating bit groups of an LDPC codeword having a length of 16200.

Referring to FIG. 5, it can be seen that an LDPC codeword having a length of 16200 is divided into 45 bit groups (0 ^th group to 44 ^th group).

In this case, 360 may be a parallel factor (PF) of an LDPC codeword. That is, since PF is 360, an LDPC codeword having a length of 16200 is divided into 45 bit groups as shown in FIG. 5, and each bit group includes 360 bits.

6 is a diagram illustrating interleaving in units of bit groups according to an interleaving sequence.

Referring to FIG. 6, it can be seen that interleaving is performed by changing the order of bit groups by the designed interleaving sequence.

For example, suppose that the interleaving sequence for an LDPC codeword of length 16200 is as follows.

Interleaving sequence = {24 34 15 11 2 28 17 25 5 38 19 13 6 39 1 14 33 37 29 12 42 31 30 32 36 40 26 35 44 4 16 8 20 43 21 7 0 18 23 3 10 41 9 27 22}

Then, the order of the bit groups of the LDPC codeword as shown in FIG. 4 is changed as shown in FIG. 6 by the interleaving sequence.

That is, the LDPC codeword 610 and the interleaved codeword 620 each include 45 bit groups, and the 24th bit group of the LDPC codeword 610 is interleaved with the LDPC codeword 620 by the interleaving sequence. The 34th bit group of the LDPC codeword 610 becomes the first bit group of the interleaved LDPC codeword 620 and the 15th bit group of the LDPC codeword 610 is interleaved The 11th bit group of the LDPC codeword 610 becomes the third bit group of the interleaved LDPC codeword 620 and the second bit group of the LDPC codeword 620 becomes the second bit group of the LDPC codeword 620, Th bit group becomes the fourth bit group of the interleaved LDPC codeword 620. [

는 N _group = N _ldpc / 360 개의 비트그룹들로 쪼개어진다. 이 때, N _ldpc 는 16200일 수 있다.LDPC codeword with length N _ldpc

Is divided into N _group = N _ldpc / 360 bit groups. At this time, N _ldpc may be 16200.

&Quot; (9) "

Here, X _j denotes a j-th bit group, and each X _j consists of 360 bits.

The LDPC codewords divided into bit groups are interleaved as shown in Equation (10).

&Quot; (10) "

Here, Y _j denotes an interleaved jth bit group, and [pi] ( j ) is a permutation order for bit group unit interleaving. The permutation order corresponds to the interleaving sequence of Equation (11).

&Quot; (11) "

Interleaving sequence

= {34 3 19 35 25 2 17 36 26 38 0 40 27 10 7 43 21 28 15 6 1 37 18 30 32 33 29 22 12 13 5 23 44 14 4 31 20 39 42 11 9 16 41 8 24}

That is, when each of the codeword and interleaved codeword includes 45 bit groups from the 0-th bit group to the 44-th bit group, the interleaving sequence of Equation (11) The 3 rd bit group of the codeword becomes the first bit group of the interleaved codeword, the 19 th bit group of the codeword becomes the second bit group of the interleaved codeword, And the eighth bit group of the codeword becomes the 43rd bit group of the interleaved codeword and the 24th bit group of the codeword becomes the third bit group of the interleaved codeword, And is the 44th bit group of the interleaved codeword.

In particular, the interleaving sequence shown in Equation (11) is optimized when a 16-symbol mapping (especially NUC symbol mapping) is used and an LDPC encoder with a length of 16200 and a coding rate of 4/15 is used.

Generally, a uniform QAM (Quadrature Amplitude Modulation) is used to transmit error-correction-coded data in broadcasting and communication systems.

7 is a diagram showing the signal constellation of 16-QAM.

Referring to FIG. 7, it can be seen that 16 symbols of the signal constellation of 16-QAM in which 4 bits are mapped are uniformly distributed.

In FIG. 7, gray-mapping is applied to each bit-to-bit mapping, but bit-string mapping of other types is also available.

The uniform 16-QAM shown in FIG. 7 has a constant distance between constellation points. This uniform QAM has an advantage of being able to be used irrespective of the coding rate of the error correcting code, but it is inferior to the non-uniform signal characteristic specific to the specific code rate. Theoretically, when the amplitude of a channel input signal (transmission signal) and the amplitude of a channel itself simultaneously follow a Gaussian distribution in an AWGN (Addictive White Gaussian Noise) channel environment, It is known that the capacity, which is the mutual information of the user, is the maximum. Based on this theoretical background, better performance can be obtained compared to the uniformity through intentional distortion of the signal constellation.

The design of the unequal signal constellation may use a symmetrical design technique.

That is, in the case of 16-QAM, the signal constellation symbols for the remaining three quadrants can be designed symmetrically after designing the four signal constellation symbols in the first quadrant.

For example, if the vector of the four signal constellation symbols in the first quadrant is w = (w ₀ , w ₁ , w ₂ , w ₃ ), the vectors of the signal constellation symbols for the remaining quadrants can be defined as follows.

- Quadrant 1: (w ₀ , w ₁ , w ₂ , w ₃ ) = w

- quadrant 2: (w ₄ , w ₅ , w ₆ , w ₇ ) = -conj (w)

- Quadrant 3: (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) = -w

- Quadrant 4: (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) = conj (w)

Where conj (w) may be a function that outputs the complex conjugate of all elements of w.

Of course, the vector of signal constellation symbols may be determined in a variety of different ways.

Symbol w _i can have the bit stream mapping value corresponding to a decimal value (decimal value) i. For example, w ₃ = 3 ₍₁₀₎ = 0010 ₍₂₎ .

When designing unequal signal constellations, using symmetric design techniques has the advantage of greatly reducing complexity.

To further reduce the design complexity, it can be assumed that the amplitudes of the real and imaginary of the vector w corresponding to the four signal constellation symbols of the first quadrant are symmetric. That is, two of the four symbols in the first quadrant may be symmetrical with respect to the magnitude of the real component and the magnitude of the imaginary component.

In this case, instead of designing four complex numbers, four PAM (Pulse Amplitude Modulation) points are designed. At this time, power can be normalized after setting the smallest PAM value to 1 and finding the remaining three PAM values. As a result, by using the symmetry mentioned above, three PAM values can be designed to produce a total of 16 signal constellations.

Generally, M-1 PAM values are designed to design L = M ² signal constellations.

When M-1 PAM values are obtained, power normalization is performed on the obtained M-1 PAM values and the smallest PAM value to define PAM_norm = [P ₁ P ₂ ... P _M ]. In the w wanted to use the PAM _norm, and the PAM value of the real and imaginary using the assumption of symmetric (symmetric), can be expressed as follows.

| real (w ₀ ) | = | imaginary (w ₁ ) |

| real (w ₁ ) | = | imaginary (w ₀ ) |

| real (w ₂ ) | = | imaginary (w ₃ ) |

| real (w ₃ ) | = | imaginary (w ₂ ) |

(real (i) is a function for outputting the real component of i, imaginary (i) is a function for outputting the imaginary component of i, and i is an arbitrary complex number)

That is, if real values of a vector w corresponding to quadrant symbols are defined, then all imaginary values of w are also defined. In the case of 16-QAM with a total of four symbols in the first quadrant, a total of 4! (Factorial) = 4 X 3 X 2 X 1 = 24 combinations is obtained as shown in Table 3 below. Table 3 below shows twenty-four ways of obtaining w, a vector corresponding to quadrant symbols.

Way w _{0 Real Imaginary of} w ₀ w _{1 Real Imaginary of} w ₁ w _{2 Real Imaginary of} w _{2 Real of} w _{3 Imaginary of} w ₃ One P ₁ P ₂ P ₂ P ₁ P ₃ P ₄ P ₄ P ₃ 2 P ₁ P ₂ P ₂ P ₁ P ₄ P ₃ P ₃ P ₄ 3 P ₁ P ₃ P ₃ P ₁ P ₂ P ₄ P ₄ P ₂ 4 P ₁ P ₃ P ₃ P ₁ P ₄ P ₂ P ₂ P ₄ 5 P ₁ P ₄ P ₄ P ₁ P ₂ P ₃ P ₃ P ₂ 6 P ₁ P ₄ P ₄ P ₁ P ₃ P ₂ P ₂ P ₃ 7 P ₂ P ₁ P ₁ P ₂ P ₃ P ₄ P ₄ P ₃ 8 P ₂ P ₁ P ₁ P ₂ P ₄ P ₃ P ₃ P ₄ 9 P ₂ P ₃ P ₃ P ₂ P ₁ P ₄ P ₄ P ₁ 10 P ₂ P ₃ P ₃ P ₂ P ₄ P ₁ P ₁ P ₄ 11 P ₂ P ₄ P ₄ P ₂ P ₁ P ₃ P ₃ P ₁ 12 P ₂ P ₄ P ₄ P ₂ P ₃ P ₁ P ₁ P ₃ 13 P ₃ P ₁ P ₁ P ₃ P ₂ P ₄ P ₄ P ₂ 14 P ₃ P ₁ P ₁ P ₃ P ₄ P ₂ P ₂ P ₄ 15 P ₃ P ₂ P ₂ P ₃ P ₁ P ₄ P ₄ P ₁ 16 P ₃ P ₂ P ₂ P ₃ P ₄ P ₁ P ₁ P ₄ 17 P ₃ P ₄ P ₄ P ₃ P ₁ P ₂ P ₂ P ₁ 18 P ₃ P ₄ P ₄ P ₃ P ₂ P ₁ P ₁ P ₂ 19 P ₄ P ₁ P ₁ P ₄ P ₂ P ₃ P ₃ P ₂ 20 P ₄ P ₁ P ₁ P ₄ P ₃ P ₂ P ₂ P ₃ 21 P ₄ P ₂ P ₂ P ₄ P ₁ P ₃ P ₃ P ₁ 22 P ₄ P ₂ P ₂ P ₄ P ₃ P ₁ P ₁ P ₃ 23 P ₄ P ₃ P ₃ P ₄ P ₁ P ₂ P ₂ P ₁ 24 P ₄ P ₃ P ₃ P ₄ P ₂ P ₁ P ₁ P ₂

For example, the optimal PAM_norm value designed for an LDPC code with a coding rate of 4/15 may be [0.3412 0.5241 0.5797 1.1282].

In this case, the obtained PAM_norm is converted into a vector w corresponding to the quadrant symbols by using the method 1 of Table 3 to obtain w = [0.3412 + 0.5241i 0.5241 + 0.3412i 0.5797 + 1.1282i 1.1282 + 0.5797i] have.

Table 4 below shows the 16 symbols of the unequal 16-symbol signal constellation optimized for the LDPC code with a coding rate of 4/15. In general, since error correcting codes differ in operating SNR and error correcting ability according to a coding rate, it is necessary to use an optimized vector w value for each coding rate to maximize the performance of the BICM. If unequal signal constellation optimized at a specific code rate is used at a different code rate, it is important to use unequal signal constellation corresponding to the code rate of the LDPC code since the performance of the BICM can be significantly degraded.

W Constellation 0    0.3412 + 0.5241i One    0.5241 + 0.3412i 2    0.5797 + 1.1282i 3    1.1282 + 0.5797i 4   -0.3412 + 0.5241i 5   -0.5241 + 0.3412i 6   -0.5797 + 1.1282i 7   -1.1282 + 0.5797i 8    0.3412 - 0.5241i 9    0.5241 - 0.3412i 10    0.5797 - 1.1282i 11    1.1282 - 0.5797i 12   -0.3412 - 0.5241i 13   -0.5241 - 0.3412i 14   -0.5797 - 1.1282i 15   -1.1282 - 0.5797i

8 is a diagram illustrating an unequal 16-symbol signal constellation optimized for an LDPC code with a code rate of 4/15.

Referring to FIG. 8, it can be seen that 16 symbols of the 16-symbol unequal signal constellation in which 4 bits are mapped are distributed non-uniformly.

Figure 8 shows the unequal 16-symbol signal constellation calculated based on the designed w. In this case, the bit stream of each symbol shown in FIG. 8 is expressed based on gray mapping, but other types of bit stream mapping are also applicable.

FIG. 9 is a diagram showing the performance of the equal signal constellation shown in FIG. 7 and the uneven signal constellation shown in FIG. 8 for an LDPC code with a coding rate of 4/15.

Referring to FIG. 9, it can be seen that the BER (Bit Error Rate) and the FER (Frame Error Rate) of the unequal signal constellation and the uniform 16-QAM according to the present invention are shown. In FIG. 9, the non-uniform signal constellation shows better performance than the uniform 16-QAM.

10 is a block diagram illustrating a modulator using a 16-symbol unequal signal constellation according to an embodiment of the present invention.

Referring to FIG. 10, a 16-symbol unequal signal constellation according to an embodiment of the present invention includes memories 1010 and 1030 and a processor 1020. At this time, the modulator shown in Fig. 10 may correspond to the modulator 15 shown in Fig.

The memory 1010 receives a codeword corresponding to an LDPC code with a code rate of 4/15.

At this time, the codeword may be an error-correction-coded LDPC codeword or an LDPC codeword interleaved with a codeword.

Processor 1020 maps the codeword to 16 symbols of unequal 16-symbol signal constellation in 4-bit units.

At this time, the processor 1020 may adjust at least one of the amplitude and the phase of the carrier in accordance with the symbol mapping.

At this time, the 16 symbols are non-uniform in distance between the symbols, and are symmetric with respect to the first group of four symbols of the first quadrant, the four symbols of the first group and the imaginary axis A second group of four symbols, a fourth group of four symbols symmetric with respect to the fourth symbol of the first group and four symbols of the first group, and a third group of four symbols symmetric with respect to the origin, Group.

In this case, a vector corresponding to four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group is w and four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) is -conj (w) (conj (w) is a function that outputs the complex conjugate of all elements of w), and the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) is-w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group may be conj (w) .

In this case, two of the four symbols of the first group may be symmetric with respect to the amplitude of the real component and the amplitude of the imaginary component.

In this case, the four symbols of the first group are w ₀ , w ₁ , w ₂ and w ₃ , and | real (w ₀ ) | _{= | Imaginary (w 1) |} (real (i) is a function that outputs a real component of the i, imaginary (i) is a function for outputting an imaginary component of the i, i is an arbitrary complex number) and, | real (w ₁ ) | = | imaginary (w ₀ ) |, and | real (w ₂ ) | = | imaginary (w ₃ ) |, and real (w ₃ ) | = | imaginary (w ₂ ) |.

At this time, the 16 symbols can be defined as shown in Table 4 below.

The memory 1030 may store additional information required for the operation of the processor 1020. [ For example, memory 1030 may store carrier frequency, amplitude, and the like.

The memory 1010 and the memory 1030 may correspond to various hardware for storing a set of bits and may include data structures such as an array, a list, a stack, a queue, data structure.

At this time, the memory 1010 and the memory 1030 may not correspond to physically separate devices, but may physically correspond to different addresses of one device. That is, the memory 1010 and the memory 1030 may not be physically separated but may be logically separated.

11 is a flowchart illustrating a modulation method using a 16-symbol unequal signal constellation according to an embodiment of the present invention.

11, a modulation method using a 16-symbol unequal signal constellation according to an embodiment of the present invention includes a codeword corresponding to an LDPC code with a coding rate of 4/15 (S1110).

At this time, the codeword may be an error-correction-coded LDPC codeword or an LDPC codeword interleaved with a codeword. That is, the step S1110 may receive the codeword immediately in the LDPC encoder or may receive the codeword through the bit interleaver in the middle.

Further, in the modulation method using the 16-symbol unequal signal constellation according to an embodiment of the present invention, the codeword is mapped to 16 symbols of the unequal 16-symbol signal constellation in units of 4 bits (S1120).

At this time, the 16 symbols are non-uniform in distance between the symbols, and are symmetric with respect to the first group of four symbols of the first quadrant, the four symbols of the first group and the imaginary axis A second group of four symbols, a fourth group of four symbols symmetric with respect to the fourth symbol of the first group and four symbols of the first group, and a third group of four symbols symmetric with respect to the origin, Group.

In this case, a vector corresponding to four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group is w and four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) is -conj (w) (conj (w) is a function that outputs the complex conjugate of all elements of w), and the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) is-w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group may be conj (w) .

In this case, two of the four symbols of the first group may be symmetric with respect to the amplitude of the real component and the amplitude of the imaginary component.

In this case, the four symbols of the first group are w ₀ , w ₁ , w ₂ and w ₃ , and | real (w ₀ ) | _{= | Imaginary (w 1) |} (real (i) is a function that outputs a real component of the i, imaginary (i) is a function for outputting an imaginary component of the i, i is an arbitrary complex number) and, | real (w ₁ ) | = | imaginary (w ₀ ) |, and | real (w ₂ ) | = | imaginary (w ₃ ) |, and real (w ₃ ) | = | imaginary (w ₂ ) |.

At this time, the 16 symbols can be defined as shown in Table 4 below.

In addition, the modulation method using the 16-symbol unequal signal constellation according to an embodiment of the present invention adjusts at least one of the amplitude and the phase of the carrier according to the mapping (S1130).

The error correction encoder 13 shown in FIG. 1 may be implemented with the structure shown in FIG.

That is, the error correction encoder may include memories and a processor. In this case, the first memory may be a memory for storing an LDPC codeword having a length of 16200 and a coding rate of 4/15, and the second memory may be a memory initialized to zero.

The memories may correspond to lambda _i (i = 0, 1, ..., N-1) and _Pj (j = 0, 1, ..., M ₁ + M ₂ -1), respectively.

The processor may accumulate the memory using a sequence corresponding to a parity check matrix to generate the LDPC codeword corresponding to the information bits.

At this time, the accumulation may be performed at parity bit addresses that are updated using the sequence of the table.

In this case, the LDPC codeword includes a systematic part (λ ₀ , λ ₁ ,..., Λ _{K -1} ) corresponding to the information bits and having a length of 4320 (= K) The first parity part (? _{K ,? K + 1} , ...,? _{K + M1-1} ) corresponding to the diagonal diagonal matrix and having a length of 1080 (= M ₁ = g) It corresponds to the matrix and has a length that can contain 10800 (M = ₂₎ of the second parity part _{(λ K + M1, λ K} + M1 + 1, ..., λ K + M1 + M2- 1).

In this case, a value obtained by dividing 4320, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, and 1080, which is the length (M ₁ ) of the first parity part, (4320/360 + 1080/360 = 15) rows.

As described above, the sequence may be represented by the table.

At this time, the second memory may have a size corresponding to the sum (M ₁ + M ₂ ) of the length (M ₁ ) of the first parity part and the length (M ₂ ) of the second parity part.

At this time, the parity bit addresses may be updated based on the result of comparing each of the previous parity bit addresses (x) shown in each row of the series with the length (M ₁ ) of the first parity part.

That is, the parity bit addresses can be updated by Equation (5). Where m is an integer greater than 0 and less than L, and L is the CPM size of the parity check matrix, Q ₁ is M ₁ / L, and M ₁ is the first parity part Q ₂ may be M ₂ / L, and M ₂ may be the size of the second parity part.

At this time, the accumulation may be performed while changing the rows of the sequence with the CPM size L = 360 units of the parity check matrix as described above.

In this case, the first parity part (? _{K ,? K + 1} , ...,? _{K + M1-1} ) has parity interleaving using the first memory and the second memory, (parity interleaving).

At this time, the second parity part _{(M1 + K} λ, λ _{K + M1 + 1,} ..., λ _{K + M1 + M2- 1)} includes a first parity part (λ _K, as described through the equation (8), after the generation of _{λ K + 1, ..., λ} K + M1-1) has completed the first parity part _{(λ K, λ K + 1} , ..., λ K + M1-1) and the sequence And performing parity interleaving using the first memory and the second memory after the accumulation performed using the first memory and the second memory is completed.

The bit interleaver 14 shown in FIG. 1 may also be implemented with the structure shown in FIG.

That is, the first memory may store an LDPC codeword having a length of 16200 and a coding rate of 4/15. The processor may generate the interleaved codeword by interleaving the LDPC codeword in a bit group unit corresponding to a parallel factor of the LDPC codeword. At this time, the parallel factor may be 360. At this time, the bit group may include 360 bits. At this time, the LDPC codeword can be divided into 45 bit groups as shown in Equation (9).

In this case, the interleaving can be performed using Equation (10) using a permutation order.

In this case, the permutation order may correspond to the interleaving sequence represented by Equation (11).

The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

In this case, the modulator may be a symbol mapping apparatus for performing NUC (Non-Uniform Constellation) symbol mapping as described with reference to FIG.

As described above, the modulator, the modulation method, and the BICM device using the unequal 16-symbol signal constellation according to the present invention are not limited to the configuration and method of the embodiments described above, All or some of the embodiments may be selectively combined so that various modifications can be made.

1010, 1030: memory
1020: Processor

Claims (6)

A memory for receiving a codeword corresponding to an LDPC code having a code rate of 4/15; And
A processor for mapping the codeword to 16 symbols of unequal 16-symbol signal constellation in 4-bit units;
Symbol signal constellation based on the unequal 16-symbol signal constellation. The method according to claim 1,
The sixteen symbols are non-uniform in distance between symbols, and are divided into a first group of four symbols in the first quadrant, four symbols in the first group and four symbols symmetrical in terms of the imaginary axis A fourth group of four symbols symmetric with respect to the fourth symbol of the first group and four symbols of the first group and a fourth group symmetric with respect to the real axis with respect to the fourth symbol of the first group, Symbol signal constellation. ≪ RTI ID = 0.0 > 16. < / RTI > The method of claim 2,
The vector corresponding to the four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group is w and the four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) is -conj (w) (conj (w) is a function that outputs the complex conjugate of all elements of w), and the four symbols of the third group (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) is-w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group is conj (w) Modulator using uniform 16-symbol signal constellation. The method of claim 3,
Wherein two of the four symbols of the first group are symmetric with respect to amplitude and imaginary component of the real component and the imaginary component, respectively. The method of claim 4,
The four symbols of the first group are w ₀ , w ₁ , w ₂ and w ₃ , and | real (w ₀ ) | _{= | Imaginary (w 1) |} (real (i) is a function that outputs a real component of the i, imaginary (i) is a function for outputting an imaginary component of the i, i is an arbitrary complex number) and, | real (w ₁ ) | = | imaginary (w ₀ ) |, and | real (w ₂ ) | = | imaginary (w ₃ ) |, and real (w ₃ ) | = | imaginary (w ₂ ) |. The modulator using the unequal 16-symbol signal constellation. The method of claim 5,
Wherein the 16 symbols are defined as shown in the following table.
[table]

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