KR20150094726A - Methods for achieving metal fill in small features - Google Patents

Abstract

A method of electroplating on a workpiece having a 30 nm-lower feature typically comprises applying chemistry to the workpiece, wherein the chemistry comprises about 55 ppm to about 250 ppm And a metal cation solute species, and applying an electrical waveform for less than about 5 seconds, wherein the electric waveform comprises a ramping of the current ramping Period, and a period of pulse plating.

Description

[0001] METHODS FOR ACHIEVING METAL FILL IN SMALL FEATURES [0002]

Cross-reference to related application

The present application claims priority to U. S. Provisional Application No. 61/737044, filed December 13, 2012, the disclosure of which is hereby expressly incorporated by reference in its entirety.

An integrated circuit is an interconnected ensemble of devices formed in a semiconductor material and in a dielectric material that is placed on the surface of the semiconductor material. Devices that may be formed in a semiconductor include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices that can be formed in the dielectric include thin film resistors and capacitors. The devices are interconnected by conductor paths formed in the dielectric. Typically, two or more levels of conductive paths, in which successive levels are separated by a dielectric layer, are employed as interconnection. In current practice, copper and silicon oxides are typically used for conductors and dielectrics, respectively.

Deposits in copper interconnects typically include a dielectric layer, a barrier layer, a seed layer, a copper fill, and a copper cap. Conventional electrochemical deposition (ECD) for copper fill and cap is performed in the feature using acid plating chemistry. Electrochemical deposition of copper is known to be the most cost effective way to deposit a metallization layer. In addition to being economically viable, such deposition techniques provide a substantially bottom-up (e.g., non-conformal) copper fill that is mechanically and electrically compatible with interconnect structures.

Conventional ECD copper-acid plated chemistries can be prepared, for example, from copper sulfate, sulfuric acid, hydrochloric acid, and organic additives (e.g., accelerators, suppressors, and levelers). The additives may be added to the surface of the substrate through their adsorptive and desorptive properties and through a competitive reaction by suppressing the plating on the sidewalls of the feature, Through the voids to drive the void-free bottom-up filling at the feature.

Constant downscaling of interconnect features presents new challenges because the characteristic dimensions (e.g., feature width and aspect ratio) typically inhibit and modify the reaction characteristics of the additives used. In this regard, the 30 nm-bottom features (sub-30 nm features) used for the copper interconnects have a small volume and are small enough to fill the features within the first few seconds of plating in conventional ECD copper acid plating chemistries Requires copper atoms. This is a shorter period of time than the time period required for adsorption and desorption kinetics of bath additives to propel conventional bottom-up charging.

Thus, in small features (e.g., 30 nm-bottom features), conventional ECD charging can result in lower quality interconnects due to the presence of voids. As an example of the type of air gap formed using conventional ECD deposition, the aperture of the feature can be pinch off. Many other types of voids can also be caused by using conventional ECD copper fill processes at small features. Such voids and other intrinsic properties of deposits formed using conventional ECD copper charging can increase the resistance of the interconnect, thereby slowing the device and reducing the reliability of the copper interconnect.

Thus, there is a need for methods of electrochemical deposition to fill 30 nm-below features from the bottom, leaving a reduced number of void regions. Embodiments of the present disclosure relate to meeting these and other needs.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features of the subject matter claimed, nor is it intended to be used to aid in determining the scope of the subject matter claimed.

According to one embodiment of the present disclosure, a method is provided for electroplating on a workpiece having a 30 nm-lower feature. The method generally comprises applying chemistry to the workpiece, wherein the chemistry has a halide ion concentration in the range of about 55 ppm to about 250 ppm, and metal cation solute species And applying an electric waveform for less than about 5 seconds, wherein the electric waveform comprises a period of ramping of the current, and a duration of the pulse plating.

According to another embodiment of the present disclosure, a method of electroplating on a workpiece having a 30 nm-lower feature is provided. The method generally comprises the steps of applying a chemistry to the workpiece, wherein the chemistry comprises a halide ion concentration in the range of about 55 ppm to about 250 ppm, and metal cation solute species, and applying an electric waveform Wherein the electric waveform includes a period of ramping of the current for a period of less than 0.2 seconds and a period of pulse plating of less than about 2 seconds.

According to another embodiment of the present disclosure, a method of electroplating on a workpiece having a 30 nm-lower feature is provided. The method generally comprises applying chemistries to the workpiece, wherein the chemistry comprises halide ion concentrations in the range of about 120 ppm to about 150 ppm, and metal cationic solute species, and applying the electric waveform Wherein the electric waveform includes a period of ramping of the current for a period of less than 0.2 seconds and a period of pulse plating of less than about 2 seconds.

According to another embodiment of the present disclosure, in any of the methods described herein, the metal cation may be copper.

According to another embodiment of the present disclosure, in any of the methods described herein, the halide ion concentration may range from about 120 ppm to about 150 ppm.

According to another embodiment of the present disclosure, in any of the methods described herein, the halide ion may be selected from the group consisting of chloride, bromide, and iodide ions, and combinations thereof .

According to another embodiment of the present disclosure, in any of the methods described herein, the ramping of the current may be performed by linear continuous ramping, non-linear continuous ramping, or pulsed ramping May be selected from the group consisting of.

According to another embodiment of the present disclosure, in any of the methods described herein, the ramping period may be less than about 0.1 seconds (100 milliseconds), less than about 0.2 seconds (200 milliseconds) And less than 0.4 seconds (400 milliseconds).

According to another embodiment of the present disclosure, in any of the methods described herein, the ramping period may begin after a delay period.

According to another embodiment of the present disclosure, in any of the methods described herein, ramping is performed at a current level in the range of about 1 amperes to about 15 amps, a current in the range of about 7 amps to about 15 amps A current level in the range of about 18 amps to about 25 amps, and a current level in the range of about 7 amps to about 25 amps.

According to another embodiment of the present disclosure, in any of the methods described herein, the pulsing period may be for a period of less than about 2 seconds (2000 milliseconds).

According to another embodiment of the present disclosure, in any of the methods described herein, the pulsing period may have a duty cycle in the range of about 20% to about 75%.

According to another embodiment of the present disclosure, in any of the methods described herein, the pulsing period may have a duty cycle of about 50%.

According to another embodiment of the present disclosure, in any of the methods described herein, the individual pulses are applied to the substrate in a period of from about 1 millisecond to about 100 milliseconds, from about 5 milliseconds to about 100 milliseconds, Lt; / RTI > to about 50 milliseconds.

According to another embodiment of the present disclosure, in any of the methods described herein, the on current pulses have a current level in the range of about 1 to about 30 amperes and a current level in the range of about 4.5 to about 30 amperes RTI ID = 0.0 > current < / RTI >

According to another embodiment of the present disclosure, in any of the methods described herein, the off current pulses are applied to the substrate at a current of between about 0 amperes and about 20 amperes, between about 0 amperes and about 10 amperes, RTI ID = 0.0 > 5 < / RTI > amps.

According to another embodiment of the present disclosure, in any of the methods described herein, the waveform may further include a triggered hot entry.

The foregoing aspects and many of the attendant advantages of the present disclosure will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings.
Figure 1 is an exemplary current waveform for use in a copper electrochemical deposition plating process, according to one embodiment of the present disclosure.
Figure 2 is an exemplary current waveform for use in a copper electrochemical deposition plating process, in accordance with one embodiment of the present disclosure.
3 is a cross-sectional SEM image of a workpiece after using a copper electrochemical deposition plating process, according to one embodiment of the present disclosure;
Figure 4 is a void count comparison for various test substrates undergoing various test conditions prepared according to embodiments of the present disclosure.

Embodiments of the present disclosure are directed to processing assemblies for processing workpieces, such as semiconductor wafers, devices, or workpieces, and methods of processing the workpieces. The term workpiece, wafer, or semiconductor wafer refers to semiconductor wafers and other substrates or wafers, glass, and optical or memory media, MEMS substrates, or micro-electrical, micro- Means any flat media or article comprising any other workpiece having electro-mechanical devices.

The processes described herein will be used for metal or metal alloy deposition in features of workpieces, including trenches and vias. In one embodiment of the present disclosure, the process can be used in small features, such as features having a feature diameter of less than 30 nm, for example. However, it should be appreciated that the processes described herein are applicable to any feature size. The dimension sizes discussed herein are post-etch feature dimensions at the top opening of the feature. The processes described herein can be applied to various types of metal and metal alloy deposition, such as, for example, in Damascene applications.

It should be appreciated that the descriptive terms "micro-feature workpiece" and "workpiece" as used herein include all structures and layers previously deposited and formed at a given point in processing . Embodiments of the present disclosure relate to methods for non-void top-down filling in small features. According to one embodiment of the present disclosure, a method includes providing a chemical-physical driving force to encourage a no-void bottom-up charging at small features. Suitable chemical-physical thrusts include increasing the halide ion concentration in the bath and applying unique entries and early plating electric waveforms at the beginning of the plating process .

In the embodiments of the present disclosure, the small features described herein may be characterized by features such as 30 nm-lower features, 20 nm-lower features, features in the range of 10 to 30 nm, May be features.

The term "void-free charging" is defined in the art as a feature with reduced void filling so as not to significantly increase the resistance of the interconnect, or significantly affect the yield or performance of the interconnect. Although the features may include a population of voids whether generated during plating or during subsequent processing conditions, these voids are generally undetectable in "void-free filling" . In this regard, voids can not be detected, for example when visually inspected, using an SEM image as shown in FIG. Moreover, the voids can have comparable performance values, such as yield, resistance, and resistance, when compared to larger features determined to be acceptable in the industry for their performance achievements, such as a 45 nm feature, , And when it achieves reliability values, it can not be detected.

The plating bath may include, for example, metal ions (e.g., copper ions in the form of copper sulfate), acid concentration (e.g., sulfuric acid), halide concentration (e.g., chloride ion concentration in the form of hydrochloric acid) Such as, for example, accelerators, inhibitors, and levelers). It should be appreciated, however, that the methods described herein can be applied to other types of chemistries than metals other than copper and those having an acid concentration, such as sulfuric acid.

According to embodiments of the present disclosure, the halide ion concentration in the plating bath can be increased by, for example, an increased chloride ion, bromide ion, or iodide ion concentration, as well as other suitable halide ions, By the use of combinations.

As a non-limiting example of a suitable halide, increased chloride ion concentrations may be used in the plating bath. The chloride concentration in conventional plating baths is typically about 50 ppm. According to embodiments of the present disclosure, the chloride concentration may range from about 1.1 to about 5 times that typical concentration. In one embodiment of the present disclosure, the chloride concentration can be about three times the typical chloride concentration in conventional plating baths. In one embodiment of the present disclosure, the chloride concentration may be in the range of about 120 to 150 ppm. In one embodiment of the present disclosure, the chloride concentration may range from about 55 ppm to about 250 ppm.

The plating baths according to embodiments of the present disclosure may further include optional organic additives that may be present at various concentrations depending on the operational conditions of the plating baths. In this regard, organic additives (e.g., accelerators, inhibitors, and levelers) in conventional ECD copper acid plating chemistries are generally effective in plating chemistries for small features, in accordance with embodiments of the present disclosure , Some or all of these additives may not be needed and therefore may be removed from the plating bath. However, if the larger features are being plated using the same chemistry bath as the smaller features, as will be described in greater detail below, in order to facilitate no-pore plating in larger features, Should include such additives.

The plating bath may also include complexing agents designed to facilitate copper deposition without requiring some or all of the organic additives. As a non-limiting example, a suitable copper complexing agent may include a chelator such as ethylenediaminetetraacetic acid (EDTA). Other complexing agents known by those skilled in the art may also be employed.

In combination with the chemical effects of increased halide concentration in the plating bath, the use of electrical waveforms adds physical components to the chemistry plating bath. In this regard, the waveform adds kinetic energy to locations within the features that would not be affected by chemistry alone. Because the feature size is very small, and is roughly on the same scale as the plating additive molecules or in the same order as the plating additive molecules, the plating chemistries will behave as expected in larger features do not behave. Thus, the use of a waveform physically manipulates the behavior of the molecules during plating. The waveform may be a current waveform or a potential waveform.

While not wishing to be bound by theory, the waveform is considered by the inventors to reduce the time delays of the effectiveness of additives in small features. Increased halide concentration is believed to alleviate any negative effects of the additives in the small features, since the additives are generally included for use in larger features and are not particularly useful in smaller features. For example, increased halide concentrations can alleviate the negative effects of accelerated inhibitors on the activation time of the inhibitor by the use of electric waveforms in small features.

According to one embodiment of the present disclosure, a suitable current waveform includes a short time period (less than 5 seconds) of the hot entry being triggered and the current ramped, followed by pulse plating. In the hot entry to be triggered, the current is an open circuit until the wafer is brought into contact with the chemistry, until the circuit is closed to initiate the pre-set waveform start.

The ramping of the current is used to maintain a constant current density in the workpiece during the wetting stage, since the entire workpiece is not wet at once. Ramping of the current can be performed in one or more ways. With reference to the non-limiting example in FIG. 1, ramping is steady ramping. In this example, it takes about 150 milliseconds (about 0 to about 150 milliseconds) for the entire workpiece to immerse in the chemistry. With reference to the non-limiting example in Figure 2, regular ramping occurs after a short delay and then remains constant. The length of the delay may depend on when the power supply is triggered. In this example, regular ramping occurs from about 0.15 seconds to about 0.40 seconds, and then remains constant from about 0.40 seconds to about 0.85 seconds.

It should be appreciated that the ramping stage may be linear continuous ramping, non-linear continuous ramping, or pulsed ramping. According to one embodiment of the present disclosure, ramping can achieve a current level in the range of about 1 ampere to about 15 amperes. According to one embodiment of the present disclosure, ramping can achieve a current level in the range of about 7 amps to about 15 amps. According to another embodiment of the present disclosure, ramping can achieve a current level in the range of about 18 amps to about 25 amps. According to another embodiment of the present disclosure, ramping can achieve a current level in the range of about 7 amps to about 25 amps.

According to embodiments of the present disclosure, the ramping period may be less than 0.1 seconds, less than 0.2 seconds, less than 0.4 seconds, or less than 1.0 seconds.

While not wishing to be bound by theory, it is believed by the inventors that a pulsed waveform can be used to account for the transient effects of current when pulsing is turned off after a ramping stage. In this regard, it is believed that the pulsed waveform helps to control voltage overshoots affecting the chemistry near the wafer.

The pulsing stage is calculated based on the charge time, topography, and architecture of the features. The inventors have found that pulsing is advantageous in reducing voids in very small features (e.g., 30 nm-lower features). However, in that pulsing tends to produce a counter plating effect that results in conformal deposition in contrast to the preferred top-down (or non-conformal) charging (e.g., by moving the additives away from the plating surface) Pulsing has a negative effect on larger features (see, for example, the experimental results described in Example 4 below). Conformal deposition is undesirable in larger features due to the tendency to create pinch-off. Thus, the pulsing stage is limited to the time period during which the 30 nm-bottom features are charged, and is terminated before the negative results are experienced in larger features.

According to one embodiment of the present disclosure, the pulsing stage may extend for up to 2 seconds (2000 milliseconds). According to one embodiment of the present disclosure, the pulsing stage may last up to 0.5 seconds (500 milliseconds). According to embodiments of the present disclosure, the pulses may range in length from greater than about 1 millisecond to about 100 milliseconds. In one embodiment, the pulses may range in length from about 5 milliseconds to about 100 milliseconds. In one embodiment, the pulses may range in length from about 5 milliseconds to about 50 milliseconds. In the illustrated embodiments of Figures 1 and 2, the pulses are about 10 milliseconds in length. (Note that due to the limited resolution for the timescale shown, the pulsing scheme is represented as a block from 0.85 seconds to 3.1 seconds in FIG. 2). The " long "pulsing scheme non- A limiting example may include, for example, a 15 second pulsing period where pulses occur every about 10 milliseconds. The pulse length can be as long as four seconds per pulse.

In one embodiment of the present disclosure, the current "on" or "high" pulses may range from about 1 to about 30 amperes. In other embodiments of the present disclosure, the current "on" or "high" pulses may range from about 4.5 to about 30 amperes. Current "off" or " low "pulses may be in the range of about 0 to about 20 amperes, about 0 to about 10 amperes, and about 0 to about 5 amperes.

The duty cycle of the pulsing stage may be in the range of about 20% to about 70%, using a maximum duty cycle of 75%. In one embodiment of the present disclosure, the duty cycle is about 50%.

The combination of the increased halide ion concentration and the specific pattern of the electric waveform is generally considered by those skilled in the art to be counterproductive in electrochemical deposition processes. In this regard, increased halide ion concentrations are generally considered by those skilled in the art to accelerate electrochemical deposition in small features, while electric waveforms are generally considered by those skilled in the art to inhibit electrochemical deposition .

Although not wishing to be bound by theory, the inventors of the present application have found that the combination of increased halide ion concentration and a particular pattern of electrochemical waveforms, due to the specific timing of activities in small features, I think I provide the results. In a non-limiting example, within about the first 100 milliseconds of plating on a small feature, the presence of halide ions causes the deposition to accelerate. During this time period, the inhibitory additive present in the plating chemistry would not have reached the interior of the small feature, and thus is still not valid inside. However, the inhibiting additive can help inhibit deposition outside the features on the field.

As small features begin to fill during these time periods, waveforms can be applied to slow or inhibit deposition. The waveform may have a period of ramping to allow some deposition at the small feature by not completely inhibiting the acceleration caused by the increased halide concentration.

Within about the second 100 milliseconds of plating on the small features, the inhibiting additive present in the plating chemistry can begin to take effect in smaller features. The waveforms are added to the suppression effects to slow the deposition and reduce the possibility of voids in the features.

After about one second, the accelerating additives present in the plating chemistry begin to take effect. Thus, to control acceleration effects, pulse plating may be used.

As described in the following examples, no-void filling was achieved on a test substrate in an Applied Materials CFD3LM plating chamber and verified by SEM imaging. 30 nm-lower features on both internal and external wafers were successfully filled and verified using CMP-post defect inspection.

Example 1: Example waveform

An exemplary waveform for the first 350 milliseconds of plating is provided in FIG. 1 and represents current ramping in an entry for 150 milliseconds followed by 50 millisecond 50 percent duty cycle pulses. In Figure 1, pulsing is shown for about 0.2 seconds (200 milliseconds); However, the pulsing scheme can continue for a longer duration. In one non-limiting example, the pulsing scheme may last for 0.5 seconds (500 milliseconds).

Example 2: Example waveform

Another exemplary waveform for the first 4 seconds of plating is provided in FIG. 2, indicating that the current ramping begins at 0.15 seconds when the wafer is submerged in the plating solution. Due to the limited resolution of the time scale shown, in Fig. 2, 10 millisecond pulses are represented as "blocks" from 0.85 seconds to 3.1 seconds. In Figure 2, pulsing is shown slightly exceeding 2 seconds (2000 milliseconds).

Example 3: SEM image

Referring to FIG. 3, there is provided a plating waveform of FIG. 2 and Example 2, and a cross-sectional SEM image showing no-void gap filling with 120 ppm chloride in the plating solution.

Example 4: Relative void count results

Referring to FIG. 4, comparative void count results are provided for three different substrates, with three different substrates: substrate A, 20 nm bottom feature; Substrate B, 20 nm-lower feature; And substrate C, a 65 nm feature. Substrate A generally has smaller arrays for a more denser feature population. Substrate B also has smaller features, but has much larger arrays with less dense spacing of feature groups.

Each substrate was exposed to five different conditions, and five different conditions: (1) control conditions of 50 ppm chloride ion concentration and no pulse plating; (2) increased chloride conditions of 120 ppm chloride ion concentration; (3) increased chloride conditions of 120 ppm chloride ion concentration and, for example, pulse plating according to the scheme of Figure 1; (4) increased chloride conditions of 120 ppm chloride ion concentration, altered additive conditions to increase total bath inhibition, and "long" pulse steps (e.g., pulse plating using a step; And (5) increased chloride conditions of 120 ppm chloride ion concentration, the same conditions as in (4) above, altered additive conditions to increase total bath inhibition, and, for example, pulse plating according to the scheme of FIG. The void counts of these five conditions are graphically shown in Fig.

The results show that the void counts for substrate A and substrate B decrease as the chloride ion concentration in the plating bath increases, as can be seen by comparing the data for condition (1) control and the data for condition (2) . In addition, as can be seen by comparing the data for condition (2) with the data for condition (3), the void counts for substrate A and substrate B, together with the pulse plating scheme, Is decreased. As can be seen by comparing the data for conditions (1) and (2) with the data for condition (4), the void counts for substrate A and substrate B are shown as Bass B (increased chloride concentration, Additive conditions), but slightly increased compared to the void counts achieved under condition (3).

Comparing the data for condition (4) and the data for condition (5), the void count for substrate A is reduced and the void count for substrate B is increased. This change in data can be dependent on the differences in array size between substrate A and substrate B, as discussed above, and the effects of the length of the pulsing period on substrates with different array sizes .

For each particular substrate, the desired waveform can be optimized; Thus, in some cases, the long pulse step may be preferable to the shorter pulse step, and vice versa. In addition, for each particular substrate, the preferred bath additive concentration can be determined. Thus, the bath chemistry and waveforms can be optimized for each individual substrate.

As can be seen by comparing the data for conditions (3), (4) and (5), as pulsing (especially the "long" pulse step as used in condition (4) Voiding is increased in Substrate C (65 nm feature), indicating that pulsing does not improve bottom-up filling in larger features.

Although illustrative embodiments have been illustrated and described, it will be appreciated that various changes may be made in the exemplary embodiments thereof without departing from the scope and spirit of this disclosure.

Claims (17)

A method of electroplating on a workpiece having a 30 nm-sub feature (sub-30 nm feature)
(a) applying chemistry to the workpiece, the chemistry comprising halide ion concentrations in the range of about 55 ppm to about 250 ppm, and metal cation solute species Included -; And
(b) applying an electric waveform for less than about 5 seconds,
/ RTI >
The electrical waveform includes a period of ramping of the current, and a period of pulse plating.
Electroplating. The method according to claim 1,
Wherein the metal cation is copper,
Electroplating. The method according to claim 1,
Wherein the halide ion concentration is in the range of about 120 ppm to about 150 ppm,
Electroplating. The method according to claim 1,
Wherein the halide ion is selected from the group consisting of chloride, bromide, and iodide ions, and combinations thereof.
Electroplating. The method according to claim 1,
The ramping of the current is selected from the group consisting of linear continuous ramping, non-linear continuous ramping, or pulsed ramping.
Electroplating. The method according to claim 1,
Wherein the ramping period is for a period selected from the group consisting of less than about 0.1 seconds (less than 100 milliseconds), less than about 0.2 seconds (less than 200 milliseconds), and less than about 0.4 seconds (less than 400 milliseconds)
Electroplating. The method according to claim 1,
Wherein the ramping period begins after a delay period,
Electroplating. The method according to claim 1,
The ramping is performed at a current level in a range of about 1 amperes to about 15 amps, a current level in a range of about 7 amps to about 15 amps, a current level in a range of about 18 amps to about 25 amps, Lt; RTI ID = 0.0 > 25 amps, < / RTI >
Electroplating. The method according to claim 1,
The pulsing period is a period of time less than about 2 seconds (2000 milliseconds)
Electroplating. The method according to claim 1,
The pulsing period may have a duty cycle in the range of about 20% to about 75%
Electroplating. The method according to claim 1,
The pulsing period has a duty cycle of about 50%
Electroplating. The method according to claim 1,
The individual pulses may be extended for a pulse length selected from the group consisting of about 1 millisecond to about 100 milliseconds, about 5 milliseconds to about 100 milliseconds, and about 5 milliseconds to about 50 milliseconds,
Electroplating. The method according to claim 1,
The on current pulses are at a current level selected from the group consisting of a current level in the range of about 1 to about 30 amperes and a current level in the range of about 4.5 to about 30 amperes,
Electroplating. The method according to claim 1,
Off current pulses are at a current level in a range selected from the group consisting of about 0 amperes to about 20 amperes, about 0 amperes to about 10 amperes, and about 0 amperes to about 5 amperes,
Electroplating. The method according to claim 1,
Wherein the waveform further comprises a triggered hot entry,
Electroplating. A method of electroplating on a workpiece having a 30 nm-lower feature,
(a) applying chemistry to the workpiece, wherein the chemistry comprises halide ion concentrations in the range of about 55 ppm to about 250 ppm, and metal cationic solute species; And
(b) applying an electric waveform
/ RTI >
Wherein the electrical waveform comprises a period of ramping of the current for a period of less than 0.2 seconds and a period of pulse plating of less than about 2 seconds.
Electroplating. A method of electroplating on a workpiece having a 30 nm-lower feature,
(a) applying chemistry to the workpiece, wherein the chemistry comprises a halide ion concentration in the range of about 120 ppm to about 150 ppm, and metal cationic solute species; And
(b) applying an electric waveform
/ RTI >
Wherein the electrical waveform comprises a period of ramping of the current for a period of less than 0.2 seconds and a period of pulse plating of less than about 2 seconds.
Electroplating.

Images