KR20150091648A - Spread spectrum clock generator - Google Patents

Abstract

A spread spectrum clock generator according to an embodiment of the present invention includes: a delay cell array including N (N is a natural number) number of unit delay cells which generate two differential phases having complementary wave forms to generate 2N number of phase arrangements individually; and a digital phase calibrator generating a calibration signal, which is able to control a delay value of the unit delay cell.

Description

{SPREAD SPECTRUM CLOCK GENERATOR}

The present invention relates to a spread spectrum clock generator, and more particularly, to a spread spectrum clock generator capable of reducing EMI.

With the advent of Complementary Metal Oxide Semiconductor (CMOS) technology, many researches have been carried out to integrate analog circuits, radio frequency (RF) circuits and digital circuits into one chip as SOC (System-On-Chip) . As a result, advantages such as reduction of chip manufacturing cost due to reduction of external devices and improvement of analog / digital connectivity can be obtained. However, electromagnetic interference (EMI) radiated from highly integrated very large scale integrated circuit (VLSI) digital circuits has threatened the reliability of analog and RF circuit signal processing. Particularly, in a transceiver (TRX) system, EMI caused by a digital clock causes a problem of causing a high spurious tone and, as a result, it can not pass the strict regulation of the spectrum mask .

Various methods have been proposed to reduce EMI such as shielding and filtering. However, these methods can increase the cost of the chip by increasing the cost of additional external devices and fabrication. As an effective method, a spread spectrum clock generator (SSCG) capable of directly reducing the amount of EMI radiation is used. The SSCG functions to disperse the peak power concentrated on one frequency to the surrounding frequency by continuously modulating the frequency of the clock with time. This alleviates the concentrated EMI peak power radiated from the digital circuitry, reducing the coupling to the transceiver circuitry and consequently reducing the interference tone.

Various SSCG implementation methods have recently been reported. SSCG can be roughly divided into a method of modulating a frequency using a phase locked loop (PLL) and a direct phase modulation method using a delay cell.

Figure 1 illustrates clock generation in a delay cell based direct phase modulation SSCG. Delay Cell Based Direct Phase Modulation The SSCG generates a frequency by generating multiple discrete phased arrays and synthesizing the required clock edges. If the unit step (DELTA T) of the delay and the number of delays are specified and the combination of the output phases is adjusted, it is possible to modulate the waveform that increases / decreases with time. This direct phase modulation method does not require a PLL component such as a passive element loop filter or a VCO (Voltage Controlled Oscillator) in comparison with a PLL-based frequency modulation method, There are advantages. However, the above-described direct phase modulation method requires a continuous infinite phase arrangement, which limits the feasibility of such a method.

Accordingly, there is a need for a spread spectrum clock generator capable of always generating a robust and continuous phase irrespective of changes in PVT (Process, Voltage, Temperature) environment and operating conditions.

SUMMARY OF THE INVENTION The present invention has been made in response to the problems and needs of the prior art, and it is an object of the present invention to provide a spread spectrum clock capable of always generating a robust and continuous phase regardless of PVT (Process, Voltage, Temperature) Generator.

It is also an object of the present invention to provide a spread spectrum clock generator capable of reducing EMI.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the invention to the precise forms disclosed. Other objects, which will be apparent to those skilled in the art, It will be possible.

The spread spectrum clock generator according to the embodiment of the present invention includes N (N is a natural number) unit delay cells, each of which generates two differential phases having a complementary waveform to generate 2N phase arrays A delay cell array for generating a delay cell array; And a digital phase corrector for generating a calibration signal capable of adjusting a delay value of the unit delay cell.

Also, the delay cell array is arranged in m columns and n rows (m X n), and the direction of the unit delay cells is different in two adjacent rows among n rows, where m * n = N .

The apparatus may further include a multiplexer capable of selecting a phase output from the delay cell array according to a modulation code, the multiplexer comprising: a column decoder for activating one of the m columns; A row decoder for activating one of the n rows; And a differential switch for selecting one of the two differential phases output from the unit delay cell located at an intersection of the activated column and the row.

The unit delay cell includes: first and second nMOS transistors constituting a differential pair; First and second pMOS transistors constituting a differential latch load; And third and fourth pMOS transistors connected in parallel to the first and second pMOS transistors, respectively, wherein a drain terminal of each of the first and second pMOS transistors is connected to a drain terminal of each of the first and second nMOS transistors , The differential input to the unit delay cell is input to the gate terminal of the first and second nMOS transistors, respectively, and the delay value of the unit delay cell is input to the gate terminal of each of the third and fourth pMOS transistors . ≪ / RTI >

The two differential phases generated in the unit delay cell are adjacent to the unit delay cell among the N unit delay cells and are transmitted as a differential input of a subsequent unit delay cell in the traveling direction, The phase is input to the cascade buffer included in the unit delay cell, and the cascade buffer is turned on and off according to a row select signal from the row decoder for the row where the unit delay cell among the n rows is located .

The delay cell array includes a load buffer corresponding to each of the m columns, and the two differential phases from n unit delay cells included in each of the m columns are supplied to the corresponding column through the cascade buffer, Lt; / RTI >

The modulation profile generator may further generate a modulation code and transmit the modulation code to the multiplexer. The modulation profile generator may generate the modulation code corresponding to the hush-kiss modulation waveform using a slope modulation scheme.

The digital phase corrector may further include: a phase detector for receiving a first phase and a second phase generated from the delay cell array and generating an up signal and a down signal according to a phase difference; A lock detector for generating a hold signal when the time at which the up signal and the down signal are input simultaneously from the phase detector is maintained for a predetermined time; An up / down counter whose magnitude is increased, decreased and held in accordance with the up signal and the down signal from the phase detector and the hold signal; And a current source for generating a digitally controlled current according to an output signal according to the up / down counter.

The phase detector may generate the up signal if the first phase is greater than the second phase, the down signal if the first phase is smaller, and the up signal and the down signal if the phase difference is less than a predetermined value. Here, the first phase may be a first phase of the 2N phases, and the second phase may be a 2N phase of the 2N phases.

In addition, the digitally controlled current signal may be the calibration signal capable of adjusting the delay value of the unit delay cell.

According to the present invention, it is possible to provide a spread spectrum clock generator capable of always generating a robust and continuous phase regardless of PVT (Process, Voltage, Temperature) environment and operation condition change.

Also, according to the present invention, EMI can be reduced in a spread spectrum clock generator.

Figure 1 illustrates clock generation in a delay cell based direct phase modulation SSCG.
2 illustrates a schematic diagram of an SSCG according to an embodiment of the present invention.
FIG. 3 illustrates a structure of a delay cell array 100 in an SSCG according to an embodiment of the present invention.
4 illustrates a circuit diagram of a unit delay cell 110 according to an embodiment of the present invention.
5 illustrates a circuit diagram of a load buffer 130 according to an embodiment of the present invention.
6 illustrates a deglitch circuit 140 according to an embodiment of the present invention.
7 illustrates an operation waveform of the deglitch circuit 140 according to an embodiment of the present invention.
8 illustrates the operation principle of the digital phase corrector 200 according to an embodiment of the present invention.
9 illustrates a circuit diagram of a phase detector 210 and a lock detector 220 included in a digital phase corrector 200 according to an embodiment of the present invention.
10 illustrates a transfer function according to the phase detector 210 according to an embodiment of the present invention.
11 illustrates a circuit diagram of a current source 240 included in a digital phase corrector 200 according to an embodiment of the present invention.
12 illustrates a change in the magnitude of a clock generated in the SSCG 1000 according to an embodiment of the present invention in accordance with a modulation waveform.
FIG. 13 illustrates the principle of implementing a hush-kiss modulated waveform in a modulation profile generator 300 according to an embodiment of the present invention.
FIG. 14 illustrates a structure of a modulation profile controller 310 according to an embodiment of the present invention.
FIG. 15 is a table showing operation changes of the components in the modulation profile controller 310 according to the external input.
16 illustrates a simulation result showing a spread waveform change according to an output value of the spread mode controller 311 according to an embodiment of the present invention.
17 illustrates a simulation result showing a change in slope of a hush-kiss profile according to a change in offset and a unit step.
FIG. 18 illustrates a simulation result of oversampling using a delta sigma modulator (DSM) according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals and the same elements are denoted by the same reference numerals even though they are shown on different drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

2 illustrates a schematic diagram of an SSCG according to an embodiment of the present invention. 2, the SSCG 1000 according to the embodiment of the present invention includes a delay cell array 100 for generating a plurality of phases and a control voltage V _CTRL And a digital phase calibrator (DPC: Digital Phase Calibrator) 200 that ensures continuous phase alignment. In addition, the SSCG 1000 according to the embodiment of the present invention may further include a modulation profile generator (MPG) 300 for generating a digital modulation code (D _MOD ).

FIG. 3 illustrates a structure of a delay cell array 100 in an SSCG according to an embodiment of the present invention. In FIG. 3, the delay cell array 100 includes 128 unit delay cells 110 (D0 to D127: UDC: Unit Delay Cell) to generate 256 phases (P). Hereinafter, the unit delay cells will be collectively referred to, or each unit delay cell will be denoted by reference numeral 110.

A unit delay cell 110 (D) according to an embodiment of the present invention may have a differential input and a differential output. Each of the 128 unit delay cells D can generate two phases having complementary waveforms. For example, a unit delay cell D _N generates a phased array P _N and a phased array P _{N + 128} having a waveform complementary thereto. At this time, the phase P _N is continuously increased by the unit delay time (ΔT) when N increases from 0 to 127, and P _N and P _{N + 128} can have complementary waveforms.

As shown in FIG. 3, the 128 unit delay cells 110 D according to the embodiment of the present invention can be arranged in 16 columns X 8 rows (16 columns X 8 rows). Odd and even rows are arranged to have opposite directions of travel in order to minimize the delay deviation due to the layout occurring between the end of each row and the beginning of the next row. For example, in the first row, the unit delay cells D0 to D15 are arranged to advance in the right direction in Fig. 3, whereas in the second row, the unit delay cells D16 to D31 are arranged to proceed in the left direction. This arrangement can last up to the eighth row.

As shown in FIG. 2, the demultiplexer 120 may include a multiplexer 120 for selecting a phase output from the delay cell array 100 according to an embodiment of the present invention. The multiplexer 120 according to the embodiment of the present invention may receive the modulation code (D _MOD ) generated from the modulation profile generator 300 and select a phase output from the delay cell array 100. 3, the multiplexer 120 according to the embodiment of the present invention may be divided into a column decoder 121, a row decoder 122, and a differential switch 123.

The multiplexer 120 according to an embodiment of the present invention may be, for example, an 8-bit multiplexer. The column decoder 121 according to the embodiment of the present invention can receive and decode the lower 4 bits D _MOD <3: 0> of the 8-bit modulation code (D _MOD ) to activate one of the 16 columns. For example, the column decoder 121 transmits a signal of Y0 to Y15 to a load buffer 130 (LB: Load Buffer) of each column according to the value indicated by 4 bits of D _MOD <3: 0> The load buffer 130 corresponding to the corresponding value can be activated. Reference numeral 130 may be used to collectively refer to LB0 to LB15 or to refer to an individual load buffer.

The row decoder 122 according to the embodiment of the present invention receives and decodes D _MOD <6: 4>, which is three bits after the lower 4 bits of the 8-bit modulation code (D _MOD ), to activate one of the eight rows . For example, the row decoder 122 may output X0 to X7 according to the value indicated by 3 bits of D _MOD <6: 4> as a 3-8 decoder to activate a row corresponding to the value. According to the outputs of the column decoder 121 and the row decoder 121, one unit delay cell 100 (D) located at the intersection of the activated column and the row may be activated. The complementary differential phases P _N and P _{N + 128} generated in the finally activated one unit delay cell 100: D are supplied to the load buffer 130 (D) located in the same column as the corresponding unit delay cell 100: LB).

The differential switch 123 (shown in FIG. 5) according to the embodiment of the present invention receives D _MOD <7> which is the most significant bit of the 8-bit modulation code (D _MOD ) One of the two complementary differential phases transmitted can be selected. For example, one of the complementary differential phases (P _N and P _{N + 128} ) located in the load buffer 130 (LB) may be selected according to the bit value of D _MOD <7>.

When one of the 256 phases is selected as the output from the delay cell array 100 by the 8-bit modulation code (D _MOD ) according to the embodiment of the present invention, a phase between the phase before being swapped and the phase after being swapped A glitch may be generated due to the timing alignment of the pixels. As shown in FIG. 3, the delay cell array 100 according to the embodiment of the present invention may include a deglitch circuit (140). The deglitch circuit 140 according to an embodiment of the present invention may be configured to remove such glitches before outputting the clock signal CLK from the delay cell array 100 to the output f _SSC .

)이 입력으로서 각각 입력된다. 4 illustrates a circuit diagram of a unit delay cell 110 according to an embodiment of the present invention. The unit delay cell 110 according to the embodiment of the present invention may include first and second n-channel metal oxide semiconductor (NMOS) transistors 111 and 112 constituting a differential pair. The differential inputs IN and IN are connected to the gate terminals of the first and second nMOS transistors 111 and 112,

Are input as inputs, respectively.

The unit delay cell 110 according to the embodiment of the present invention may include first and second p-channel metal oxide semiconductor (pMOS) transistors 113 and 114 constituting a differential latch load . The drain terminal of each of the first and second pMOS transistors 113 and 114 is connected to the drain terminal of each of the first and second nMOS transistors 111 and 112. At this time, the gate terminal of the first pMOS transistor 113 is connected to the drain terminal of the second pMOS transistor 114, and the gate terminal of the second pMOS transistor 114 is connected to the drain terminal of the first pMOS transistor 113 .

)은 각각 제1 및 제2 nMOS 트랜지스터(111 및 112) 각각의 드레인단에서 생성될 수 있다. 이때, 차동 출력(OUT 및

)은 각각 다음 단위 딜레이 셀(110)의 입력으로서 연결됨과 동시에 제1캐스코드 버퍼(115 및 117) 및 제2캐스코드 버퍼(116 및 118)에 연결될 수 있다. 이때, 제1 및 제2 캐스코드 버퍼(115 내지 118)는 로우 디코더(122)로부터의 로우 선택 신호(X_N)에 따라 온/오프(on/off)될 수 있다. The differential outputs OUT and OUT of the unit delay cell 110 according to the embodiment of the present invention

May be generated at the drain ends of the first and second nMOS transistors 111 and 112, respectively. At this time, the differential outputs (OUT and

May be coupled to the first cascode buffers 115 and 117 and the second cascode buffers 116 and 118, respectively, while being coupled as inputs to the next unit delay cell 110, respectively. At this time, the first and second cascode buffers 115 to 118 may be turned on / off according to the row select signal X _N from the row decoder 122.

)이 인가되고 제5 nMOS 트랜지스터(117)의 게이트단에는 로우 선택 신호(X_N)가 인가될 수 있다. 이와 마찬가지로, 제2캐스코드 버퍼에서 제4 nMOS 트랜지스터(116)의 드레인단과 제6 nMOS 트랜지스터(118)의 소스단이 접속되어 있다. 제4 nMOS 트랜지스터(116)의 게이트단에는 단위 딜레이 셀(110)의 비반전 출력(OUT)이 인가되고 제6 nMOS 트랜지스터(118)의 게이트단에는 로우 선택 신호(X_N)가 인가될 수 있다. The drain terminal of the third nMOS transistor 115 and the source terminal of the fifth nMOS transistor 117 are connected in the first cascode buffer. The gate terminal of the third nMOS transistor 115 is connected to the inverted output of the unit delay cell 110

And a row select signal X _N may be applied to the gate terminal of the fifth nMOS transistor 117. Likewise, the drain terminal of the fourth nMOS transistor 116 and the source terminal of the sixth nMOS transistor 118 are connected in the second cascode buffer. The non-inverted output OUT of the unit delay cell 110 may be applied to the gate terminal of the fourth nMOS transistor 116 and the row select signal X _N may be applied to the gate terminal of the sixth nMOS transistor 118 .

This configuration has the advantage that the unit delay cell 110 drives the same load without changing the row select signal X _N , which is an external signal.

The unit delay cell 110 according to the embodiment of the present invention is connected to the first and second pMOS transistors 113 and 114 constituting the differential latch load in parallel in order to adjust the delay value of the corresponding unit delay cell 110 And a third pMOS transistor 113p and a fourth pMOS transistor 114p connected to each other. At this time, the phase correction of the delay cell array 100 can be performed by adjusting the control voltage V _CTRL applied to the gates of the third pMOS transistor 113p and the fourth pMOS transistor 114p. That is, when the control voltage VCTRL is changed, the current value flowing through the third pMOS transistor 113p and the fourth pMOS transistor 114p may be changed. The thus changed current value can control the gate-to-drain delay of the first nMOS transistor 111 and the second nMOS transistor 112.

4, the source terminals of the first to fourth nMOS transistors 111, 112, 115, and 116 of the unit delay cell 110 according to the embodiment of the present invention are connected to the ground, 1 to the fourth pMOS transistors 113, 114, 113p, and 114p may be connected to a power supply voltage.

5 illustrates a circuit diagram of a load buffer 130 according to an embodiment of the present invention. 5 illustrates a configuration of a load buffer 130 in which outputs of eight unit delay cells 110 included in the same column via a column decoder 121 are commonly connected as shown in FIG.

)을 입력으로 받는 차동 래치를 구성하는 제5 및 제6 pMOS 트랜지스터(131 및 132)를 포함할 수 있다. 도4에서 캐스코드 버퍼의 출력으로서 도5에 입력으로 인가되는 신호인 Z 및

는 전류 형태를 가지므로 이를 적절한 전압으로 바꿔주기 위한 로드로서 제5 및 제6 pMOS 트랜지스터(131 및 132)가 이용된다. 따라서, 제5 및 제6 pMOS 트랜지스터(131 및 132)는 출력으로서 전압 형태의 차동 위상(Z 및

)을 생성할 수 있다. 본 발명의 실시예에 따른 로드 버퍼(130)에서 제5 pMOS 트랜지스터(131)의 게이트단은 제6 pMOS 트랜지스터(132)의 드레인단에 접속되고 제6 pMOS 트랜지스터(132)의 게이트단은 제5 pMOS 트랜지스터(131)의 드레인단에 접속된다. The load buffer 130 according to the embodiment of the present invention includes the cascode buffer outputs (Z and C) included in the eight unit delay cells 110 located in the same column,

And the fifth and sixth pMOS transistors 131 and 132 constituting a differential latch receiving the input signal as an input. Z, which is the input to the input in Figure 5 as the output of the cascode buffer in Figure 4, and

The fifth and sixth pMOS transistors 131 and 132 are used as a load for changing the voltage to an appropriate voltage. Thus, the fifth and sixth pMOS transistors 131 and 132 output differential phases (Z and &lt; RTI ID = 0.0 &gt;

Can be generated. The gate terminal of the fifth pMOS transistor 131 in the load buffer 130 according to the embodiment of the present invention is connected to the drain terminal of the sixth pMOS transistor 132 and the gate terminal of the sixth pMOS transistor 132 is connected to the drain terminal of the fifth and is connected to the drain terminal of the pMOS transistor 131.

The load buffer 130 according to the embodiment of the present invention may further include a seventh pMOS transistor 133 and an eighth pMOS transistor 134 connected in parallel to the fifth and sixth pMOS transistors 131 and 132, have. At this time, the gate terminal of the seventh pMOS transistor 133 may be commonly connected to the drain terminal of the fifth and seventh pMOS transistors 131 and 133. The gate terminal of the eighth pMOS transistor 134 may be commonly connected to the drain terminal of the sixth and eighth pMOS transistors 132 and 134. As such, the seventh pMOS transistor 133 and the eighth pMOS transistor 134 may be configured as a diode connected load to operate as a resistor. The seventh pMOS transistor 133 and the eighth pMOS transistor 134 may assist the operation of the fifth and sixth PMOS transistors 131 and 132 by generating a continuous current path.

) 중 하나가 출력될 수 있다. 3, only one of the 16 load buffers 130 (LB0 to LB15) may be connected to the output of the delay cell array 100 through the switch 135 according to the column select signals Y0 to Y15 of the column decoder 121 . 5, the differential switch 123 selects two differential phases (Z and D) according to the value of the most significant bit (D _MOD < 7 &gt;) of the modulation code

) May be output.

6 illustrates a deglitch circuit 140 according to an embodiment of the present invention. If swapping occurs momentarily from one phase to another according to the modulation code (D _MOD ), unwanted glitches can be generated depending on the phase and timing of the swap signal. The deglitch circuit 140 according to an embodiment of the present invention can be designed to prevent such glitches. 6, the diglit circuit 140 according to the embodiment of the present invention includes a D flip flop 141, a delay unit 142, and an inverter 143 .

7 illustrates an operation waveform of the deglitch circuit 140 according to an embodiment of the present invention. The operation of the deglitch circuit 140 according to the embodiment of the present invention will be described with reference to FIG. 7 illustrates a case where a swapped signal such as P _B is generated by swapping a delay signal to the P _A signal.

D flip-flop according to an embodiment of the invention 141, a data signal (f _IN) is a delay unit 142, a rough delay data signal _{(IN f, D)} is input as a clock (CLK). At this time, it is preferable that the delay amount in the delay section 142 is longer than the time in which glitches can occur. The inverted data signal in which the data signal f _IN is inverted through the inverter 143 is input to the reset terminal R of the D flip-flop 141. By configuring the deglitch circuit 140 as described above, the data signal f _IN is sampled at the rising edge of the delay data signals f _{IN and D} , and the data signal f _IN is lowered The D flip flop 141 is reset at the falling edge. Thus, the deglitch circuit 140 can effectively remove the glitch as in the output signal (f _OUT ) waveform of FIG.

8 illustrates the operation principle of the digital phase corrector 200 according to an embodiment of the present invention. The Nth unit delay cell 100 according to the embodiment of the present invention may be designed to generate the differential complementary phases P _N and P _{N + 128} , so that the incremental delay through the ideal 127 unit delay cells is D _{i, 0} to D _{i, 256} c. D _{i, 0} is the case without delay and can be incremented up to D _{i, 256} through 127 unit delay cells. At this time, in ideal cases _, the delay difference between D _{i, 256} and D _{i, 0} should be 1 / f _CLK (ideal case). In an actual situation, the incremental delay through 127 unit delay cells can be expressed as D _p.0 to D _{p, 256} . D _p.0 is the case without delay and can be incremented by D _{p, 256} through 127 unit delay cells. When the ΔT by incrementally delay occurs in the real world, D _p, the delay difference between ₂₅₆ and the D _p.0 may be represented by a 256 X ΔT (practical case). At this time, the corrected incremental delay (t _CAL ) should be satisfied by the equation (1) so that the actual case can be corrected to the ideal case as follows.

_{D i, 256 -D i, 0} = D p, 256 - D p.0

1 / f _CLK = 256 * (t _CAL )

t _CAL = 1 / (256 * f _CLK ) Equation (1)

Therefore, the digital phase corrector 200 according to the embodiment of the present invention can correct the actually generated phase to an ideal case by changing the actual incremental delay value? T to the t _CAL value. In Figure 8, D _C.0 , D _{C, 1 ...} represents the incremental delay after being calibrated through the digital phase corrector 200 of the present invention.

Calibration of the digital phase corrector 200 according to the embodiment of the present invention adjusts the delay of each unit delay cell 110 so that the 128th phase is divided into a half period of the input clock having a duty cycle of 50% Can be made equal.

Although there are various methods of calibrating? T to t _CAL , the spread spectrum clock generator 1000 according to the embodiment of the present invention can perform calibration using an up / down counter 230 that is simple and can be implemented with low power have. The digital phase corrector 200 according to the embodiment of the present invention directly compares P ₀ and P ₂₅₆ through the phase detector 210 and calculates the difference between the output of the phase comparator 210 and the output of the up / .

The output of the up / down counter 230 according to an embodiment of the present invention is applied to a digitally controlled current source (DCCS) 240 to adjust the control voltage of the unit delay cell 110, . Accordingly, ΔT is sufficiently close to the t _CAL When the phase detector 210 is the bias voltage of the lock (lock) by the hold (hold) a value with the export and the up / down counter 230, the signal unit of the delay cell 110 Can be fixed. This will be described in detail with reference to FIG.

As can be seen from Equation (1), the digital phase corrector 200 according to the embodiment of the present invention compares the 256th phase, so that the deviation of DELTA T and t _CAL is 256 (8-bit) times amplified. Thus, the digital phase corrector 200 is required to have an accuracy of at least 8 bits. Therefore, the digital phase corrector 200 according to the embodiment of the present invention can be designed to have an accuracy of 8 bits, which is the minimum requirement in consideration of circuit complexity and power consumption.

2, a digital phase corrector 200 according to an embodiment of the present invention includes a phase detector 210, a lock detector 220, an up / down counter 230, and a current source 240 Lt; / RTI &gt; The phase detector 210 and the lock detector 220 according to the embodiment of the present invention generate an output signal according to phase difference information and the up / down counter 230 outputs a value according to the output signal of the phase detector 210 / RTI &gt; The digitally controlled current source 240 may be configured to adjust the bias voltage using the value of the up / down counter 230.

9 illustrates a circuit diagram of a phase detector 210 and a lock detector 220 included in a digital phase corrector 200 according to an embodiment of the present invention. The phase detector 210 according to the embodiment of the present invention may be implemented as a Bang-Bang Phase Detector. 9, the phase detector 210 includes a tri-state phase frequency detector (PFD) used for an analog phase locked loop (PLL) and a subsequent processor for processing output values from a tri-state PFD So as to have a transfer function as shown in Fig. The 3-state PFD may comprise two D flip flops 211 and 212 and an AND gate 213 and the subsequent processing unit may include two delay cells 214 and 215 and two D flip flops 216 and 217 ). &Lt; / RTI &gt; 10 illustrates a transfer function according to the phase detector 210 according to an embodiment of the present invention.

In the phase detector 210 shown in Fig. 9, two phases P _A and P _B are input. The two phases P _A and P _B input to the phase detector 210 may be P ₀ and P ₂₅₅ as shown in FIG. That is, P _A and P _B are the first phase P ₀ generated from the first unit cell array D ₀ of the delay cell array 100 and the last phase P ₂₅₅ generated from the last unit cell array D ₁₂₇ , Lt; / RTI &gt; If P _A is greater than P _B , an UP signal is generated, and if P _A is less than P _B , a DOWN signal is generated. Both the up signal and the down signal can be generated when the difference between the P _A and P _B signals is smaller than the preset t _DLY . At this time, t _DLY is a value that can be set on the simulation, and can be set to a value less than half of the delay value? T of the unit delay cell 110, for example.

At this time, the up signal and the down signal output from the phase detector 210 may be directly applied to the up / down counter 230. At the same time, the up signal and the down signal may be connected to the XNOR gate 221 of the lock detector 220 and used to generate a LOCK signal. The XNOR gate 221 operates such that its output becomes high when both the up signal and the down signal, which are the outputs of the phase detector 210, are high or both are low. A lock detector 220 according to an embodiment of the present invention includes an XNOR gate 221, an inverter 222, D flip-flops 223, 224, 225, 226, 227 and 229 and an AND gate 228, . The lock detector 220 according to the embodiment of the present invention is configured such that when the two phases P _A and P _B maintain the locked state during four cycles of the input clock as shown in FIG. 9, (kcal) &lt; / RTI &gt; The four periods may be set differently according to the embodiment. That is, the lock detector 220 according to an embodiment of the present invention can generate a hold signal when the two phases (P _A and P _B ) inputs remain locked for a predetermined time.

11 illustrates a circuit diagram of a current source 240 included in a digital phase corrector 200 according to an embodiment of the present invention. The up / down counter 230 according to the embodiment of the present invention increases and / or decreases the output value one step at a time according to the output signal of the phase detector 210 to generate a digitally controlled And drives the current source 240. As shown in FIG. 11, the upper four bits of the current source 240 are implemented in binary and the lower four bits can be implemented in a thermometer to ensure monostability.

20W, 20W, W, 16W, 32W, 64W and 128W are displayed on the right side of the transistors 247_2, 246_2, 245_2, 244_2, 243_2, 242_2, 241_2 in FIG. This indicates the size (size) of the transistor, and the current flowing through the branches 247 to 241 including the transistor is scaled according to the ratio. For example, the current flowing through the branch 243 is twice (32 W / 16 W) larger than the current flowing through the branch 244.

For example, the digital code, which is an 8 bit calibration code k _CAL delivered from the up / down counter 230, drives a current mirror implemented in a cascode and the current i _DCCS generated from this current mirror is coupled to a pMOS The load (113p and 114p in Fig. 4) is met to regulate the control voltage. At this time, the value of the current i _DCCS generated from the current source 240 according to the embodiment of the present invention may have a value of 0.5Xk _CAL <0.7> added to the value of the current source 249 as shown in FIG. This control voltage may be used to control the unit delay value by being connected to the pMOS loads 113p and 114p included in the unit delay cell 110 of the delay cell array 100 shown in Fig.

12 illustrates a change in the magnitude of a clock generated in the SSCG 1000 according to an embodiment of the present invention in accordance with a modulation waveform. An appropriate modulated signal is required to synthesize the output spread spectrum clock SSC using the 256 phase signals generated from the delay cell array 100 according to the embodiment of the present invention. A modulation profile generator 300 according to an embodiment of the present invention is proposed to obtain a waveform of a spread spectrum clock SSC by changing a modulation waveform, a spread ratio?, A modulation frequency fm and the like.

When triangular waveform modulation as shown in the upper part of FIG. 12 (a) is performed, the EMI reduction performance is reduced due to peaking at the edge portion of the spectrum as shown in the lower part of FIG. 12 (a) . Therefore, the modulation profile generator 300 according to the embodiment of the present invention implements a modulation waveform such as Hershey-Kiss (HK) as shown in the upper part of FIG. 12 (b) using a slope modulation scheme Can be used.

13 illustrates a principle of implementing a hush-kiss modulated waveform in a modulation profile generator 300 according to an embodiment of the present invention. The modulation profile generator 300 according to the embodiment of the present invention can implement a hush-kiss waveform using a two-step modulation method as shown in FIG. First, as shown in Fig. 13 (a), a slope modulation is generated that increases / decreases with time at twice the fm. Then, as shown in FIG. 13 (b), a hush-kiss waveform can be implemented by integrating the modulation frequency fm. At this time, the curvature of the hush-kiss waveform can be adjusted by using the offset and the slope used in the slope modulation. Further, the operation mode such as up / center / down spread can be changed by using the phase combination of the increase / decrease signal.

As shown in FIG. 2, the modulation profile generator 300 according to the embodiment of the present invention may be configured in three parts. A modulation profile generator 300 according to an embodiment of the present invention includes a modulation profile controller 310 (MPC: Modulation Profile Controller) 310 for adjusting a modulation frequency, a spread ratio, a waveform, A delta sigma modulator (DSM) 320 for converting the code modulation information into 8-bit information and an accumulator for converting the code modulation information into phase modulation information. In the modulation profile generator 300 according to the embodiment of the present invention, all the components may be implemented as Verilog codes and may be automatically PNR (Place and Route) using a standard cell.

FIG. 14 illustrates a structure of a modulation profile controller 310 according to an embodiment of the present invention. In FIG. 14, the structure of the modulation profile controller 310 is illustrated by a block diagram. A Modulation Frequency Generator (MFG) 313 for dividing the input clock, a Spread Mode Controller (SMC) 314 for changing a spread mode such as an up / center / down spread, a Hush- A slope controller 312 and an adder 313 for adjusting the slope of the profile, a 16-bit accumulator 314 for changing the triangular profile to a hush-kiss, - Mux (MUX: Multiplexer) capable of selecting a kiss profile.

FIG. 15 is a table showing operation changes of the components in the modulation profile controller 310 according to the external input. The external input may be a condition input to the modulation profile controller 310 via an I ² C (Inter-Integrated Circuit) bus. The operation of the modulation profile controller 310 will be described in more detail with reference to the table shown in FIG.

When the modulation frequency generator 316 generates the modulation frequency fm, its value can be determined through the following mathematical expression (2).

f _m = 19.2 MHz / divider / NFREFSEL / 32 Equation (2)

Here, since the divider and the NREFSEL have a total of 4 and 3 bits respectively, they can vary in the range of 0 to 15 and 0 to 7. Here, the Divider value is used to determine how much the input frequency is to be frequency-divided, and N_REF_SEL indicates that a plurality of values divided by Divider are selected and pulled by using the multiplexer. Accordingly, the modulation frequency fm may vary from 5.7 kHz to 600 kHz for an input frequency of 19.2 MHz.

16 illustrates a simulation result showing a spread waveform change according to a value of the spread mode controller 311 according to an embodiment of the present invention. FIG. 16 shows a change in the spread waveform according to the value of spread <1: 0>. As can be seen from the simulation result of FIG. 16, the center spread, the down spread when the spread value is 1, and the up spread when the spread value is 3 can be shown when the spread values are 0 and 2, respectively.

The hush-kiss profile can be obtained by integrating the triangular profile shown in Fig. 16 for each section. At this time, the slope of the hush-kiss profile generated by adjusting the initial value of the triangular profile and the unit step can be adjusted.

17 illustrates a simulation result showing a change in slope of a hush-kiss profile according to a change in offset and a unit step. Since it is impossible to know in advance what value can be optimal in a real environment, it is implemented so that offset and unit step value can be adjusted using an external 20-bit input.

1.5%의 편차를 갖는 스프레드 스펙트럼 클럭 생성기(1000)는 총 19.2MHz의 클럭을 움직여야 하므로 그에 상응하는 주기인 50.2ns를 50.2*(0.03)만큼 움직여야 한다. 하지만, 19.2MHz를 256개의 위상으로 나눈 딜레이 셀 어레이(100)의 단위 해상도는 50.2ns/256이므로 총 256*(0.03)=7.64칸을 움직여야 한다. 16비트의 해상도를 3비트가 채 안되는 7.64칸으로 줄이기 위해서 본 발명의 실시예에 따른 델타 시그마 변조기(320)를 통한 오버샘플링 기법이 이용될 수 있다. The modulation profile generator 300 according to an embodiment of the present invention may include a Delta Sigma Modulator (DSM) For example, since the output of the modulation profile controller 310, which has a total of 16 bits, has a very high resolution, while the deviation of design requirement (delta) is limited by the amount of unit delay, Modulator 320 is used. for example,

The spread spectrum clock generator 1000 having a deviation of 1.5% must move a clock of 19.2 MHz in total so that the corresponding period of 50.2 ns should be moved by 50.2 * (0.03). However, since the unit cell resolution of the delay cell array 100 in which 19.2 MHz is divided into 256 phases is 50.2 ns / 256, a total of 256 * (0.03) = 7.64 cells must be moved. An oversampling scheme through a delta sigma modulator 320 according to an embodiment of the present invention may be used to reduce the resolution of 16 bits to 7.64 squares, which is less than 3 bits.

FIG. 18 illustrates a simulation result of oversampling using a delta sigma modulator (DSM) according to an embodiment of the present invention. 18 shows a simulation result in which a total of 16 bits of the triangular profile is oversampled by 10 squares using the delta sigma modulator 320. In FIG.

The modulation profile generator 300 according to an embodiment of the present invention may include an accumulator 330 to change the code profile generated through the delta sigma modulator 320 to a direct phase domain selection signal. The accumulator 330 according to the embodiment of the present invention may serve as an ideal integrator to convert the control voltage of the voltage-controlled oscillator into the output phase in the phase locked loop structure.

As described above, the spread spectrum clock generator (SSCG) according to the embodiment of the present invention described in the present invention can spread a frequency of 19.2 MHz, which is a digital clock mainly used in a mobile device such as a cellular phone . The spread ratio and the modulation frequency may be set to 3% and 30 kHz as defaults, for example, but may be variable according to an external SPI (Serial-to-Parallel Interface) input. Up, center and down spreads may be supported depending on the method. In addition, the modulation method can support not only a triangular profile but also Hershey-Kisses having a high EMI reduction effect.

EMI reduction of the SSCG according to an embodiment of the present invention can be roughly predicted through the following equation (3).

Equation (3)

In Equation (2), S is the EMI reduction amount,? Is the spread ratio, fm is the modulation frequency, and f _CLK is the input carrier frequency. When δ is 3% and fm is 30 kHz, the EMI reduction amount S from equation (2) can be expected to be 12.8 dB.

As described above, the spread spectrum clock generator 1000 according to the embodiment of the present invention can provide a direct phase modulation technique for reducing the EMI of the digital clock. The spread spectrum clock generator 1000 according to the embodiment of the present invention separates the clock into 256 phases using the delay cell array 100 and then performs phase equalization using the digital phase corrector 200, The combination may be used in the modulation profile generator 300 to generate a spread spectrum clock (SSC) having various modulation frequencies fm and spread ratios delta. Furthermore, in the embodiment of the present invention, a hush-kiss profile function using a slope modulation method using a phase modulation method is provided, and as a result, an EMI reduction performance of up to 12.8 dB can be obtained.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof. Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, It is intended that all changes and modifications derived from the equivalent concept be included within the scope of the present invention.

1000: SSCG
100: Delay cell array
200: Digital Phase Corrector
300: modulation profile generator

Claims (10)

Each of the unit delay cells includes N (N is a natural number) unit delay cells, each of the unit delay cells generating two differential phases having a complementary waveform to generate 2N phase arrays; And
And a digital phase corrector for generating a calibration signal capable of adjusting a delay value of the unit delay cell,
Spread spectrum clock generator. The method according to claim 1,
Wherein the delay cell array is arranged in m columns and n rows (m X n), wherein the direction of the unit delay cells in two adjacent rows of n rows are different from each other, wherein m * n = N,
Spread spectrum clock generator. 3. The method of claim 2,
Further comprising a multiplexer capable of selecting a phase output from the delay cell array according to a modulation code,
The multiplexer comprising:
A column decoder for activating one of the m columns;
A row decoder for activating one of the n rows; And
And a differential switch for selecting one of the two differential phases output from the unit delay cell located at an intersection of the activated column and the row.
Spread spectrum clock generator. The method of claim 3,
The unit delay cell includes:
First and second nMOS transistors constituting a differential pair;
First and second pMOS transistors constituting a differential latch load; And
And third and fourth pMOS transistors connected in parallel to the first and second pMOS transistors, respectively,
A drain terminal of each of the first and second pMOS transistors is connected to a drain terminal of each of the first and second nMOS transistors,
A differential input to the unit delay cell is input to the gate terminals of the first and second nMOS transistors,
Wherein the delay value of the unit delay cell is adjusted according to a control voltage applied to a gate terminal of each of the third and fourth pMOS transistors,
Spread spectrum clock generator. 5. The method of claim 4,
The two differential phases generated in the unit delay cell are adjacent to the unit delay cell among the N unit delay cells and are transmitted as a differential input of a subsequent unit delay cell in the traveling direction,
The two differential phases are input to a cascode buffer included in the unit delay cell,
Wherein the cascode buffer is capable of being turned on and off according to a row select signal from the row decoder for a row in which the unit delay cell of the n rows is located,
Spread spectrum clock generator. 6. The method of claim 5,
Wherein the delay cell array includes a load buffer corresponding to each of the m columns,
The two differential phases from n unit delay cells included in each of the m columns are transferred to the load buffer of the corresponding column through the cascade buffer,
Spread spectrum clock generator. The method of claim 3,
Further comprising a modulation profile generator for generating and transmitting the modulation code to the multiplexer,
Wherein the modulation profile generator generates the modulation code corresponding to a hush-kiss modulated waveform using a slope modulation scheme,
Spread spectrum clock generator. 8. The method according to any one of claims 1 to 7,
Said digital phase corrector comprising:
A phase detector receiving a first phase and a second phase generated from the delay cell array and generating an up signal and a down signal according to a phase difference;
A lock detector for generating a hold signal when the time at which the up signal and the down signal are input simultaneously from the phase detector is maintained for a predetermined time;
An up / down counter whose magnitude is increased, decreased and held in accordance with the up signal and the down signal from the phase detector and the hold signal; And
And a current source for generating a digitally controlled current according to an output signal according to the up / down counter.
Spread spectrum clock generator. 9. The method of claim 8,
Wherein the phase detector generates the up signal if the first phase is greater than the second phase, the down signal if the first phase is smaller than the second phase, and the up signal and the down signal when the phase difference is less than a predetermined value,
Wherein the first phase is a first phase of the 2N phases and the second phase is a 2Nth phase of the 2N phases,
Spread spectrum clock generator. 9. The method of claim 8,
Wherein the digitally controlled current signal is a calibration signal capable of adjusting a delay value of the unit delay cell,
Spread spectrum clock generator.

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