KR20150085385A - Method for repairing thin film transistor, device including repaired thin film transistor, and organic light emitting display - Google Patents

Abstract

Provided are a method for repairing a thin film transistor, a device including a repaired thin film transistor, and an organic light emitting display. According to a method for repairing a thin film transistor, the thin film transistor includes a semiconductor layer which includes a source region, a drain region, and a first channel and a second channel which are connected in parallel between the source region and the drain region, and a gate electrode which is overlapped with the first channel and at least prat of the second channel. The error of the thin film transistor is inspected. In the first channel and the second channel, an error channel which is short-circuited with the gate electrode is distinguished. The error channel is separated from the source region. The error channel is separated from the drain region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair method for a thin film transistor, an apparatus including the repaired thin film transistor, and an organic light emitting display,

Embodiments of the present invention relate to a repair method of a thin film transistor, an apparatus including the thin film transistor repaired by the repair method, and an organic light emitting display.

The thin film transistor is composed of a gate, a source, a drain, and a channel, and functions as a switching element. The thin film transistor is turned on or off according to the voltage applied to the gate. In the turn-on state, a current flows between the source and the drain, and in the turn-off state, no current flows between the source and the drain. When the channel of the thin film transistor is defective, the thin film transistor is always turned on or off and can not function as a switching element. In this case, the thin film transistor in which the channel is defective needs to be repaired, but since the size of the thin film transistor is getting smaller, it is not easy to repair the thin film transistor.

Embodiments of the present invention provide a repair method for a thin film transistor, an apparatus including the thin film transistor repaired by the repair method, and an organic light emitting display.

According to an aspect of the present invention, there is provided a repair method of a thin film transistor. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a first channel and a second channel connected in parallel between the source region and the drain region, and a semiconductor layer including a first channel and a second channel, And a gate electrode overlapping the gate electrode. According to the repair method of the thin film transistor, defects of the thin film transistor are inspected. And a defective channel in which a defect is generated among the first channel and the second channel is identified. The defective channel is separated from the source region. The defective channel is separated from the drain region.

According to an example of the repair method of the thin film transistor, separating the defective channel from the source region and the drain region includes separating the defective channel from the source region and the drain region, And a step of irradiating a laser to the drain region.

According to another example of the repair method of the thin film transistor, the defective channel is electrically disconnected from the source region and the drain region by an identifier of the defective thin film transistor and a channel number of the defective channel of the repair thin film transistor And storing the determined operation mode.

According to another example of the repair method of the thin film transistor, a current to flow through the first channel and the second channel flows through the normal channel, not the defective channel, among the first channel and the second channel. And correcting a voltage applied to the gate electrode of the repaired thin film transistor based on the identifier and the operation mode.

According to another example of the repair method of the thin film transistor, the aspect ratio of the first channel may be the same as the aspect ratio of the second channel.

According to another example of the repair method of the thin film transistor, the aspect ratio of the first channel may be different from the aspect ratio of the second channel.

According to an aspect of the present invention, there is provided an apparatus for repairing a thin film transistor, the apparatus including a thin film transistor repaired by the repair method of the thin film transistor. The device comprises a substrate, a substrate, a source region, a drain region, a normal channel electrically coupled between the source region and the drain region, and a source region electrically isolated from the source region and the drain region, And a gate electrode disposed on the substrate and overlapping at least part of the normal channel and the defective channel.

According to an example of the apparatus including the repaired thin film transistor, the defective channel and the gate electrode may be electrically short-circuited by the conductive particles.

According to another example of the apparatus including the repaired thin film transistor, the gate electrode may be disposed on the semiconductor layer.

According to another example of an apparatus including the refreshed thin film transistor, the gate electrode may be located between the substrate and the semiconductor layer.

According to an aspect of the present invention, there is provided an organic light emitting display including a substrate, and a display panel including at least one pixel arranged on the substrate. Wherein the at least one pixel comprises a semiconductor layer comprising a source region, a drain region, a first channel and a second channel electrically coupled between the source region and the drain region, and a semiconductor layer including at least the first channel and the second channel, Channel thin film transistor including a gate electrode partially overlapping the gate electrode.

The at least one pixel may further include a pixel electrode electrically connected to the dual channel thin film transistor, an organic light emitting layer on the pixel electrode, and an opposite electrode on the organic light emitting layer. have. The dual channel thin film transistor may provide a driving current to the organic light emitting layer.

According to another example of the organic light emitting display, the first channel may have at least two bent portions. The first channel may have a "d" shape when viewed from a plane.

According to another example of the OLED display device, the channel length of the second channel may be shorter than the channel length of the first channel. The second channel may have a straight shape when viewed from a plane.

According to another example of the OLED display device, the at least one pixel is connected to a gate line and a source line, and receives a data signal input through the source line in response to a scan signal input through the gate line Channel transistor to generate a driving current corresponding to a voltage charged in the capacitor, and a switching transistor to transmit the data signal, a capacitor to charge the voltage corresponding to the transferred data signal, and a driving current corresponding to the voltage charged in the capacitor.

According to another example of the OLED display, when a defect occurs in the first channel or the second channel, the first channel or the second channel in which a defect occurs may be separated from the source region and the drain region .

According to another example of the organic light emitting display, the organic light emitting display includes a pixel including the first channel or the second channel separated from the source region and the drain region, And a memory storing a pixel address and an operation mode determined according to a channel number of the channel separated from the source region and the drain region.

According to another example of the OLED display device, the organic light emitting display includes a timing controller for receiving RGB data (RGB Data) from the outside and generating digital image data (Data) corresponding to the RGB data, A data correction unit that receives the digital image data Data and generates corrected digital image data CData based on the pixel address and the operation mode stored in the memory, A source driver for generating the data signal and providing the data signal to the at least one pixel, and a gate driver for providing the scan signal to the at least one pixel.

Other aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

According to the present invention, since a thin film transistor has a plurality of channels, a thin film transistor can be operated as a switching element by using another channel even if a defect occurs in one channel. As the number of channels is reduced, the driving current of the thin film transistor is reduced, but the reduction of the driving current can be compensated by using the memory for storing the address of the repaired thin film transistor and the data correction unit. In particular, since the driving transistor of the organic light emitting display device has a larger area than other switching transistors, the possibility of channel failure is relatively high. However, according to the present invention, the driving transistor of the organic light emitting display can be repaired even if a channel defect occurs by duplicating the channel. Therefore, the entire organic light emitting display device is not required to be disposed of as a defective one, so that the production cost can be reduced.

FIG. 1 is a plan view schematically illustrating a dual channel thin film transistor according to one embodiment.
2 is a cross-sectional view schematically illustrating a cross-sectional view of the dual channel thin film transistor of FIG. 1 taken along the perforated line.
FIG. 3 schematically shows a cross-sectional view when a failure occurs in the first channel CH1 of the dual channel thin film transistor TFTa shown in FIG.
Figure 4 shows a top view schematically illustrating a refreshed thin film transistor according to one embodiment.
5 is a plan view schematically showing a short channel thin film transistor in which a defect has occurred.
FIG. 6 schematically shows a plan view when the short channel thin film transistor shown in FIG. 5 is repaired.
7 shows a top view schematically showing a refreshed thin film transistor according to another embodiment.
8 is a cross-sectional view schematically showing a section taken along the perforated line of the repairing thin film transistor shown in FIG.
9 illustrates an exemplary equivalent circuit diagram of one subpixel including a dual channel thin film transistor according to one embodiment.
10 is a plan view illustrating an exemplary subpixel shown in FIG.
11 is a block diagram schematically showing an organic light emitting display according to an embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods of achieving them will be apparent with reference to the embodiments described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or corresponding components throughout the drawings, and a duplicate description thereof will be omitted .

In the following embodiments, the terms first, second, etc. are used for the purpose of distinguishing one element from another element, rather than limiting. The singular expressions include plural expressions unless the context clearly dictates otherwise. Or " comprising " or " comprises ", or " comprises ", means that there is a feature, or element, recited in the specification and does not preclude the possibility that one or more other features or elements may be added.

FIG. 1 is a plan view schematically illustrating a dual channel thin film transistor according to one embodiment. 2 is a cross-sectional view schematically illustrating a cross-sectional view of the dual channel thin film transistor of FIG. 1 taken along the perforated line.

Referring to Figs. 1 and 2, a dual channel thin film transistor TFTa including a substrate SUB, a semiconductor layer SL, and a gate electrode GE is shown. The semiconductor layer SL includes a source region SR and a drain region DR and a first channel CH1 and a second channel CH2 connected in parallel between the source region SR and the drain region DR. do.

A substrate (SUB) can be an insulating substrate made of a glass material, or a transparent plastic material of a transparent material whose main component is silicon oxide (SiO _2). The substrate SUB may be a conductive substrate made of a thin metal material. The substrate SUB may be a flexible substrate or a rigid substrate. A buffer layer (not shown) may be disposed on the substrate SUB to prevent diffusion of impurity ions and penetration of moisture or outside air, and to provide a planarized surface. The buffer layer may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide or titanium nitride. The buffer layer may contain an organic insulating material such as polyimide, polyester, acryl, etc., or may be formed of a laminate of the exemplified materials or a laminate of an organic insulating material and an inorganic insulating material.

A semiconductor layer SL may be disposed on the substrate SUB. The semiconductor layer SL includes a source region SR and a drain region DR which are doped with an impurity and have conductivity. The semiconductor layer SL includes a first channel CH1 and a second channel CH2 connecting the source region SR and the drain region DR. For example, a polysilicon layer (not shown) may be formed by first depositing a layer of semiconductor material (not shown), for example, an amorphous silicon layer, over the substrate SUB and then crystallizing it. The amorphous silicon may be formed by a rapid thermal annealing (RTA) process, a solid phase crystallization (SPC) process, an excimer laser annealing (ELA) process, a metal induced crystallization (MIC) process, a metal induced lateral crystallization (MILC) process, ) Method and the like. The polysilicon layer thus formed can be patterned by a photolithography process into an active pattern including the source region SR, the first and second channels CH1 and CH2, and the drain region DR. According to another example, an active pattern including a source region SR, first and second channels CH1 and CH2, and a drain region DR is formed by first patterning the amorphous silicon layer and then crystallizing the amorphous silicon layer It is possible.

The semiconductor layer SL may be formed of a silicon-based element semiconductor, but according to other examples, the semiconductor layer SL may be formed of a compound semiconductor, for example, an oxide semiconductor or an organic semiconductor.

A selective ion implantation process is performed on the source region SR and the drain region DR, so that impurities can be implanted. A low concentration source region (not shown) is interposed between the source region SR and the first and second channels CH1 and CH2 and a drain region DR and a first channel CH1 and a second channel CH2 A low concentration drain region (not shown) may be interposed.

The first channel CH1 and the second channel CH2 are disposed adjacent to each other and provide a conductive path disposed in parallel between the source region SR and the drain region DR. That is, when the dual channel thin film transistor TFTa is turned on, the source region SR and the drain region DR are electrically connected through both the first channel CH1 and the second channel CH2. When the dual channel thin film transistor TFTa is turned off, both the first channel CH1 and the second channel CH2 are non-inverted, so that the source region SR and the drain region DR are electrically isolated from each other. In FIG. 1, the first channel CH1 and the second channel CH2 are shown to have the same aspect ratio, but this is exemplary, and the first channel CH1 and the second channel CH2 have different aspect ratios It is possible.

A gate insulating film GI covering the semiconductor layer SL may be disposed on the semiconductor layer SL. The gate insulating film GI may be formed of an oxide, a nitride, an oxynitride, or a combination thereof.

A gate electrode GE overlapping at least a part of the first and second channels CH1 and CH2 of the semiconductor layer SL may be disposed on the gate insulating film GI. A conductive material layer (not shown) is stacked on the gate insulating layer GI, and the conductive material layer may be patterned into the gate electrode GE through a photolithography process and an etching process. The gate electrode GE may be made of a metal such as molybdenum (Mo), molybdenum tungsten (MoW), aluminum (Al) alloy or the like, but is not limited thereto. In addition, the gate electrode GE may have a laminated structure of molybdenum (Mo) / aluminum (Al) / molybdenum (Mo).

The gate electrode GE can function as an ion mask in the process of implanting impurities into the source region SR and the drain region DR. The first channel CH1 and the second channel CH2 may be defined as a portion overlapping the gate electrode GE as the semiconductor layer SL between the source region SR and the drain region DR.

The dual channel thin film transistor TFTa may be electrically connected to other thin film transistors or other elements such as organic light emitting diodes. For example, the dual channel thin film transistor TFTa is connected to the drain region DR via the source electrode SE and / or the drain contact DC which is electrically connected to the source region SR through the source contact SC. And may be electrically connected to other elements through the electrically connected drain electrode DE. The dual channel thin film transistor TFTa may be electrically connected to another element using the semiconductor layer SL. For example, the source region SR or the drain region DR of the dual channel thin film transistor TFTa may be the drain region DR or the source region SR of another thin film transistor (not shown).

Defects may occur in the first channel (CH1) or the second channel (CH2) of the dual channel thin film transistor TFTa. FIG. 3 schematically shows a cross-sectional view when a failure occurs in the first channel CH1 of the dual channel thin film transistor TFTa shown in FIG.

As shown in FIG. 3, the first channel CH1 and the gate electrode GE may be short-circuited due to the conductive particles P during the manufacturing process. The first channel CH1 in which a failure occurs is referred to as a bad channel, and the second channel CH2 in which a failure has not occurred can be referred to as a normal channel. The source region SR and the drain region DR can always be electrically connected regardless of the voltage applied to the gate electrode GE due to the failure of the first channel CH1. Depending on the conductivity type of the dual channel thin film transistor TFTa, the source region SR and the drain region DR may always be electrically insulated because of the failure of the first channel CH1. The second channel CH2 operates normally but the first channel CH1 and the second channel CH2 are connected in parallel so that the dual channel thin film transistor TFTa can no longer function as a switching element.

Figure 4 shows a top view schematically illustrating a refreshed thin film transistor according to one embodiment.

Referring to FIG. 4 together with FIG. 3, a first channel CH1 of a refreshed thin film transistor TFTb is separated from a source region SR and a drain region DR, as shown in FIG.

According to the standard manufacturing process, it is checked whether the device including the dual channel thin film transistor TFTa in the test process operates normally. As described above, the dual channel thin film transistor TFTa shown in FIG. 3 can not function as a switching element due to a failure occurring in the first channel CH1. Defective of the dual channel thin film transistor (TFTa) can be confirmed in the test process.

The defective channel of the dual channel thin film transistor TFTa is identified. Whether the first channel CH1 of the dual channel thin film transistor TFTa is defective or the second channel CH2 is defective can be confirmed. For example, the tester can observe the double-channel thin film transistor TFTa under a microscope to see that the conductive particles P exist on the first channel CH1 as shown in Fig. According to another example, the tester may verify that the first channel CH1 is a bad channel through an electrical test.

The tester can separate the first channel CH1 in which the defect has occurred from the source region SR and the drain region DR. For example, the portion of the source region SR may be cut by irradiating a portion of the source region SR adjacent to the first channel CH1. The first channel CH1 may be electrically isolated from the source region SR. In addition, the portion of the drain region DR can be cut by irradiating a laser to a portion of the drain region DR adjacent to the first channel CH1. The first channel CH1 can be electrically isolated from the drain region DR. Therefore, the first channel CH1 can not function as an electrical path for electrically connecting the source region SR and the drain region DR.

For laser irradiation for electrical isolation, the portion of the source region SR adjacent to the first channel CH1 and the portion of the drain region DR may not be covered by the conductive material. For example, the metal patterns may not be disposed above the portion of the source region SR and the portion of the drain region DR.

Since the first channel CH1 is electrically isolated from the source region SR and the drain region DR, the thin film transistor TFTb can function as a switching element through the second channel CH2. That is, the thin film transistor TFTb can be repaired by a normal thin film transistor.

By removing the first channel CH1, the current between the source region SR and the drain region DR is reduced. That is, if the first channel CH1 is not removed due to a failure occurring in the first channel CH1, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode GE, Lt; RTI ID = 0.0 > (CH2). ≪ / RTI > However, since the first channel CH1 is removed, a current flows only through the second channel CH2, and the magnitude of the current becomes smaller than the magnitude of the current before the first channel CH1 is removed. For example, when the thin film transistor TFTb operates as a switching element, a large problem will not occur. However, when the thin film transistor TFTb operates as an analog element to which a current proportional to the gate electrode GE flows The size of the current flowing between the source region SR and the drain region DR is reduced, so that the repaired thin film transistor TFTb can not perform normal operation. To solve this problem, the apparatus including the thin film transistor TFTb may further include a memory and a data correction unit.

The memory can store an operation mode determined according to the identifier of the repaired thin film transistor TFTb and the channel number of the removed channel (the first channel CH1 in this example) of the repaired thin film transistor TFTb. The data correction unit corrects the remaining channel of the thin film transistor TFTb in which the current to be flowed through the first channel CH1 and the second channel CH2 of the normal dual channel thin film transistor TFTa has been repaired, (CH2)), it is possible to correct the voltage applied to the gate electrode GE of the refreshed thin film transistor TFTb based on the identifier stored in the memory and the operation mode. The memory and data correction unit will be described in more detail with reference to FIG.

5 is a plan view schematically showing a short channel thin film transistor in which a defect has occurred. FIG. 6 schematically shows a plan view when the short channel thin film transistor shown in FIG. 5 is repaired.

Referring to Fig. 5, a short channel thin film transistor TFTp is shown. The short channel thin film transistor TFTp is substantially the same as the double channel thin film transistor TFTa except that one channel CH is disposed between the source region SR and the drain region DR.

As shown in FIG. 5, defects may occur in the channel CH due to the conductive particles P. For example, the conductive particles P may cause a short between the channel CH and the gate electrode GE. In this case, since the short channel thin film transistor TFTp is always turned on or off, it can not function as a switching element.

6, a hole H surrounding the conductive particles P is formed in the gate electrode GE to electrically isolate the conductive particles P from the gate electrode GE, thereby forming the short channel thin film transistor TFTp. Can be repaired. However, since the devices including the thin film transistors are becoming highly integrated and the size of the thin film transistor becomes small, the gate electrode GE is cut or the semiconductor layer SL is formed while forming the hole H as shown in FIG. The pattern can be cut. In this case, the repair of the short channel thin film transistor TFTp fails. When the gate electrode GE is cut, not only the thin film transistor but also other thin film transistors connected to the conductive pattern including the gate electrode GE can not perform normal operation.

7 shows a top view schematically showing a refreshed thin film transistor according to another embodiment. 8 is a cross-sectional view schematically showing a section taken along the perforated line of the repairing thin film transistor shown in FIG.

Referring to Figures 7 and 8, a refreshed thin film transistor TFTc is shown. The repaired thin film transistor TFTc has the same structure as the repaired thin film transistor TFT3 shown in FIG. 3 except that the gate electrode GE is a bottom gate type interposed between the substrate SUB and the semiconductor layer SL. (TFTb). The repaired thin film transistor TFTb shown in FIG. 3 is a top gate type in which the gate electrode GE is disposed on the semiconductor layer SL.

The repaired thin film transistor TFTc includes a substrate SUB, a gate electrode GE, and a semiconductor layer SL. A gate insulating film GI is interposed between the gate electrode GE and the semiconductor layer SL. The semiconductor layer SL is disposed on the gate insulating film GI and includes a source region SR, a drain region DR, a second channel CH2 (not shown) electrically connected between the source region SR and the drain region DR, And a first channel CH1 that is electrically insulated from the source region SR and the drain region DR and is disposed adjacent to the second channel CH2 and has a defect. The first channel CH1 in which a failure occurs is referred to as a bad channel, and the second channel CH2 in which a failure has not occurred can be referred to as a normal channel.

The gate electrode GE is sandwiched between the substrate SUB and the gate insulating film GI and overlaps at least a part of the first channel CH1 and the second channel CH2. 8, the conductive particles P are interposed between the gate electrode GE and the first channel CH1 to cause a short failure between the gate electrode GE and the first channel CH1 have. However, since the first channel CH1 is electrically isolated from the source region SR and the drain region DR, the failure of the first channel CH1 does not affect the operation of the repaired thin film transistor TFTc . When the refreshed thin film transistor TFTc is turned on, the source region SR and the drain region DR are electrically connected through the second channel CH2. The repaired thin film transistor TFTc can operate as a switching element through the second channel.

The device including the thin film transistors (TFTa, TFTb, TFTc) according to the above-described embodiments may be, for example, an organic light emitting display. Hereinafter, an organic light emitting diode display including a dual channel thin film transistor will be described in accordance with the above embodiments.

9 illustrates an exemplary equivalent circuit diagram of one subpixel including a dual channel thin film transistor according to one embodiment.

Referring to FIG. 9, a sub-pixel including thin film transistors T1, T2, T3, T4, T5 and T6, a storage capacitor Cst and an organic light emitting diode (OLED) SP) is shown. The subpixel SP is connected to the signal lines 12, 14, 16, 32, 34, An organic light emitting diode (OLED) emits light by receiving a driving current Id from the thin film transistor T1.

The thin film transistors T1 to T6 are constituted by a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initial thin film transistor T4, an operation control thin film transistor T5, T6). ≪ / RTI >

Each of the signal lines 12, 14, 16, 32, 34 and 42 includes a gate line 14 for transferring a scan signal Sn, a transfer gate 14 for transferring a previous scan signal Sn- A light emission control line 16 for transmitting a light emission control signal En to the gate line 12, the operation control thin film transistor T5 and the light emission control thin film transistor T6, A driving voltage line 34 extending in parallel with the source line 32 for transferring the driving voltage ELVDD and an initializing voltage Vint for initializing the driving thin film transistor T1, And may be referred to as an initialization voltage line 42 that carries the voltage.

The driving thin film transistor T1 may be a dual channel thin film transistor including two channels which are controlled by a control signal applied to the gate electrode G1 and connected in parallel. The gate electrode G1 of the driving thin film transistor T1 is connected to the first electrode Cst1 of the storage capacitor Cst. The source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line 34 via the operation control thin film transistor T5. The drain electrode D1 of the driving thin film transistor T1 is electrically connected to the anode of the organic light emitting device OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies the driving current Id to the organic light emitting element OLED.

The gate electrode G2 of the switching thin film transistor T2 is connected to the gate line 14 and the source electrode S2 of the switching thin film transistor T2 is connected to the source line 32. [ The drain electrode D2 of the switching thin film transistor T2 is connected to the source electrode S1 of the driving thin film transistor T1 and is connected to the driving voltage line 34 via the operation control thin film transistor T5. The switching TFT T2 turns on the data signal Dm transferred to the source line 32 according to the scan signal Sn transmitted through the gate line 14 to the source electrode of the driving TFT T1 Lt; RTI ID = 0.0 > S1. ≪ / RTI >

And the gate electrode G3 of the compensating thin film transistor T3 is connected to the gate line 14. [ The source electrode S3 of the compensating thin film transistor T3 is connected to the drain electrode D1 of the driving thin film transistor T1 and is connected to the anode of the organic light emitting element OLED via the emission control thin film transistor T6. Lt; / RTI > The drain electrode D3 of the compensating thin film transistor T3 is connected to the first electrode Cst1 of the storage capacitor Cst and the drain electrode D4 of the initializing thin film transistor T4 and the gate electrode G1 of the driving thin film transistor T1 ). The compensating thin film transistor T3 is turned on according to the scan signal Sn transmitted through the gate line 14 to connect the gate electrode G1 and the drain electrode D1 of the driving thin film transistor T1 to each other, And the transistor T1 is diode-connected.

The gate electrode G4 of the initializing thin film transistor T4 is connected to the previous gate line 12 and the source electrode S4 of the initializing thin film transistor T4 is connected to the initialization voltage line 42. [ The drain electrode D4 of the initialization thin film transistor T4 is connected to the first electrode Cst1 of the storage capacitor Cst, the drain electrode D3 of the compensating thin film transistor T3 and the gate electrode G1 of the driving thin film transistor T1 ). The initializing TFT T4 is turned on according to the previous scan signal Sn-1 transferred through the previous gate line 12 to transfer the initialization voltage Vint to the gate electrode G1 of the driving TFT T1 And performs an initialization operation for initializing the voltage of the gate electrode G1 of the driving thin film transistor T1.

The gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line 16 and the source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line 34, The drain electrode D5 of the thin film transistor T5 is commonly connected to the source electrode S1 of the driving thin film transistor T1 and the drain electrode D2 of the switching thin film transistor T2.

The gate electrode G6 of the light emission control thin film transistor T6 is connected to the emission control line 16 and the source electrode S6 of the light emission control thin film transistor T6 is connected to the drain electrode D1 of the driving thin film transistor T1. And the source electrode S3 of the compensating thin film transistor T3. The drain electrode D6 of the light emission control thin film transistor T6 is connected to the anode of the organic light emitting device OLED. The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in accordance with the emission control signal En received through the emission control line 16 to generate a drive current (Id) flows to the organic light emitting element OLED.

And the second electrode (Cst2) of the storage capacitor (Cst) is connected to the driving voltage line (34). The first electrode Cst1 of the storage capacitor Cst is connected to the gate electrode G1 of the driving thin film transistor T1, the drain electrode D3 of the compensating thin film transistor T3 and the drain electrode of the initializing thin film transistor T4 D4.

The cathode of the organic light emitting diode OLED is connected to the common voltage ELVSS. The organic light emitting diode OLED emits light by receiving a driving current Id supplied from the driving thin film transistor T1. The organic light emitting elements OLED of the plurality of sub-pixels SP display an image.

Hereinafter, a specific operation process of one subpixel of the organic light emitting display shown in FIG. 9 of the present invention will be described in detail.

During the initialization period, the previous scan signal (Sn-1) of a low level is supplied through the previous gate line (12). The initializing thin film transistor T4 is turned on in response to the low level previous scan signal Sn-1 and the initializing voltage Vint is supplied from the initializing voltage line 42 through the initializing thin film transistor T4 Is connected to the gate electrode G1 of the driving thin film transistor T1 and the driving thin film transistor T1 is initialized by the initializing voltage Vint.

Then, a low level scan signal Sn is supplied through the gate line 14 during the data programming period. The switching thin film transistor T2 and the compensation thin film transistor T3 are turned on in response to the low level scan signal Sn. At this time, the driving thin film transistor T1 is diode-connected by the turned-on compensating thin film transistor T3 and biased in the forward direction. The compensation voltage Dm-Vth reduced by the threshold voltage Vth of the driving thin film transistor T1 from the data signal Dm supplied through the source line 32 is applied to the first electrode Cst1 of the storage capacitor Cst . The drive voltage ELVDD and the compensation voltage Dm-Vth are applied to both ends of the storage capacitor Cst and the charge corresponding to the voltage difference ELVDD-Dm + Vth is stored in the storage capacitor Cst.

Thereafter, the emission control signal En supplied from the emission control line 16 during the emission period is changed from the high level to the low level. The operation control thin film transistor T5 and the emission control thin film transistor T6 are turned on by the low level emission control signal En during the light emission period. The driving current Id corresponding to the voltage difference (ELVDD-Dm + Vth) between the voltage (Dm-Vth) of the gate electrode G1 of the driving thin film transistor T1 and the driving voltage ELVDD is generated, The driving current Id is supplied to the organic light emitting element OLED through the transistor T6. The gate-source voltage Vgs of the driving thin film transistor T1 is maintained at ELVDD-Dm + Vth by the storage capacitor Cst during the light emission period, and according to the current-voltage relationship of the driving thin film transistor T1, (Id) is proportional to the square of the source-gate voltage Vgs, i.e., the value obtained by subtracting the threshold voltage Vth from ELVDD-Dm + Vth, i.e., (ELVDD-Dm) ² . Therefore, the driving current Id is determined regardless of the threshold voltage Vth of the driving thin film transistor T1.

Although the driving thin film transistor T1 in FIG. 9 is illustrated as being a dual channel thin film transistor (TFTa, TFTb, TFTc) according to various embodiments, other thin film transistors T2- May be thin film transistors (TFTa, TFTb, TFTc).

Hereinafter, the detailed structure of subpixels of the organic light emitting display device shown in FIG. 9 will be described in detail with reference to FIG.

10 is a plan view illustrating an exemplary subpixel shown in FIG.

10, the subpixel SP of the OLED display includes a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, An operation control thin film transistor T5, a light emission control thin film transistor T6, a storage capacitor Cst, and an organic light emitting element OLED. The subpixel SP applies a scan signal Sn, a previous scan signal Sn-1, a light emission control signal En, an initialization voltage Vint, a data signal Dm, and a drive voltage ELVDD The gate line 14, the previous gate line 12, the emission control line 16, the initialization voltage line 42, the source line 32, and the driving voltage line 34. The gate line 14, the previous gate line 12, the emission control line 16, and the initialization voltage line 42 extend in the row direction, and the source line 32 and the drive voltage line 34 extend in the column direction Lt; / RTI >

The subpixel SP may include a semiconductor layer SL, a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4. Insulating films are interposed between the semiconductor layer SL, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. The subpixel SP further includes an intermediate layer (not shown) including an organic light emitting layer and a counter electrode layer (not shown).

The semiconductor layer SL includes a first driving active pattern Act1a and a second driving active pattern Act1b of the driving thin film transistor T1, a switching active pattern Act2 of the switching thin film transistor T2, a compensation thin film transistor T3 The initialization active pattern Act4 of the initialization thin film transistor T4, the operation control active pattern Act5 of the operation control thin film transistor T5, and the light emission control of the light emission control thin film transistor T6 And an active pattern Act6. The semiconductor layer SL may include a source region, a drain region, and a channel between the source region and the drain region. The semiconductor layer SL may have various shapes depending on the design.

The first conductive layer M1 may include a previous gate line 12, a gate line 14, and a light emission control line 16. [ The first conductive layer M1 includes a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, an operation control thin film transistor T5 and a light emission control thin film transistor T6 ) Gate electrodes g1-g6, respectively. The second conductive layer M2 may include a second electrode Cst2 of the capacitor Cst. The third conductive layer M3 may include a source line 32, a driving voltage line 34 and a connecting line 36. [ The fourth conductive layer M4 may include an initialization voltage line 42 and a pixel electrode 44. [

The driving thin film transistor T1 includes a source region s1, a drain region d1, a first driving active pattern Act1a including a first channel, a second driving active pattern Act1b including a second channel, And a driving gate electrode g1 at least partially overlapping the first channel and the second channel. The first channel is defined as a portion overlapping the driving gate electrode g1 in the first driving active pattern Act1a and the second channel is defined as a portion overlapping the driving gate electrode g1 in the second driving active pattern Act1b, .

The first channel of the driving thin film transistor T1 is electrically connected between the source region s1 and the drain region d1 and may have at least two bent portions. For example, the first channel may have the shape of "d" as viewed in plan, as shown in Fig. As shown in FIG. 10, since the first channel occupies a large area, there is a high possibility that defects are caused by conductive parts during the manufacturing process. According to one embodiment, the driving thin film transistor T1 includes a second channel in addition to the first channel.

The second channel of the driving thin film transistor T1 is electrically connected in parallel with the first channel between the source region s1 and the drain region d1. As shown in FIG. 10, the second channel may have a channel length shorter than the channel length of the first channel, and may have a straight line when viewed from a plane. The aspect ratio of the second channel may be greater than the aspect ratio of the first channel.

When a defect occurs in the first channel, the first channel can be electrically separated from the source region s1 and the drain region d1. The driving thin film transistor T1 can generate the driving current Id through the second channel and supply the driving current Id to the organic light emitting element OLED. Defects may also occur in the second channel. In this case, the second channel can be electrically separated from the source region s1 and the drain region d1. The driving thin film transistor T1 can generate the driving current Id through the first channel and supply the driving current Id to the organic light emitting element OLED. Therefore, the driving thin film transistor T1 can be repaired even if a failure occurs in the first channel or the second channel.

The storage capacitor Cst includes a driving gate electrode g1 and a second electrode Cst2 that function as a first electrode Cst1. And the second electrode Cst2 is disposed on the driving gate electrode g1. The second electrode Cst2 may be designed to overlap with the driving gate electrode g1 at the maximum to obtain the maximum capacitance. The second electrode (Cst2) may be connected to the driving voltage line (34) through at least one contact plug (34p1). The second electrode Cst2 includes an opening Cst2op through which the contact plug 36p1 connected between the driving gate electrode g1 and the connection line 36 can pass.

The switching thin film transistor T2 includes a switching active pattern Act2 and a switching gate electrode g2 which is a part of the gate line 14. [ The switching active pattern Act2 includes a channel region overlapping the switching gate electrode g2 and a source region s2 and a drain region d2. The source region s2 may be connected to the source line 32 through the contact plug 32p1. The drain region d2 is connected to the source region s1 of the driving thin film transistor T1 along the semiconductor layer SL.

The compensating thin film transistor T3 includes a compensating active pattern Act3 and a compensation gate electrode g3 which is a part of the gate line 14. [ The compensation active pattern Act3 includes a channel region overlapping the compensation gate electrode g3 and a source region s3 and a drain region d3. The source region s3 is connected to the drain region d1 of the driving thin film transistor T1 along the semiconductor layer SL. The drain region d3 may be connected to the connection line 36 via the contact plug 36p2. That is, the drain region d3 of the compensating thin film transistor T3 is electrically connected to the driving gate electrode g1 through the connection line 36. [ As shown in Fig. 10, the compensation gate electrode g3 is formed of a dual gate electrode having two gate electrodes, so that leakage current can be reduced.

The initialization thin film transistor T4 may include an initialization active pattern Act4 and an initialization gate electrode g4 which is a part of the previous gate line 12. [ The initialization active pattern Act4 includes a channel region overlapping the initialization gate electrode g4, and a source region s4 and a drain region d4. The source region s4 is connected to the initialization voltage line 42 through the contact plug 42p. The drain region d4 is connected to the connection line 36 through the contact plug 36p2. As shown in Fig. 10, the initialization gate electrode g4 is formed of a dual gate electrode having two gate electrodes, so that leakage current can be reduced.

The operation control thin film transistor T5 includes an operation control active pattern Act5 and an operation control gate electrode g5 which is a part of the light emission control line 16. [ The operation control active pattern Act5 includes a channel region overlapping the operation control gate electrode g5, and a source region s5 and a drain region d5. The drain region d5 is connected to the source region s1 of the driving thin film transistor T1 along the semiconductor layer SL. The source region s5 is connected to the driving voltage line 34 through the contact plug 34p2.

The light emission control thin film transistor T6 includes the light emission control active pattern Act6 and the light emission control gate electrode g6 which is a part of the light emission control line 16. [ The light emission control active pattern Act6 includes a channel region overlapping the light emission control gate electrode g6 and a source region s6 and a drain region d6. The source region s6 is connected to the drain region d1 of the driving thin film transistor T1 along the semiconductor layer SL. And the drain region d6 is connected to the pixel electrode 44 through the contact plug 44p.

The pixel electrode 44 may be disposed on the second electrode Cst2 and may provide an electric current to the intermediate layer including the organic light emitting layer disposed on the upper portion. The current applied to the intermediate layer is transmitted to the counter electrode (not shown) on the intermediate layer.

The equivalent circuit diagram shown in Fig. 9 and the plan view shown in Fig. 10 are illustrative and can be variously modified according to the design.

11 is a block diagram schematically showing an organic light emitting display according to an embodiment.

11, the OLED display 100 includes a display panel 110, a gate driver 120, a source driver 130, a timing controller 140, a data correction unit 150, and a memory 160 .

The OLED display 100 may be a component for displaying images of electronic devices such as a smart phone, a tablet PC, a notebook PC, a monitor, a TV, and the like.

The display panel 110 includes a plurality of pixels P arranged in a matrix. Each of the pixels P includes a predetermined number of (e.g., three, two, or four) sub-pixels SP. The pixel P displays a subpixel SP displaying a first color (e.g., green), a subpixel SP displaying a second color (e.g., red), and a subpixel SP displaying a third color (e.g., blue) And a sub-pixel SP. According to another example, the pixel P may further include a subpixel SP representing a fourth color (e.g., white). According to another example, the display panel 110 may include a first sub-pixel SP including a sub-pixel SP displaying a first color (e.g., green) and a sub-pixel SP displaying a second color (e.g., red) A second pixel P including a subpixel SP displaying a first color (e.g., green) and a subpixel SP displaying a third color (e.g., blue) Lt; / RTI >

A plurality of gate lines GL extending in a first direction (e.g., a row direction) and a plurality of source lines SL extending in a second direction (e.g., column direction) are arranged on the display panel 110 . The gate lines GL and the source lines SL are electrically connected to the sub-pixels SP.

The subpixels SP may include, for example, the subpixels SP shown in Figs. 9 and 10. As described above, the subpixel SP may include a dual channel thin film transistor. The sub-pixel SP includes a switching transistor (for example, a switching thin film in FIG. 9) for transferring a data signal Dm input through a source line SL in response to a scan signal Sn input through a gate line GL. A capacitor (for example, the storage capacitor Cst in Fig. 9) for charging a voltage (e.g., ELVDD-Dm + Vth in the subpixel in Fig. 9) corresponding to the data signal Dm transferred from the switching transistor, And a dual channel thin film transistor (e.g., a driving thin film transistor T1) that generates a driving current Id corresponding to a voltage charged in the capacitor. As described above, the dual channel thin film transistor includes a source region, a drain region, and a first channel and a second channel which are connected in parallel between the source region and the drain region.

A failure may occur in the first channel or the second channel. For example, a short failure may occur between the first channel or the second channel and the gate electrode. For ease of explanation below, it is assumed that a failure has occurred in the first channel, for example. The first channel is referred to as a bad channel, and the second channel is referred to as a normal channel. The defective channel is electrically separated from the source region and the drain region. For example, the source region and the drain region adjacent to the defective channel can be cut using a laser. The driving current Id is generated through the first channel and the second channel of the driving thin film transistor T1. Since the first thin film transistor T1 is repaired due to the repair process, . A voltage applied to the driving gate electrode g1 of the driving thin film transistor T1 so that the driving current Id corresponding to the data signal Dm can be generated through the second channel of the driving thin film transistor T1. Should be corrected.

The memory 160 may store the pixel address Addr of the subpixel SP including the repaired driving thin film transistor T1. The memory 160 may store an operation mode (mod) determined according to which of the first channel and the second channel of the repaired drive thin film transistor T1 is separated from the source region and the drain region. For example, if the first channel is split, the mode of operation (mod) may be one. For example, if the second channel is split, the mode of operation (mod) may be two. If the aspect ratios of the first channel and the second channel are the same, the memory 160 may store only the address of the subpixel SP including the repaired drive thin film transistor T1.

The aspect ratios of the first channel and the second channel may be different from each other. As shown in FIG. 10, the aspect ratio of the second channel may be larger than the aspect ratio of the first channel. That is, the second channel may have a larger current driving capability than the first channel. For example, it is assumed that the current driving capability of the second channel is twice the current driving capability of the first channel. If the operation mode is 1, the second channel should generate 1.5 times the current. If the operation mode is 2, the first channel should generate three times the current. To this end, the voltage applied to the driving gate electrode g1 can be corrected.

The data correction unit 150 includes the repaired driving thin film transistor T1 based on the pixel address Addr stored in the memory and the operation mode mod in order to correct the voltage applied to the driving gate electrode g1 The data provided to the sub-pixel SP which is the sub-pixel SP can be corrected. For example, when the operation mode (mod) is 1, the data corresponding to the pixel address (Addr) can be corrected so that the repaired drive thin film transistor (T1) can generate 1.5 times the drive current with the second channel. For example, when the operation mode (mod) is 2, the data corresponding to the pixel address (Addr) can be corrected so that the repaired drive thin film transistor (T1) can generate three times the drive current on the first channel.

The timing controller 140 may control the gate driver 120 and the source driver 130. [ The timing controller 140 receives the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, the clock CLK and the RGB data RGB data for the input frame and outputs the first control signal CON1, 2 < / RTI > control signal CON2. For example, the timing controller 140 can generate the first control signal CON1, the second control signal CON2, and the digital image data Data based on the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC have.

The data correction unit 150 receives the digital image data Data and generates corrected digital image data CData based on the pixel address Addr stored in the memory 150 and the operation mode mod. The corrected digital image data CData is obtained by correcting the data corresponding to the pixel address Addr according to the operation mode (mod).

The source driver 130 may drive the source lines SL1 to SLn in response to the second control signal CON2 and the corrected digital image data CData. The source driver 130 converts the corrected digital image data CData into data signals having gradation voltages and sequentially supplies the data signals to the subpixels SP through the source lines SL1 to SLn can do. The subpixel SP corresponding to the pixel address Addr receives the corrected digital image data CData and the repaired drive thin film transistor T1 responds to the digital image data Data before correction using only the normal channel (Id) < / RTI > The subpixel SP corresponding to the pixel address Addr can emit light with the luminance corresponding to the digital image data Data before correction.

The gate driver 120 may sequentially drive the gate lines GL1 to GLm in response to the first control signal CON1. For example, the first control signal CON1 may be an instruction signal for instructing the gate driver 120 to start scanning the gate lines GL1-GLm. The gate driver 120 may generate a scan signal and sequentially provide a scan signal to the sub-pixels SP through the gate lines GL1-GLm.

The gate driver 120, the source driver 130, and the timing controller 140 may be formed on separate semiconductor chips or integrated on one semiconductor chip. The gate driver 120 may be formed on the same substrate together with the display panel 110.

Although the present invention has been described with reference to the limited embodiments, various embodiments are possible within the scope of the present invention. It will also be understood that, although not described, equivalent means are also incorporated into the present invention. Therefore, the true scope of protection of the present invention should be defined by the following claims.

100: organic light emitting display
110: Display panel
120: gate driver
130: source driver
140: Timing controller
150: Data correction unit
160: Memory

Claims (20)

A semiconductor device comprising: a semiconductor layer including a source region, a drain region, and a first channel and a second channel connected in parallel between the source region and the drain region; and a gate electrode A repair method of a thin film transistor including an electrode,
Inspecting a defect of the thin film transistor;
Identifying a defective channel in which a defect has occurred among the first channel and the second channel;
Separating the defective channel from the source region; And
And separating the defective channel from the drain region. The method according to claim 1,
Separating the defective channel from the source region and the drain region comprises irradiating the source region and the drain region with a laser so that the defective channel is electrically insulated from the source region and the drain region Wherein the repairing method of the thin film transistor is performed. The method according to claim 1,
Further comprising the step of storing an operation mode determined by the identifier of the repaired thin film transistor and the channel number of the defective channel of the repaired thin film transistor by electrically separating the defective channel from the source region and the drain region Wherein said repairing method comprises: The method of claim 3,
The method of claim 1, further comprising: determining whether the current flowing through the first channel and the second channel flows through a normal channel, not the bad channel, among the first channel and the second channel, Further comprising the step of correcting a voltage applied to the gate electrode of the transistor. The method according to claim 1,
Wherein the aspect ratio of the first channel is equal to the aspect ratio of the second channel. The method according to claim 1,
Wherein the aspect ratio of the first channel is different from the aspect ratio of the second channel. An apparatus comprising a thin film transistor repaired by a repair method of a thin film transistor according to any one of claims 1 to 6,
Board;
A source region, a drain region, a normal channel electrically connected between the source region and the drain region, and a source region electrically insulated from the source region and the drain region and disposed adjacent to the normal channel A semiconductor layer including a defective channel where a defect occurs; And
And a gate electrode disposed on the substrate and overlapping at least part of the normal channel and the defective channel. 8. The method of claim 7,
Wherein the defective channel and the gate electrode are electrically shorted by conductive particles. 8. The method of claim 7,
And wherein the gate electrode is disposed on the semiconductor layer. 8. The method of claim 7,
And wherein the gate electrode is positioned between the substrate and the semiconductor layer. Board; And
And a display panel including at least one pixel arranged on the substrate,
Wherein the at least one pixel comprises a semiconductor layer comprising a source region, a drain region, a first channel and a second channel electrically coupled between the source region and the drain region, and a semiconductor layer including at least the first channel and the second channel, Wherein the organic light emitting display includes a dual channel thin film transistor including a gate electrode partially overlapping the organic thin film transistor. 12. The method of claim 11,
Wherein the at least one pixel comprises:
A pixel electrode electrically connected to the dual channel thin film transistor;
An organic light emitting layer on the pixel electrode; And
Further comprising an opposite electrode on the organic light emitting layer,
Wherein the dual channel thin film transistor provides a driving current to the organic light emitting layer. 12. The method of claim 11,
Wherein the first channel has at least two bent portions. 14. The method of claim 13,
Wherein the first channel has a "d" shape when viewed from a plane. 12. The method of claim 11,
And the channel length of the second channel is shorter than the channel length of the first channel. 16. The method of claim 15,
Wherein the second channel has a linear shape when viewed from a plane. 12. The method of claim 11,
Wherein the at least one pixel comprises:
A switching transistor connected to the gate line and the source line and transmitting a data signal input through the source line in response to a scan signal input through the gate line;
A capacitor for charging a voltage corresponding to the transferred data signal; And
And the dual channel thin film transistor for generating a driving current corresponding to a voltage charged in the capacitor. 18. The method of claim 17,
Wherein when the first channel or the second channel is defective, the first channel or the second channel in which a failure occurs is separated from the source region and the drain region. 19. The method of claim 18,
A pixel address of a pixel including the dual channel thin film transistor including the first channel or the second channel separated from the source region and the drain region and a channel address of a channel separated from the source region and the drain region And a memory for storing an operation mode determined according to the operation mode. 20. The method of claim 19,
A timing controller for receiving RGB data (RGB Data) from outside and generating digital image data (Data) corresponding to the RGB data;
A data correction unit that receives the digital image data Data and generates digital image data CData corrected based on the pixel address and the operation mode stored in the memory;
A source driver for generating the data signal based on the corrected digital image data CData and providing the data signal to the at least one pixel; And
And a gate driver for providing the scan signal to the at least one pixel.

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