KR20150081738A - Semiconductor device having air spacer - Google Patents

Abstract

The present invention includes a semiconductor pin which is formed on a semiconductor substrate and includes a first source and drain region, a second source and drain region, and a channel region, a gate electrode which crosses the surface of the channel region and is formed on the semiconductor substrate, a gate dielectric layer which is located between the gate electrode and the channel region, a contact plug which is in contact with the first source and drain region and the second source and drain region, and an insulation spacer with a multilayer structure to cover both sidewalls of the gate electrode. The insulation spacer includes an air spacer.

Description

Technical Field [0001] The present invention relates to a semiconductor device having an air spacer,

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a fin structure transistor.

A transistor having a pin structure for increasing the channel area of the cell transistor while increasing the degree of integration has been disclosed. The fin structure transistor has a fin structure active region that can increase the width of the effective channel within a limited area by forming a channel on the side of the active region as well as the upper surface of the active region. In such a fin structure transistor, it is necessary to suppress the parasitic capacitance between the contact plug and the gate conductor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of preventing deterioration of electrical characteristics in a miniaturized semiconductor device and maintaining reliability.

A semiconductor device according to an aspect of the present invention includes a semiconductor fin formed on a semiconductor substrate and including a first source / drain region, a second source / drain region, and a channel region; A gate dielectric layer disposed between the gate electrode and the channel region; a contact plug contacting the first source / drain region and the second source / drain region; And a multilayered insulating spacer covering both side walls of the gate electrode, wherein the insulating spacer comprises an air spacer.

In some embodiments, the insulating spacer further comprises a liner nitride film, and the air spacer may be spaced apart from the gate electrode via the liner nitride film.

In some embodiments, the insulating spacer further comprises an outer spacer on the opposite side of the gate electrode with the air spacer therebetween, and the contact plug can be self-aligned by the outer spacer.

In some embodiments, the air spacers may extend to a level higher than the top surface of the gate electrode, and the air spacers extend to a level higher than the top surfaces of the first source / drain regions and the second source / .

In some embodiments, the air spacers may extend continuously along the sidewalls of the gate electrode. The length of the air spacers in the region where the semiconductor pins are located may be shorter than the length of the air spacers in the region where the semiconductor pins are not located.

In some embodiments, the top surfaces of the first source / drain region and the second source / drain region may be located at a higher level than the top surface of the channel region. The first source / drain region and the second source / drain region and the channel region may be formed of the same material. The upper side width of the air spacers may be smaller than the lower side width of the air spacers as a direction in which the semiconductor pins extend.

The semiconductor device according to the technical idea of the present invention can reduce the parasitic capacitance due to the low dielectric constant of the air spacer by forming an air spacer between the contact plug and the gate conductor even when the semiconductor device has a highly miniaturized feature size . As the parasitic capacitance is reduced, it is possible to suppress the occurrence of problems such as a reduction in operation speed and a reduction in sensing margin, a reduction in electrical characteristics of the semiconductor device, and a high reliability of the semiconductor device can be maintained.

FIG. 1A is a perspective view showing a part of a semiconductor device according to an embodiment of the present invention. FIG.
1B is a plan view cut along the xy plane of FIG. 1A.
1C is a sectional view taken along the line C1-C1 'in FIG. 1B.
1D is a sectional view taken along the line D1-D1 'of FIG. 1B.
FIG. 2 is a cross-sectional view taken along line C1-C1 'of FIG. 1B, illustrating a semiconductor device 200 according to an embodiment of the present invention.
3 is a cross-sectional view of the semiconductor device 300 according to one embodiment of the present invention, taken along line D1-D1 'in FIG. 1B.
4 is a cross-sectional view taken along line C1-C1 'of FIG. 1B, illustrating a semiconductor device 400 according to an embodiment of the present invention.
5A to 5I are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.
6A to 6H are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.
7A to 7J are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.
8A to 8G are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof will be omitted.

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various elements, regions, layers, regions and / or elements, these elements, components, regions, layers, regions and / It should not be limited by. These terms do not imply any particular order, top, bottom, or top row, and are used only to distinguish one member, region, region, or element from another member, region, region, or element. Thus, a first member, region, region, or element described below may refer to a second member, region, region, or element without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used, predefined terms are to be interpreted as having a meaning consistent with what they mean in the context of the relevant art, and unless otherwise expressly defined, have an overly formal meaning It will be understood that it will not be interpreted.

If certain embodiments are otherwise feasible, the particular process sequence may be performed differently from the sequence described. For example, two processes that are described in succession may be performed substantially concurrently, or may be performed in the reverse order to that described.

In the accompanying drawings, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein, but should include variations in shape resulting from, for example, manufacturing processes.

FIG. 1A is a perspective view showing a part of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a plan view cut along the x-y plane of FIG. 1A. 1C is a sectional view taken along the line C1-C1 'in FIG. 1B. 1D is a sectional view taken along the line D1-D1 'of FIG. 1B.

1A to 1D, a semiconductor device 100 includes a semiconductor substrate 101, a substrate insulating layer 102, a semiconductor fin 110, a gate electrode 120, a gate dielectric layer 122, an interlayer insulating layer 130 A contact plug 140, and an insulating spacer 150.

In this example, an example in which the semiconductor device 100 is implemented using an SOI (Silicon-On-Insulator) substrate will be described. However, the technical idea of the present invention is not limited to this, and may be implemented using a bulk-type silicon substrate.

In some embodiments, the semiconductor substrate 101 may be made of silicon. The substrate insulating layer 102 may be an oxide film.

The semiconductor fin 110 may be made of Si, Ge, SiGe, SiC, GaAs, InAs, InP, or a combination thereof.

The semiconductor fin 110 includes a first source / drain region 110a, a second source / drain region 110b, and a channel region 110c.

The first source / drain region 110a and the second source / drain region 110b and the channel region 110c may be formed of the same material, as described later with reference to FIG. 5E. The first source / drain region 110a and the second source / drain region 110b and the channel region 110c may be formed of different materials.

The first source / drain region 110a and the second source / drain region 110b are formed by selective epitaxial growth (SEG) of the base semiconductor fin 110x, .

In some embodiments, the top surface 110aT of the first source / drain region 110a and the top surface 110bT of the second source / drain region 110b are located at a level higher than the top surface 110cT of the channel region 110c can do.

The gate electrode 120 is formed on the substrate insulating layer 102 across the surface of the channel region 110c of the semiconductor fin 110. [ In some embodiments, the height 120h1 of the gate electrode 120 in the region where the semiconductor fin 110 is not located in the gate electrode 120 is greater than the height 120h1 of the gate electrode 120 in the region where the semiconductor fin 110 is located. Is higher than the height 120h2 of the electrode 120.

A gate dielectric layer 122 may be interposed between the gate electrode 120 and the substrate insulation layer 102 or between the gate electrode 120 and the channel region 110c. That is, the gate dielectric layer 122 is located on the lower surface of the gate electrode 120. In some embodiments, the gate dielectric 122 may be silicon oxide. However, the gate dielectric layer 122 is not limited thereto, and may be made of a high dielectric material such as hafnium oxide, lanthanum oxide, or a combination thereof.

The interlayer insulating film 130 is formed to cover the gate electrode 120 and the insulating spacer 150. The interlayer insulating film 130 may be, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

The contact plug 140 contacts the first source / drain region 110a and the second source / drain region 110b. In some embodiments, the contact plug 140 may be a bit line contact (DC) or a buried contact (BC). Although not shown, in some embodiments the bit line contacts are electrically connected to bit lines (not shown) that may be formed in a subsequent process, and the storage contacts are electrically connected to capacitors (not shown) .

The insulating spacers 150 may have a multi-layer structure that covers both sidewalls of the gate electrode 120. In some embodiments, insulating spacer 150 includes air spacers 150a and outer spacers 150b.

An air spacer 150a filled with air is formed between the outer spacers 150b and the gate electrode 120 as shown in FIG. As described above, parasitic capacitance generated between the gate electrode 120 and the contact plug 140 is reduced by filling air having a low dielectric constant between the gate electrode 120 and the contact plug 140.

In some embodiments, the air spacers 150a may extend to a level higher than the top surface 120T of the gate electrode 120. The air spacers 150a may extend to a level higher than the upper surface 110aT of the first source / drain region 110a and the upper surface 110bT of the second source / drain region 110b.

In some embodiments, the air spacers 150a extend continuously along the sidewalls of the gate electrode 120. Here, the length 150h2 of the air spacer in the region where the semiconductor fin 110 is located in the air spacer 150a may be shorter than the length 150h1 of the air spacer in the region where the semiconductor fin 110 is not located.

The upper width D1 of the air spacers 150a may be smaller than the lower width D2 of the air spacers 150a in the direction in which the semiconductor pins 110 extend.

The outer spacers 150b are formed on the opposite side of the gate electrode 120 with the air spacers 150a therebetween. The outer spacers 150b may be formed by the manufacturing process described later in FIG. In some embodiments, the outer spacers 150b may be the same material as the interlayer insulating layer 130. [ In another embodiment, the outer spacers 150b may be a material different from the interlayer insulating film 130. [ For example, the outer spacers 150b may be an oxide film, a nitride film, an oxynitride film, or a combination thereof.

FIG. 2 is a cross-sectional view taken along line C1-C1 'of FIG. 1B, illustrating a semiconductor device 200 according to an embodiment of the present invention. In Fig. 2, the same reference numerals as in Figs. 1A to 1D denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

2, the semiconductor device 200 includes a semiconductor substrate 101, a substrate insulating layer 102, a gate electrode 120, a gate dielectric layer 122, an interlayer insulating layer 230, a contact plug 140, And includes a spacer 250.

The interlayer insulating film 230 is formed to cover the gate electrode 120 and the insulating spacer 250. The interlayer insulating film 230 may be, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

The insulating spacer 250 includes an air spacer 250a, an outer spacer 250b, and a liner nitride film 250c.

As shown in FIG. 2, the air spacers 250a are spaced apart from the gate electrode 120 with the liner nitride film 250c interposed therebetween.

The outer spacer 250b is formed on the opposite side of the gate electrode 120 with the air spacer 250a and the liner nitride film 250c interposed therebetween. The outer spacers 250b may be formed by the manufacturing process described later in FIG. 6E. In some embodiments, the outer spacers 250b may be the same material as the interlayer insulating layer 230. [ In another embodiment, the outer spacers 250b may be a different material from the interlayer insulating layer 230. [ For example, the outer spacers 250b may be an oxide film, a nitride film, an oxynitride film, or a combination thereof.

The liner nitride film 250c may be made of silicon nitride or silicon oxynitride. However, the present invention is not limited to this, and the liner nitride film 250c may include other materials within the technical scope of the present invention.

Since the insulating spacer 250 includes the liner nitride film 250c, it is possible to prevent damage to the gate electrode 120 that may occur in the process of forming the air spacer 250a.

3 is a cross-sectional view of the semiconductor device 300 according to one embodiment of the present invention, taken along line D1-D1 'in FIG. 1B. In Fig. 3, the same reference numerals as in Figs. 1A and 2 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

3, the semiconductor device 300 includes a semiconductor substrate 101, a substrate insulation layer 102, a semiconductor fin 110, a gate electrode 120, a gate dielectric layer 122, a high-k dielectric layer 324, An insulating film 130, a contact plug 140, and an insulating spacer 150.

In some embodiments, the high-k film 324 may be interposed between the gate electrode 120 and the gate dielectric layer 122 (see FIG. 7D).

The high-k dielectric layer 324 may be made of a material having a dielectric constant larger than that of the silicon oxide layer. For example, the high-k dielectric layer 324 may be made of hafnium oxide, lanthanum oxide, or the like. However, it is needless to say that the high-k dielectric layer 324 is not limited thereto but may be made of another material.

4 is a cross-sectional view taken along line C1-C1 'of FIG. 1B, illustrating a semiconductor device 400 according to an embodiment of the present invention. In FIG. 4, the same reference numerals as in FIGS. 1A to 3 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

4, the semiconductor device 400 includes a semiconductor substrate 101, a substrate insulating layer 102, a gate electrode 120, a gate dielectric layer 122, an interlayer insulating layer 430, a contact plug 440, And includes a spacer 450.

The interlayer insulating film 430 is formed to cover the gate electrode 120 and the insulating spacer 450. The interlayer insulating film 430 may be, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

In some embodiments, the contact plugs 440 may be self-aligned by the outer spacers 450b. That is, the contact plug 440 may be formed by a Self Align Contact (SAC) process.

The self-aligned contact (SAC) process is a process of using an outer spacer 450b formed on the sidewall of the gate electrode 120 as an etch mask during anisotropic etching for forming the contact plug 440, It is possible not only to increase the alignment margin but also to reduce the separation distance between the gate electrodes in the fabrication of the memory device and the like, thereby improving the degree of integration of the semiconductor device.

Insulation spacers 450 include an air spacer 450a and an outer spacer 450b. In some embodiments, air spacers 450a and outer spacers 450b may be formed by the fabrication process described below in Figures 8A-8G.

5A to 5I are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. In Figs. 5A to 5I, the same reference numerals as in Figs. 1A to 4 denote the same members, and a duplicate description thereof will be omitted for the sake of brevity.

Referring to FIG. 5A, a base semiconductor pin 110x is formed on a substrate insulation layer 102. [0064] FIG. The base semiconductor fin 110x may be formed by an etching process. In this example, the process of forming the base semiconductor fin 110x by using the SOI substrate is described as an example, but the semiconductor fin 110x may be formed using the bulk silicon substrate within the scope of the technical idea of the present invention.

Referring to FIG. 5B, a gate dielectric layer 122x is formed to cover the substrate insulation layer 102 and the base semiconductor fin 110x. The gate layer 120x is formed so as to cover the gate dielectric film 122x. In some embodiments, the gate dielectric layer 122x and the gate layer 120x may be formed by a deposition process. After the formation of the gate layer 120x, a chemical mechanical polishing (CMP) process can be performed.

Referring to FIG. 5C, a gate mask 126 is formed in the gate layer 120x where the gate electrode 120 is to be located. The gate mask 126 may be an oxide film. The exposed gate layer 120x and the gate dielectric layer 122x are etched using the gate mask 126 as an etch mask.

Referring to FIG. 5D, a sacrificial layer (not shown) covering both side walls of the gate electrode 120 is formed. The sacrificial film is formed of a material having a high etch selectivity in relation to the gate mask 126. Also, the sacrificial film is formed of a material that can be easily removed through a wet etching process. As the material that can be used as a sacrificial film, for example, silicon germanium or silicon nitride can be cited. Thereafter, a sacrificial spacer 550 is formed by anisotropically etching the sacrificial layer. The sacrificial spacer 550 is not present in the portion of the base semiconductor fin 110x but may be present only in the portion of the gate electrode 120 by adjusting the etching process time of the sacrifice layer.

Referring to FIG. 5E, the semiconductor fin 110 is formed by selective epitaxial growth (SEG) of a portion of the base semiconductor fin 110x exposed to the outside of the finished product after the processes 5a to 5d described above. That is, the semiconductor fin 110y is coupled to the base semiconductor fin 110x through the selective epitaxial growth process to form the semiconductor fin 110 (see FIG. 1D).

There are various methods for selective epitaxial growth. In the case of homoepitaxy, the base semiconductor pin 110x and the semiconductor fin 110y may be the same material. On the other hand, in the case of heteroepitax, the base semiconductor pin 110x and the semiconductor fin 110y may be silicon having different compositions.

The selective epitaxial growth can be realized by a reduced pressure chemical vapor deposition method or a low pressure chemical vapor deposition method. Selective epitaxial growth can use hydrogen gas as the flow gas.

The semiconductor fin 110 may include a first source / drain region 110a and a second source / drain region 110b. The first source / drain region 110a and the second source / drain region 110b may be formed, for example, through an ion implantation process.

Referring to FIGS. 5F and 5G, after the outer spacers 150b covering the sacrificial spacers 550 are formed, the sacrificial spacers 550 are removed. As shown, the outer spacer 150b is formed such that the top surface of the sacrificial spacer 550 is exposed. That is, the height from the substrate insulating layer 102 to the upper surface of the outer spacer 150b is lower than the height from the substrate insulating layer 102 to the upper surface of the sacrificial spacer 550. The process of removing the sacrificial spacers 550 may be performed through a selective wet etching process.

Referring to FIG. 5H, an interlayer insulating film 130x is formed to cover an upper portion of the result of the above-described processes 5a to 5g. In some embodiments, the interlayer insulating film 130x may be formed by a PVD process. The interlayer insulating film 130x is formed so as not to fill the portion where the sacrificial spacers 650 are removed, so that the insulating spacer 150 has the air spacers 150a. After the interlayer insulating film 130x is formed, a CMP process can be performed. The interlayer insulating layer 130x may penetrate into the air spacers 150a to cover the sidewalls of the gate electrode 120 during formation of the interlayer insulating layer 130x as shown in FIG. The technical idea is not necessarily limited to that shown in FIG. 5H.

Referring to FIG. 5I, a predetermined portion of the interlayer insulating film 130x is etched, and a contact plug 140 is formed by depositing a conductive material.

By using the above-described processes, it is possible to manufacture a semiconductor device in which the parasitic capacitance is reduced between the conductive patterns.

6A to 6H are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. 6A to 6H, the same reference numerals as in Figs. 1A to 5I denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

Referring to FIG. 6A, a base semiconductor fin 110x, a gate electrode 120, a gate dielectric layer 122, and a gate mask 126 are formed on a substrate insulation layer 102. As shown in FIG. This process can be performed similarly to the processes of Figs. 5A to 5C described above.

Referring to FIG. 6B, a liner nitride film 250c covering both side walls of the gate electrode 120 is formed, and a sacrificial spacer 650 is formed to cover the liner nitride film 250c. The formation process of the sacrificial spacers 650 may be performed in a manner similar to that described above with reference to FIG. 5D.

Referring to FIG. 6C, a semiconductor fin 110 is formed through a selective epitaxial growth process, and a first source / drain region 110a and a second source / drain region 110b are formed through an ion implantation process. The formation process of the semiconductor fin 110 may be performed in a manner similar to that described above with reference to FIG. 5E.

6D and 6E, after forming the outer spacers 250b covering the sacrificial spacers 650, the sacrificial spacers 650 are removed. Such a process can be performed similarly as described above in Figs. 5F and 5G.

Referring to FIG. 6F, an interlayer insulating film 230x is formed to cover an upper portion of the resultant process of FIGS. 6A to 6E. The interlayer insulating film 230x is formed so as not to fill the portion where the sacrificial spacer 650 is removed, so that the insulating spacer 250 has the air spacers 250a.

The interlayer insulating layer 230x forming material may penetrate into the air spacers 250a to cover the side walls of the gate electrode 120 during the formation of the interlayer insulating layer 230x as shown in FIG. The technical idea is not necessarily limited to that shown in FIG. 6F.

6G, in order to form the contact plug 140, a part of the interlayer insulating film 230x is etched. Thereafter, a contact plug 140 is formed which contacts each of the exposed first source / drain region and the second source / drain region, and a CMP process can be additionally performed.

7A to 7J are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. In Figs. 7A to 7J, the same reference numerals as in Figs. 1A to 6G denote the same members, and a duplicate description thereof will be omitted for the sake of brevity.

Referring to FIG. 7A, a base semiconductor pin 110x is formed on a substrate insulation layer 102. FIG. This process can be performed similarly as described above in Fig. 5A.

7B to 7D, a sacrifice film 752a is formed so as to cover the upper surface of the base semiconductor fin 110x and the substrate insulating layer 102. As shown in FIG. As the material that can be used as the sacrifice film 752a, for example, silicon germanium or silicon nitride can be cited.

Thereafter, the sacrifice film 752a of the portion of the gate electrode 120 to be formed in the subsequent process is etched to form the sacrifice film 752b.

The gate dielectric layer 122, the high-k dielectric layer 324 and the gate electrode 120 are formed on the exposed substrate insulation layer 102 after the sacrifice layer 752b is formed. The gate dielectric layer 122, the high-k dielectric layer 324 and the gate electrode 120 may be performed by a deposition process.

Thereafter, the CMP process is performed so that the top surface of the sacrifice film 752b is exposed, and then the sacrifice film 752b is removed. The sacrificial film 752b may be removed through an etching process.

7E, a sacrificial spacer 750a covering both side walls of the gate electrode 120 is formed. The fabrication process of the sacrificial spacer 750a may be performed similar to that described above in Fig. 5D.

Referring to FIG. 7F, the semiconductor fin 110 is formed by selective epitaxial growth of the portion of the base semiconductor fin 110x exposed to the outside of the resultant process of FIG. 7A to FIG. 7F, 1 source / drain region 110a and a second source / drain region 110b. The formation process of the semiconductor fin 110 may be performed in a manner similar to that described above with reference to FIG. 5E.

After forming the semiconductor fin 110, a sacrificial spacer 750b is formed. The sacrificial spacer 750b is formed to cover the sacrificial spacer 750a, and the fabrication process can be performed similarly to that described above in Fig. 5D.

Referring to Figures 7G and 7H, after forming the outer spacers 150b covering the sacrificial spacers 750b, the sacrificial spacers 750b are removed. As shown, the outer spacer 150b is formed such that the upper surface of the sacrificial spacer 750b is exposed. That is, the height from the substrate insulating layer 102 to the upper surface of the outer spacer 150b is lower than the height from the substrate insulating layer 102 to the upper surface of the sacrificial spacer 750b. The process of removing the sacrificial spacers 750b may be performed through a selective wet etching process.

Referring to FIG. 7I, an interlayer insulating film 130x is formed to cover an upper portion of the resultant product of steps 7a to 7h. The interlayer insulating film 130x is formed so as not to fill the portion where the sacrificial spacer 750b is removed, so that the insulating spacer 150 has the air spacers 150a. As shown in FIG. 7I, during formation of the interlayer insulating layer 130x, the interlayer insulating layer 130x may penetrate into the air spacers 150a to cover the side walls of the gate electrode 120. However, The technical idea is not necessarily limited to that shown in Fig. 7i.

After the interlayer insulating film 130x is formed, a CMP process can be performed.

Referring to FIG. 7J, a part of the interlayer insulating film 130x is etched to form the contact plug 140. Next, as shown in FIG. Thereafter, a contact plug is formed that contacts each of the exposed first source / drain region and the second source / drain region, and a CMP process may be further performed.

8A to 8G are perspective views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. In Figs. 8A to 8H, the same reference numerals as in Figs. 1A to 7K denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

Referring to FIG. 8A, a base semiconductor pin 110x and a sacrifice layer 752b are formed on a substrate insulation layer 102. [ This process can be performed similarly to the processes of Figs. 7A to 7C described above.

8B, a gate dielectric layer 122, a high-k dielectric layer 324, a gate electrode 120, and a nitride layer 826 are formed on the exposed substrate insulation layer 102 after forming the sacrifice layer 752b, The film 752b is removed. The gate dielectric layer 122, the high-k dielectric layer 324, the gate electrode 120, and the nitride layer 826 may be formed by a deposition process. The CMP process may be performed prior to the etching process of the sacrifice film 752b.

Referring to FIG. 8C, a nitride spacer 850a is formed to cover both side walls of the gate electrode 120. As shown in FIG. The manufacturing process of the nitride spacer 850a may be performed similarly as described above in Fig. 5D.

8D, a semiconductor fin 110 is formed by selective epitaxial growth of a portion of the base semiconductor fin 110x exposed to the outside of the resultant process of FIG. 8A to FIG. 8C, 1 source / drain region 110a and a second source / drain region 110b. The formation process of the semiconductor fin 110 may be performed in a manner similar to that described above with reference to FIG. 5E.

After the semiconductor fin 110 is formed, a nitride spacer 850b is formed. The nitride spacer 850b is formed so as to cover the nitride spacer 850a, and the manufacturing process can be performed similarly to that described above in Fig. 5D.

Referring to FIG. 8E, an interlayer insulating film 430x is formed to cover an upper portion of the resultant product of steps 8a to 8d. After the interlayer insulating film 430x is formed, a CMP process can be performed.

Referring to FIG. 8F, a part of the interlayer insulating film 430x is etched to form a contact hole (not shown). The contact holes are formed by self-alignment by the nitride spacer 850b. When the contact holes are formed by self-alignment, the alignment margin can be increased and the degree of integration of the unit cells can be increased. A contact plug 440 is formed in the contact hole. The contact plug 440 contacts the first source / drain region and the second source / drain region, respectively. After the formation of the contact plug 440, a CMP process may be additionally performed.

Referring to FIG. 8G, the nitride film 826 and the nitride spacers 850a and 850b are removed through an etching process. Silicon oxide is then deposited in the space from which the nitride film 826 and the nitride spacers 850a and 850b are removed to form the air spacers 450a, the outer spacers 450b, and the interlayer insulating film 430. In some embodiments, the outer spacers 450b and the interlayer insulating film 430 may be the same material. The outer spacers 450b and the interlayer insulating film 430 may be, for example, silicon oxide.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100: semiconductor element
101: semiconductor substrate 102: substrate insulating layer
110: semiconductor pin
110a: first source / drain region 110b: second source / drain region
120: gate electrode 122: gate dielectric film
130: interlayer insulating film 140: contact plug
150: Insulation spacer 150a: Air spacer
150b: outer spacer 250c: liner nitride film
324: high dielectric constant film

Claims (10)

A semiconductor fin formed on the semiconductor substrate and including a first source / drain region, a second source / drain region, and a channel region;
A gate electrode traversing the surface of the channel region and formed on the semiconductor substrate;
A gate dielectric layer positioned between the gate electrode and the channel region,
A contact plug in contact with the first source / drain region and the second source / drain region,
And an insulating spacer having a multi-layer structure covering both side walls of the gate electrode,
Wherein the insulating spacer comprises an air spacer. The method according to claim 1,
Wherein the insulating spacer further comprises a liner nitride film.
3. The method of claim 2,
Wherein the air spacer is spaced apart from the gate electrode with the liner nitride film interposed therebetween. The method according to claim 1,
Wherein the insulating spacer further comprises an outer spacer on the opposite side of the gate electrode with the air spacer therebetween,
And the contact plug is self-aligned by the outer spacers. The method according to claim 1,
Wherein the air spacers extend to a level higher than the upper surface of the gate electrode. The method according to claim 1,
And the air spacers extend to a level higher than the upper surfaces of the first source / drain region and the second source / drain region. The method according to claim 1,
Wherein the air spacers extend continuously along a sidewall of the gate electrode. 8. The method of claim 7,
Wherein a length of the air spacers in the region where the semiconductor pins are located is shorter than a length of air spacers in the region where the semiconductor pins are not located. The method according to claim 1,
Drain regions and upper surfaces of the first source / drain regions and the second source / drain regions are located at a level higher than the upper surface of the channel region,
Wherein the first source / drain region and the second source / drain region and the channel region are made of the same material. The method according to claim 1,
Wherein an upper width of the air spacers is smaller than a lower width of the air spacers along a direction in which the semiconductor pins extend.

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