KR20150065125A - A Semiconductor Device - Google Patents

Abstract

A semiconductor device including a conductive layer structure with copper includes a bottom interlayer dielectric layer, a stopper layer, and a top interlayer dielectric layer which are successively stacked on a substrate. A first bottom conductive layer and a second bottom conductive layer are separately provided on the bottom interlayer dielectric layer. Provided are a first top via plug which passes through the top interlayer dielectric layer and the stopper layer and is connected to a first bottom conductive layer and a second top via plug which is connected to a second bottom conductive layer. Provided is at least one line type shield via plug which passes through the interlayer dielectric layer and the stopper layer between the first top via plug and the second top via plug and is extended in the bottom interlayer dielectric layer. The shield via plug is electrically floated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a conductive layer structure including copper.

Resistance of conductive layers used in a semiconductor device which is gradually increasing in performance has been lowered along with miniaturization of the pattern. Accordingly, the conductive layers for the wiring of the semiconductor device use metal. Particularly, copper having a low resistance among metals is attracting attention. However, copper has difficulties in application due to the phenomenon of electronic migration, and methods for preventing the diffusion due to the electronic migration of copper are being sought.

A problem to be solved by the present invention is to provide a semiconductor device including a structure for preventing the shorting of conductive layers by copper diffusion through a gap at an interface between an interlayer insulating layer and a stopper layer.

Another object of the present invention is to provide a semiconductor device including a structure for preventing copper from diffusing from a chip guard ring surrounding a main chip to a main chip region.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a lower interlayer insulating layer, a first stopper layer, and an upper interlayer insulating layer sequentially stacked on a substrate; A first lower conductive layer and a second lower conductive layer disposed in the lower interlayer insulating layer and separated laterally; A first upper via plug passing through the upper interlayer insulating layer and the first stopper layer and connected to the first lower conductive layer, and a second upper via plug connected to the second lower conductive layer; And at least one shield via plug extending through the first stopper layer between the first upper via plug and the second upper via plug and extending from the upper insulating layer to the lower interlayer insulating layer, The via plug is a line-like pattern in plan view and can include a conductive film and can be electrically floated.

The apparatus includes a first upper conductive layer disposed on the upper interlayer dielectric layer and connected to the first upper via plug, a second upper conductive layer connected to the second upper via plug, and a second upper conductive layer connected to the shield via plug And a third upper conductive layer formed on the second upper conductive layer.

The shield via plug may surround the side wall of the second upper via plug and the side wall of at least a part of the second lower conductive layer.

The first lower conductive layer and the second lower conductive layer may include copper.

The shield via plug may include a conductive film and a via insulating film disposed at least on the sidewall thereof.

The shield via plug may include a conductive film and a via insulating film disposed under the conductive film.

The lower interlayer insulating layer may include a first interlayer insulating layer, a second stopper layer, and a second interlayer insulating layer between the second stopper layer and the first stopper layer, which are sequentially stacked on the substrate.

The shield via plug passes through the first stopper layer, the second interlayer insulating layer, and the second stopper layer, and may extend from the upper interlayer insulating layer into the first interlayer insulating layer.

The apparatus may further include a first lower via plug disposed in the lower interlayer insulating layer and connected to the first lower conductive layer, and a second lower via plug connected to the second lower conductive layer.

According to another aspect of the present invention, a semiconductor device includes a main chip region, a scribelane region, and a chip boundary region between the main chip region and the scribelane region. A plurality of interlayer insulating layers including a stopper layer provided on the substrate; A conductive structure disposed in the plurality of interlayer insulating layers provided in the main chip area; A chip guard ring disposed in the plurality of interlayer insulating layers provided in the chip boundary region and continuously surrounding the main chip region and connected to the substrate; And a plurality of interlayer dielectric layers disposed continuously between the chip guard ring and the main chip region and surrounding the main chip region, the portion of the plurality of interlayer dielectric layers including the at least one stopper layer, The shield via plug including a conductive via, the shield via plug including a conductive material and being electrically floated.

The plurality of shield via plugs may be disposed in the chip boundary region.

The chip guard ring and the conductive structure may include a conductive layer including copper.

Wherein the interlayer insulating layer includes a lower interlayer insulating layer, a first stopper layer, and an upper interlayer insulating layer sequentially stacked on the substrate, wherein the shield via plug passes through the first stopper layer, And may extend into the lower interlayer insulating layer.

Wherein the conductive structure and the chip guard ring each include a lower via plug and a lower conductive layer which are sequentially disposed in the lower interlayer insulating layer and which are stacked in order and which are connected to the lower conductive layer through the upper interlayer insulating layer and the first stopper layer An upper via plug disposed on the upper interlayer insulating layer, and an upper conductive layer connected to the upper via plug.

Wherein the plurality of interlayer insulating layers comprise a first interlayer insulating layer, a first stopper layer, a second interlayer insulating layer, a second stopper layer, and a third interlayer insulating layer which are sequentially stacked on the substrate, May extend through the third interlayer insulating layer and the second stopper layer, the second interlayer insulating layer, and the first stopper layer and into the first interlayer insulating layer.

Wherein the conductive structure and the chip guard ring each comprise a lower via plug disposed in the first interlayer insulating layer and the first stopper layer, a lower conductive layer connected to the lower via plug and disposed in the second interlayer insulating layer, An upper via plug connected to the lower conductive layer and passing through the second stopper layer and the third insulating layer, and an upper conductive layer connected to the upper via plug and disposed on the third interlayer insulating layer .

The shield via plug may include a conductive film, a via insulating film disposed at least on the sidewall thereof, or a conductive film and a via insulating film disposed under the conductive film.

According to another aspect of the present invention, there is provided a semiconductor device including a main chip region, a scribe region, and a chip boundary region between the main chip region and the scribe region, A plurality of interlayer insulating layers including at least one stopper layer provided in the main chip region, a first via-under plug disposed in the plurality of interlayer-insulating layers provided in the main chip region and connected to the substrate, And a first upper plug connected to the first conductive layer and disposed on the first conductive layer, the conductive structure including a first conductive layer, And a second lower via disposed in the plurality of interlayer insulating layers provided in the region and continuously surrounding the main chip region, A plug, a second conductive layer connected to the second lower via plug and disposed on the second lower via plug, and a second upper via connected to the second conductive layer, A chip guard ring that includes a plug and a conductive ring that continuously surrounds the conductive structure and is disposed between the chip guard ring and the conductive structure and penetrates a portion of the plurality of interlayer dielectric layers including the at least one stopper layer And a shield via plug spaced apart from the substrate, wherein the shield via plug includes the same conductive material as the second upper via plug and can be electrically floated.

The shield via plug may have a lower surface than an upper surface of the second conductive layer.

The upper surface of the shield via plug may be substantially flush with the upper surface of the second upper via plug, and the height of the shield via plug may be greater than the height of the second upper via plug.

The details of other embodiments are included in the detailed description and drawings.

The semiconductor device according to the present invention can prevent diffusion of copper through a gap formed between the interface between the stopper layer and the interlayer insulating layer, thereby effectively preventing electrical shorting between the conductive layers.

1 is a plan view schematically showing a semiconductor device according to one embodiment of the present invention.
FIG. 2A is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention taken along a line I-I 'in FIG. 1, and FIG. 2B is an enlarged view of a portion "A"
3 is a plan view showing a modification of the semiconductor device according to the embodiment of the present invention.
4 to 9 are cross-sectional views schematically showing semiconductor devices according to another embodiment of the present invention, taken along the line II 'in FIG.
10 and 11 are cross-sectional views schematically showing a semiconductor device according to still another embodiment of the present invention.
12 is a plan view schematically showing a semiconductor device according to still another embodiment of the present invention.
13 and 14 are cross-sectional views schematically showing semiconductor devices according to still another embodiment of the present invention, taken along line II-II 'in FIG.
15 and 16 are cross-sectional views schematically showing semiconductor devices according to still another embodiment of the present invention.
FIGS. 17 to 21 are cross-sectional views schematically showing semiconductor devices according to still another embodiment of the present invention, taken along line II-II 'of FIG.
22 is a schematic block diagram showing an electronic system including a semiconductor device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention, and FIG. 2B is an enlarged view of a portion "A" in FIG. 2A. 3 is a schematic plan view showing a modification of the semiconductor device according to an embodiment of the present invention.

1, 2A, and 2B, a semiconductor device includes a lower interlayer insulating layer 20 formed on a substrate 10, a first stopper layer 32, an upper interlayer insulating layer 36, The structure 60 may include a second conductive structure 62 and a shield via structure 64 between the first conductive structure 60 and the second conductive structure 62. [ The substrate 10 may be a substrate comprising a semiconductor material. The semiconductor material may comprise, for example, a material containing silicon. The substrate 10 may include a direct circuit (not shown). The integrated circuit may include a transistor. The substrate 10 may include at least one insulating film and at least one conductive layer and a via plug formed therein. Each of the interlayer insulating layers 20 and 36 may include a plurality of stacked insulating films. The interlayer insulating layers 20 and 36 may be formed of a silicon oxide containing a small amount of impurities or a silicon oxide not containing an impurity. For example, each of the interlayer insulating layers 20 and 26 may be formed of boron silicate glass (BSG), phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), silicon oxyfluoride (SiOF), silicon carbonic hydrooxide ), Tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), or the like. The interlayer insulating layers 20 and 36 may be formed by various deposition methods including a chemical vapor deposition method using thermal or plasma or a spin coating method.

The first stopper layer 32 may be formed of a material having an etch selectivity with respect to the interlayer insulating layers 20 and 36. For example, the first stopper layer 32 may serve as an etching stopper for preventing the first and second lower conductive layers 44a and 44b from being etched when the upper interlayer insulating layer 36 is etched. The first stopper layer 32 may be formed of an insulating material harder than the silicon oxide film. For example, the first stopper layer 32 may comprise silicon nitride, silicon carbide nitride, or silicon oxynitride. The interlayer insulating layers 20 and 36 may be thicker than the first stopper layer 32.

The first conductive structure 60 includes a first lower via plug 40a, a first lower conductive layer 44a, a first upper via plug 48a, and a first upper conductive layer 56a stacked in that order . The second conductive structure 62 may include a second lower via plug 40b, a second lower conductive layer 44b, a second upper via plug 48b, and a second upper conductive layer 56b. The first conductive structure 62 and the second conductive structure 60 may be spaced apart from each other in the second direction D2 as shown in FIG. The first lower via plug 40a and the first lower conductive layer 44a may be disposed in the lower interlayer insulating layer 20. [ The first lower via-plug 40a may be connected to the substrate 10. For example, the first lower via-plug 40a may be connected to the integrated circuit of the substrate 10. On the other hand, the first lower via-plug 40a can be connected to the integrated circuit of the substrate 10 through at least one conductive layer and a via plug disposed thereunder. The first lower conductive layer 44a is connected to the first lower via plug 40a and may be a line-shaped wiring extending in the first direction D1 as shown in FIG. On the other hand, the first lower conductive layer 44a may be a wiring extending in a direction different from the first direction D1. The upper surface of the first lower conductive layer 44a may be substantially coplanar with the upper surface of the lower interlayer insulating layer 20. [ The first upper via plug 48a may be connected to the first lower conductive layer 44a through the upper interlayer insulating layer 36 and the first stopper layer 32. [ For example, the first upper via plug 48a includes a first via trench 38a formed through the upper interlayer insulating layer 36 and the first stopper layer 32 formed on the first lower conductive layer 44a, As shown in Fig. A first upper conductive layer 56a may be formed on the upper interlayer insulating layer 36 to be connected to the first upper via plug 48a. 1, the first upper conductive layer 56a may be formed to be longer than the first lower conductive layer 44a in the first direction D1. However, the first upper conductive layer 56a may not be limited to the first lower conductive layer 44a, Or may extend in a direction different from the first direction D1.

The second lower via plug 40b and the second lower conductive layer 44b of the second conductive structure 62 may be disposed in the lower interlayer insulating layer 20. [ The second lower via-hole plug 40b may be connected to the substrate 10. For example, the second lower via-hole plug 40b may be connected to a direct circuit formed on the substrate 10. [ On the other hand, the second lower via-hole plug 40b can be connected to the integrated circuit of the substrate 10 through at least one conductive layer and a via plug disposed thereunder. The second lower conductive layer 44b may be connected to the second lower via plug 40b and may be a line-shaped wiring extending in a first direction D1 as shown in FIG. 1. However, the second lower conductive layer 44b is not limited thereto, And may extend in a direction different from the direction D2. The upper surface of the second lower conductive layer 44b may be substantially coplanar with the upper surface of the lower interlayer insulating layer 20. [ The second upper via plug 48b may be connected to the second lower conductive layer 44b through the upper interlayer insulating layer 36 and the first stopper layer 32. [ For example, the second upper via plug 48b includes a second via trench 38b formed through the first stopper layer 32 formed on the upper interlayer insulating layer 36 and the second lower conductive layer 44b, As shown in Fig. A second upper conductive layer 56b connected to the second upper via plug 48b may be formed on the upper interlayer insulating layer 36. [ 1, the second upper conductive layer 56b may be formed to be longer than the second lower conductive layer 44b in the first direction D1. However, the second upper conductive layer 56b may be formed of the second lower conductive layer 44b, Or may extend in a direction different from the first direction D1.

The via plugs 40a, 40b, 48a and 48b of the first and second conductive structures 60 and 62 may be in the shape of a hole. Further, the via plugs 40a, 40b, . For example, the conductive film may include tungsten (W). Each of the via plugs 40a, 40b, 48a, 48b may further include a barrier film surrounding the conductive film. For example, the barrier film may comprise titanium (Ti), titanium nitride (TIN), or tungsten nitride (WN). The first lower conductive layer 44a of the first conductive structure 60 and the second lower conductive layer 44b of the second conductive structure 62 may be a metal conductive layer. For example, the first and second lower conductive layers 44a and 44b may include copper (Cu). On the other hand, the first and second lower conductive layers 44a and 44b may further include a barrier film including a material such as titanium (Ti), titanium nitride (TiN), or tungsten nitride (WN) And the second lower conductive layers 44a and 44b include copper, diffusion prevention of copper at the interface between the lower interlayer insulating layer 20 and the first stopper layer 32 may be required. The difference in thermal stress between the interlayer insulating layers 20 and 36 containing oxide and the first stopper layer 32 including nitride may be large. Furthermore, if the adhesion of the first stopper layer 32 on the upper surface of or around the first lower conductive layer 44a of the first conductive structure 60 is weakened, the semiconductor device including the conductive structures 60 and 62 The first stopper layer 32 may be excited and a gap 33 may be generated as shown in FIG. 2B due to the thermal stress difference. Copper of the first lower conductive layer 44a is diffused through the gap 33 and electrical failure may occur in which the first lower conductive layer 44a and the second lower conductive layer 44b are short-circuited. The formation of the gap 33 between the lower interlayer insulating layer 20 and the first stopper layer 32 may be suppressed and the shield via structure 64 may be required to prevent diffusion of copper.

The shield via structure 64 may be disposed between the first conductive structure 60 and the second conductive structure 62 separated from each other in the second direction D2. Although FIGS. 1 and 2A are shown as being formed at the central portion between the first conductive structure 60 and the second conductive structure 62, they are not necessarily shown at the center. The shield via structure 64 may include a shield via plug 46 and a third upper conductive layer 58. The shield via plug 46 penetrates through the upper interlayer insulating layer 36 and the first stopper layer 32 between the first upper via plug 48a and the second upper via plug 48b to form the lower interlayer insulating layer 20 As shown in Fig. The lower surface of the shield via plug 46 may be lower than the upper surface of the lower interlayer insulating layer 20. [ Therefore, the lower surface of the shield via plug 46 can be lower than the upper surface of the first lower conductive layer 44a. The shield via plug 46 may be elongated in a first direction D1 in a line-like pattern in plan view as shown in Fig. The shield via plug 46 may be formed longer than the first lower conductive layer 44a. The shield via plug 46 may be formed in the third via trench 40. The third via trench 40 may be formed between the first via trench 38a and the second via trench 38b by an upper interlayer insulating layer 36 and the first stopper layer 32 and extend into the lower interlayer insulating layer 20. For example, the third via trench 40 may be formed simultaneously with the same process when the first and second via trenches 38a and 38b are formed. During the etching process for the upper interlayer dielectric layer 36 and the first stopper layer 32 to form the first via trench 38a, the second via trench 38b and the third via trench 40, You can proceed with each angle. At this time, since the region where the third via trench 40 is to be formed has no conductive layer, the lower interlayer insulating layer 20 can be further etched. For example, the lower interlayer insulating layer 20 may be etched deeper than the upper surface of the first lower conductive layer 44a. Furthermore, the lower interlayer insulating layer 20 can be etched deeper than the lower surface of the first lower conductive layer 44a. The third via trench 40 can extend into the lower interlayer insulating layer 20 through the interface vertically between the lower interlayer insulating layer 20 and the first stopper layer 32 which is the path of copper diffusion. In addition, the third via trenches 40 may be formed longer in the first direction D1 than the first lower conductive layer 44a. The shield via plug 46 may include a conductive film filling the third via trench 40. The conductive film of the shield via plug 46 may be the same conductive film as the first and second upper via plugs 48a and 48b. That is, the shield via plug 46 may include tungsten (W). Further, the shield via plug 46 may further include a barrier film surrounding the conductive film. For example, the barrier film may comprise titanium (Ti), titanium nitride (TIN), or tungsten nitride (WN). The shield via plug 46 can block the gap 33 which is the path of copper diffusion by vertically penetrating the interface between the first stopper layer 32 and the lower insulating layer 20. The shield via plug 46, Has a pattern that is elongated longer than the first lower conductive layer 44a in plan view, so that diffusion of copper can be blocked horizontally. A third upper conductive layer 58 connected to the shield via plug 46 may be formed on the upper interlayer insulating layer 36. The third upper conductive layer 58 may be formed to overlap with the shield via plug 46 in the same direction. The third upper conductive layer 58 may be a means for suppressing lifting of the first stopper layer 32 together with the shield via plug 46. Meanwhile. The third upper conductive layer 58 may be formed by the same process as the first upper conductive layer 56a and the second upper conductive layer 56b. The first to third upper conductive layers 56a, 56b and 58 may include a metal conductive material, for example, aluminum (Al), or an aluminum alloy (Al-alloy). The shield via structure 64 may include only the shield via plug 46 without the third upper conductive layer 58. [ The shield via structure 64 is not connected to other conductive structures, and is electrically floated, so that it is not used as a wiring. Thus, the shield via plug 46 can be electrically floated.

Referring to FIGS. 2A and 3, in a plan view, the shield via structure 64 may surround the second conductive structure 62. The shield via plug 46 continuously surrounds at least a part of the side wall of the second upper via plug 48b of the second conductive structure 62 and the second lower conductive layer 44b so that copper is electrically connected to the second lower conductive layer 44b, respectively. The third upper conductive layer 58 may continuously surround the second conductive structure 62 in the same manner as the shield via plug 46. However, The second conductive structure 62 may overlap the shield via plug 46 and surround the second conductive structure 62 discontinuously. On the other hand, the third upper conductive layer 58 may not be formed on the upper interlayer insulating layer 36.

FIGS. 4 to 9 are cross-sectional views schematically showing semiconductor devices according to other embodiments of the present invention, taken along line I-I 'of FIG. Hereinafter, the same components as those described in FIGS. 1 to 3 will be omitted and the description will be focused on the characteristic parts.

1 and 4, the semiconductor device may include a shield via via plug 46 including a shield via conductive film 46a and a shield via insulating film 46b connected to the shield via via film 46a and disposed thereunder . The shield via conductive film 46a may include a conductive material. The conductive material may be, for example, tungsten (W). The shield via-hole insulating film 46b may be formed under the third via trench 40. The shield via insulating film 46b may extend through the upper interlayer insulating layer 36 and the first stopper layer 32 vertically and extend into the lower interlayer insulating layer 20. [ Thus, the copper of the first lower conductive layer 44a can be prevented from diffusing along the interface between the first stopper layer 32 and the lower interlayer insulating layer 20. The shield via insulating film 46b may be formed of, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or other insulating material. The other insulating material may be an oxide such as hafnium oxide (HfO 2) or alumina (Al 2 O 3), or a silicon containing a small amount of boron (B, boron), phosphorus (P), fluorine Oxide. A first via insulating film 47a may be disposed on the side wall of the first upper via plug 48a and a second via insulating film 47b may be disposed on the side wall of the second upper via plug 48b. The first via insulating film 47a formed along the sidewall of the first via trench 38a surrounds the sidewall of the first upper via plug 48a and the second via insulating film 47b formed along the sidewall of the second via trench 38b. (47b) may surround the side wall of the second upper via plug (48b). The width of the shield via plug 46 may be narrower than the width of the first and second lower via plugs 48a and 48b. The first via insulating film 47a and the second via insulating film 47b may be formed in the same process as the shield via insulating film 46b. For example, the third via trench 40 may be formed to be narrower than the width of the first and second via trenches 38a and 38b, and an insulating film may be formed in the trenches 38a, 38b, and 40. [ At this time, the third via trench 40 is filled with an insulating film, and an insulating film may be formed on the inner wall of the first and second via trenches 38a and 38b to a predetermined thickness. The insulating film in the trenches 38a, 38b and 40 is etched to form the first via insulating film 47b on the side wall of the first via trench 38a and the second via insulating film 47b on the side wall of the second via trench 38b. And a shield via insulating film 46b filling the lower portion of the third via trench 40 can be formed. Subsequently, each of the trenches 38a, 38b, and 40 may be filled with a conductive film to form the first and second upper via-plugs 48a and 48b and the shield via conductive film 46a.

1 and 5, the semiconductor device may include a shield via via plug 46 including a shield via conductive film 46a and a shield via insulating film 46b connected to the shield via via film 46a and disposed on the side wall thereof . The shield via insulating film 46b may surround the shield via conductive film 46a. The shield via conductive film 46a may include a metal conductive material. The metal conductive material may be, for example, tungsten (W). The shield via insulating film 46b may be formed on the sidewall of the third via trench 40. The shield via via insulating film 46b and the shield via conductive film 46a may be formed to penetrate the upper interlayer insulating layer 36 and the first stopper layer 32 vertically and extend into the lower interlayer insulating layer 20 . Thus, the copper of the first lower conductive layer 44a can be prevented from diffusing along the interface between the first stopper layer 32 and the lower interlayer insulating layer 20. On the other hand, the copper of the second lower conductive layer 44b can also be prevented from diffusing along the interface between the first stopper layer 32 and the lower interlayer insulating layer 20. The shield via insulating film 46b may be the same material as described with reference to FIG. A first via insulating film 47a is disposed on the side wall of the first upper via plug 48a and a second via insulating film 47b may be disposed on the side wall of the second upper via plug 48b. A first via insulating film 47a formed along the sidewalls of the first via trench 38a surrounds the sidewalls of the first upper via plug 48a and is connected to the second via trench 38a formed along the sidewalls of the second via trench 38a. The insulating film 47b may surround the side wall of the second upper via plug 48b. The first via insulating film 47a and the second via insulating film 47b may be formed in the same process as the shield via insulating film 46b. For example, the first and second via trenches 38a and 38b and the third via trench 40 may be formed therebetween, and an insulating film may be formed in the trenches 38a, 38b, and 40. [ At this time, an insulating film may be formed to a constant thickness on the inner walls of the trenches 38a, 38b, and 40. The insulating film in the trenches 38a, 38b, and 40 is etched to form the first via trench 38a The second via insulating film 47b may be formed in the first via insulating film 47a and the second via trench 38b and the shield via insulating film 46b may be formed in the third via trench 40. Subsequently, 38a, 38b, and 40 may be filled with a conductive film to form the first and second upper via plugs 48a and 48b and the shield via conductive film 46a.

1 and 6, the semiconductor device includes a lower interlayer insulating layer 20 formed on a substrate 10, a first stopper layer 32, an upper interlayer insulating layer 36, a first conductive structure 60 A second conductive structure 62 and a shield via structure 64 between the first conductive structure 60 and the second conductive structure 62. The lower interlayer insulating layer 20 may include a first interlayer insulating layer 22, a second stopper layer 26, and a second interlayer insulating layer 30. The first interlayer insulating layer 22 and the upper interlayer insulating layer 36 may include a plurality of stacked insulating films, respectively. The first conductive structure 60 and the second conductive structure 62 are formed by the first interlayer insulating layer 22, the second stopper layer 26, the second interlayer insulating layer 30, the first stopper layer 32, , And the upper interlayer insulating layer 36. [0050]

The interlayer insulating layers 22, 30, and 36 and the stopper layers 26 and 32 may include an insulating material as described with reference to FIG. 2A. The interlayer insulating layers 22, 30, and 36 may be thicker than the stopper layers 26 and 32. In addition, the first and second conductive structures 60 and 62, and the shield via structure 64 may also comprise the same conductive material as described in FIG. 2A.

The first conductive structure 60 includes a first lower via plug 40a, a first lower conductive layer 44a, a first upper via plug 48a, and a first upper conductive layer 56a stacked in that order . The second conductive structure 62 may include a second lower via plug 40b, a second lower conductive layer 44b, a second upper via plug 48b, and a second upper conductive layer 56b. The first lower via plug 40a of the first conductive structure 60 and the second lower via plug 40b of the second conductive structure 62 are electrically connected to the second stopper layer 26 and the first interlayer insulating layer 22, Can be vertically penetrated. The first lower conductive layer 44a of the first conductive structure 60 and the second lower conductive layer 44b of the second conductive structure 62 are disposed in the second interlayer insulating layer 30, (32) and the second stopper layer (26). That is, the upper surfaces of the first and second lower conductive layers 44a and 44b are in contact with the first stopper layer 32 and substantially coplanar with the upper surface of the second interlayer insulating layer 30. The lower surfaces of the first and second lower conductive layers 44a and 44b are in contact with the second stopper layer 26 and substantially coplanar with the lower surface of the second interlayer insulating layer 30. [ In order to prevent diffusion of copper from the first lower conductive layer 44a through the interfaces between the second interlayer insulating layer 30 and the first and second stopper layers 32 and 26, 64 may be provided. The shield via structure 64 is formed on the upper surface of the upper interlayer insulating layer 36 and the shield via via plug 46 extending through the upper interlayer insulating layer 36 and the first stopper layer 32 and into the lower interlayer insulating layer 20, And a third upper conductive layer 58 disposed on the second upper conductive layer 58. For example, the shield via plug 46 vertically penetrates the upper interlayer insulating layer 36, the first stopper layer 32, the second interlayer insulating layer 30, and the second stopper layer 26, It may extend into the interlayer insulating layer 22 to block the interface between the stopper layers 26 and 32 and the second interlayer insulating layer 30. [ The shield via plug 46 may be a pattern extending in a line shape as shown in FIG. The lower surface of the shield via plug 46 may be lower than the lower surfaces of the first and second conductive layers 44a and 44b. The shield via structure 64 may include only the shield via plug 46 without the third upper conductive layer 58. [ The shield via structure 64 is not connected to other conductive structures, and is electrically floated, so that it is not used as a wiring. Thus, the shield via plug 46 can be electrically floated. The first and second upper via-plugs 48a and 48b may be formed in the same process. The shield via plug 46 may be formed by a different process than the first and second upper via plugs 48a and 48b. For example, the shield via plug 46 may be formed earlier or later than the first and second upper via plugs 48a, 48b. The first to third upper conductive layers 55a, 56b and 58 may be formed by the same process.

1 and 7, the semiconductor device includes a shield via conductive film 46a vertically penetrating a part of the upper interlayer insulating layer 36 and a part of the upper interlayer insulating layer 36, And a shield via insulating film 46b that penetrates the first and second stopper layers 26 and 32 and the second interlayer insulating layer 30 therebetween and extends into the first interlayer insulating layer 22, A plug 46 may be included. The shield via insulating film 46b may shield copper diffusion through the interfaces between the stopper layers 26 and 32 and the second interlayer insulating layer 30. [ The shield via plug 46 including the shield via insulating film 46b may be electrically floating, but not limited thereto, and may also be used as an electrical wiring. The first via insulating film 47a may be disposed on the side wall of the first upper plug 48a and the second via insulating film 47b may be disposed on the side wall of the second upper plug 48b.

1 and 8, the semiconductor device may include a shield via via plug 46 including a shield via conductive film 46a and a shield via insulating film 46b connected to the shield via via film 46a and disposed on a side wall thereof . The shield via insulating film 46a may surround the shield via conductive film 46b. The shield via via insulating film 46b and the shield via conductive film 46a are formed by stacking the upper interlayer insulating layer 36, the first and second stopper layers 26 and 32 and the second interlayer insulating layer 30 therebetween vertically And may extend into the first interlayer insulating layer 22. [0052] The shield via via insulating film 46b and the shield via conductive film 46a can prevent diffusion of copper through the interfaces between the second interlayer insulating layer 30 and the stopper layers 26 and 32. [ The shield via plug 46 including the shield via insulating film 46b may be electrically floating, but not limited thereto, and may be used as an electrical wiring. The first via-insulating film 47a may be disposed on the side wall of the first upper via-plug 48a and the second via-insulating film 47b may be disposed on the side wall of the second upper via-plug 48b.

1 and 9, the semiconductor device includes a shield via via plug 46 including a shield via conductive film 46a and a shield via insulating film 46b connected to the shield via conductive film 46a and disposed on the side wall and the bottom surface thereof . The shield via-insulating film 46b may surround the side walls and the bottom surface of the shield via conductive film 46a. The shield via-hole insulating film 46b and the shield via conductive film 46a are formed on the upper interlayer insulating layer 36, the first and second stopper layers 26 and 32, and the second interlayer insulating layer 30 therebetween And extend into the first interlayer insulating layer 22 vertically. The shield via via insulating film 46b and the shield via conductive film 46a can prevent diffusion of copper through the interfaces between the second interlayer insulating layer 30 and the stopper layers 26 and 32. [ The shield via plug 46 including the shield via insulating film 46b may be electrically floating, but not limited thereto, and may be used as an electrical wiring. On the other hand, the first via insulating film 47a and the second via insulating film 47b shown in FIG. 8 may be absent from the side walls of the first and second upper via conductive plugs 48a and 48b.

On the other hand, each of the shield via structures 64 shown in Figs. 4 to 9 may continuously surround the second conductive structure 62 in a plan view as shown in Fig. For example, the shield via plug 46 continuously surrounds at least a part of the side wall of the second lower via plug 40b of the second conductive structure 62 and at least a part of the second lower conductive layer 44b It can be rice.

10 and 11 are cross-sectional views schematically showing semiconductor devices according to still another embodiment of the present invention, respectively. 10 and 11, each of the components of the semiconductor device is not different from the respective components of the semiconductor devices shown in Figs. 2A and 6 except for the number of the shield via plugs 46. Fig. A pair of shield via structures 64 may be disposed between the first conductive structure 60 and the second conductive structure 62. For example, a pair of shield via plugs 46 may be disposed between the first and second conductive structures 60 and 62 to define at least one of the first and second conductive layers 44a and 44b The diffusion of copper through the interfaces between the first stopper layer 32 and the lower interlayer insulating layer 20 or between the stopper layers 26 and 32 and the second interlayer insulating layer 30 can be blocked . In a plan view, the pair of shield via plugs 46 can be arranged in a line shape. For example, at least one pair of shield via plugs 46 may be formed on at least a portion of the second conductive structure 62 (for example, at least the side wall of the second upper via plug 48b and the second lower conductive layer 44b) A side wall of the second lower via plug 48b, a side wall of the second lower conductive layer 44b, and a side wall of at least a part of the second lower via plug 40b). On the other hand, one of the pair of shield via plugs 46 is connected to a part of the first conductive structure 60 (for example, at least a part of the side wall of the first upper via plug 48a and the first lower conductive layer 44a) The sidewalls of the first lower via plugs 48a, the sidewalls of the first lower conductive layer 44a and the sidewalls of the first lower via plugs 40a) (For example, a side wall of the second upper via plug 48b and a side wall of at least a part of the second lower conductive layer 44b, or a side wall of the second upper via plug 48b, The side wall of the conductive layer 44b and the side wall of at least a part of the second lower via plug 40b). On the other hand, each of the pair of shield via plugs 46 may include the above-described via insulating film 46b. On the other hand, three or more shield via plugs 46 may be arranged in a line form when viewed in plan between the first conductive structure 60 and the second conductive structure 62.

12 is a plan view schematically showing a semiconductor device according to still another embodiment of the present invention. FIGS. 13 to 14 are cross-sectional views schematically showing still another embodiment of the present invention cut along the line II-II 'of FIG.

12 and 13, a semiconductor device may include a scribe lane region SL and a chip region CA formed on a substrate 100. [ The chip area CA may include a main chip area MC and a chip boundary area CE around the main chip area MC. A conductive structure 162 is disposed in the main chip region MC and a chip guard ring 160 and a shield via structure 164 surrounding the main chip region MC may be disposed in the chip boundary region CE . The chip guard ring 160 is disposed adjacent to the scribelane area SL and the shield via structure 164 can be disposed between the chip guard ring 160 and the main chip area MC. The chip guard ring 160 and the shield via structure 164 may be a line-shaped pattern surrounding the main chip area MC continuously. Further, the shield via plug 146 of the shield via structure 164 may be a loop-shaped pattern continuously surrounding the main chip area MC. The substrate 100 may be a substrate comprising a semiconductor material. The semiconductor material may comprise, for example, a material containing silicon. The substrate 100 of the main chip area CA may include a direct circuit (not shown). The integrated circuit may include a plurality of transistors. A lower interlayer insulating layer 120, a first stopper layer 132, and an upper interlayer insulating layer (not shown) are formed in the main chip region MC, the chip boundary region CE, and the scribe lane region SL formed on the substrate 100 136 may be formed. The lower and upper interlayer insulating layers 120 and 136 may include a plurality of stacked insulating films, respectively. The conductive structure 162, the shield via structure 164 and the chip guard ring 160 may be disposed in the lower interlayer insulating layer 120, the first stopper layer 132, and the upper interlayer insulating layer 136.

The interlayer insulating layers 120 and 136 may be formed of a silicon oxide containing a small amount of impurities or a silicon oxide not containing an impurity. For example, the interlayer insulating layers 120 and 136 may be formed of boron silicate glass (BSG), phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), silicon oxyfluoride (SiOF), silicon carbonic hydrooxide , Tetra ethyl ortho silicate (TEOS), undoped silicate glass (USG), or the like. The interlayer insulating layers 120 and 136 may be formed by various methods including a chemical vapor deposition method using thermal or plasma or a spin coating method.

The first stopper layer 132 may be formed of a material having an etch selectivity with respect to the upper interlayer insulating layer 136. For example, the first stopper layer 132 may serve as an etching stopper for preventing the conductive layers 144a and 144b from being etched when the upper interlayer insulating layer 136 is etched. The first stopper layer 132 may be formed of an insulating material harder than the silicon oxide film. For example, the first stopper layer 132 may comprise silicon nitride, silicon carbide nitride, or silicon oxynitride. The interlayer insulating layers 120 and 136 may be thicker than the first stopper layer 132.

The chip guard ring 160 formed in the chip boundary region CE includes a first lower via plug 140a, a first lower conductive layer 144a, a first upper via plug 148a, Layer 156a. The first lower via plug 140a and the first lower conductive layer 144a of the chip guard ring 160 may be disposed in the lower interlayer insulating layer 120. [ The chip guard ring 160 may be connected to the substrate 100. For example, the first lower via-plug 140a of the chip guard ring 160 may be connected to the substrate 100. [ Meanwhile, the first lower via plug 140a may be connected to the substrate 100 through at least one conductive layer and a via plug disposed thereunder. The upper surface of the first lower conductive layer 144a may be substantially coplanar with the upper surface of the lower interlayer insulating layer 120. The first upper via plug 148a may be connected to the first lower conductive layer 144a through the upper interlayer insulating layer 136 and the first stopper layer 132. [ The first upper via plug 148a may include a first via trench 138a formed through the upper interlayer insulating layer 136 and the first stopper layer 132 formed on the first lower conductive layer 144a, As shown in Fig. A first upper conductive layer 156a connected to the first upper via plug 148a may be formed on the upper interlayer insulating layer 136. [ The first lower via plug 140a, the first lower conductive layer 144a, the first upper via plug 148a, and the first upper conductive layer 156a included in the chip guard ring 160 are successively connected to the main It may surround the chip area MC and be a line-shaped pattern in plan view.

The conductive structure 60 of the main chip area MC includes a second via plug 140b, a second lower conductive layer 144b, a second upper via plug 148b, and a second upper conductive layer 156b can do. The second lower via plug 140b and the second lower conductive layer 144b of the conductive structure 160 may be disposed in the lower interlayer insulating layer 120. [ The conductive structure 160 may be connected to the substrate 100. For example, the conductive structure 160 may be connected to the integrated circuit of the substrate 100. The second lower via plug 140b of the conductive structure 162 may be connected to the substrate 100. [ Meanwhile, the second lower via plug 140b may be connected to the substrate 100 through at least one conductive layer and a via plug disposed thereunder. The upper surface of the second lower conductive layer 144b may be substantially coplanar with the upper surface of the lower interlayer insulating layer 120. The second upper via plug 148b may be connected to the second lower conductive layer 144b through the upper interlayer insulating layer 136 and the first stopper layer 132. [ For example, the second upper via plug 148b includes a second via trench 138b formed through the first stopper layer 132 formed on the upper interlayer insulating layer 136 and the second lower conductive layer 144b, As shown in Fig. A second upper conductive layer 156b may be formed on the upper interlayer insulating layer 136 and connected to the second upper via plug 148b.

The chip guard ring 160 and the via plugs 140a, 140b, 148a, and 148b constituting the conductive structure 162 may include a conductive film. For example, the conductive film may include tungsten (W). The via plugs 140a, 140b, 148a, and 148b may further include a barrier film. For example, the barrier film may comprise titanium (Ti), titanium nitride (TIN), or tungsten nitride (WN). The first lower conductive layer 144a of the chip guard ring 160 and the second lower conductive layer 144b of the conductive structure may be metal conductive layers. For example, the first and second lower conductive layers 144a and 144b may include copper (Cu). On the other hand, the first and second lower conductive layers 144a and 144b may further include a barrier film including titanium (Ti), titanium nitride (TiN), or tungsten nitride (WN) Since the lower conductive layers 144a and 144b include copper, it is necessary to prevent copper from diffusing at the interface between the lower interlayer insulating layer 120 and the first stopper layer 132. Furthermore, the difference in thermal stress between the interlayer insulating layers 120 and 132 including oxide and the first stopper layer 132 including nitride may be large. Therefore, when the thermal stress is applied at a high temperature after the formation of the chip guard ring 160 and the conductive structure 164, the chip boundary region CE is weakened due to the thermal stress difference, A gap may be generated at the interface between the first stopper layer 120 and the first stopper layer 132. A defect that the copper of the first lower conductive layer 144a of the chip guard ring 160 diffuses into the main chip area MC and shorts to the second lower conductive layer 144b of the conductive structure 162 through this gap Lt; / RTI > This prevents the gap between the lower interlayer insulating layer 120 and the first stopper layer 132 from being generated and prevents the diffusion of copper from the chip guard ring 160. In order to prevent diffusion of copper from the chip guard ring 160, And may be disposed between the chip guard ring 160 and the main chip area MC at the peripheral edge CE. The shield via structure 164 may include a shield via plug 146 and a third upper conductive layer 158. The shield via plug 146 is formed between the upper interlayer insulating layer 136 between the first upper via plug 148a of the chip guard ring 160 and the second upper via plug 148b of the conductive structure 162, And may extend through the layer 132 to extend into the lower interlayer insulating layer 120. The lower surface of the shield via plug 146 may be lower than the upper surface of the lower interlayer insulating layer 120. The lower surface of the shield via plug 146 may be lower than the upper surface of the first lower conductive layer 144a of the chip guard ring 160. [ The upper surface of the shield via plug 146 may be coplanar with the upper surface of the first upper via plug 148a of the chip guard ring 160 and the upper surface of the second upper via plug 148b of the conductive structure 162 have. The height of the shield via plug 146 may be greater than the height of the first upper via plug 148a of the chip guard ring 160 and the height of the second upper via plug 148b of the conductive structure 162. [ The third via trench 140 may be formed in the third via trench 140. The third via trench 140 may be formed in the third via trench 140 in the chip boundary region CE, May extend through the upper interlayer insulating layer 136 and the first stopper layer 132 between the trenches 138b and into the lower interlayer insulating layer 120 and may be formed in the chip boundary region CE. The third via trench 140 may be formed in the same process as the first via trench 138a and the second via trench 138b. When the upper interlayer insulating layer 136 and the stopper layer 132 are etched to form the first via trench 138a, the second via trench 138b and the third via trench 140, an over- have. At this time, since the region where the third via trench 140 is to be formed has no conductive layer, the lower interlayer insulating layer 120 can be further etched. The lower surface of the third via trench 140 may be lower than the upper surface of the first lower conductive layer 144a. In addition, the third via trench 140 may be formed to continuously surround the main chip area MC. The shield via plug 146 may include a conductive film filling the third via trench 140. The conductive film of the shield via plug 146 may be the same conductive film as the first and second upper via plugs 148a and 148b. That is, the shield via plug 146 may include tungsten (W). Further, the shield via plug 146 may further include a barrier film surrounding the conductive film. For example, the barrier film may comprise titanium (Ti), titanium nitride (TIN), or tungsten nitride (WN). The shield via plug 146 vertically cuts the interface between the first stopper layer 132 and the lower interlayer insulating layer 120 by passing through the interface between the stopper layer 132 and the lower interlayer insulating layer 120, The shield via plug 146 completely surrounds the main chip area MC to prevent diffusion of copper from the first lower conductive layer 144a of the chip guard ring 160 to the main chip area MC. have. A third upper conductive layer 58 connected to the shield via plug 146 may be formed on the upper interlayer insulating layer 136. [ The third upper conductive layer 158 may continuously surround the main chip area MC in the same direction as the shield via plug 146. However, the third upper conductive layer 158 may not overlap the shield via plug 146, To surround the main chip area MC. The third upper conductive layer 158 may be a means for suppressing the gap between the first stopper layer 132 and the lower interlayer insulator 120 together with the shield via plug 146. Meanwhile. The third upper conductive layer 158 may be formed in the same process as the first upper conductive layer 156a and the second upper conductive layer 156b. The third upper conductive layer 158 may comprise a metal conductive material such as aluminum (Al) or an aluminum alloy (Al-alloy), such as first and second top conductive layers 156a and 156b . The shield via structure 164 may include only the shield via plug 146 without the third upper conductive layer 158. [ The shield via structure 164 is electrically floated and is not used as a wiring. Thus, the shield via plug 146 can be electrically floated.

12 and 14, a semiconductor device includes a lower interlayer insulating layer 120 formed on a substrate 100 including a scribelane region SL, a chip boundary region CE, and a main chip region MC. A first stopper layer 132, an upper interlayer insulating layer 136, a chip guard ring 160, a conductive structure 162 and a shield via structure between the chip guard ring 160 and the conductive structure 162 164). The chip guard ring 160 and the conductive structure 162 may be connected to the substrate 100. For example, the chip guard ring 160 and the conductive structure 162 may be connected to the integrated circuit of the substrate 100. The lower interlayer insulating layer 120 may include a first interlayer insulating layer 122, a second stopper layer 126, and a second interlayer insulating layer 130. The first interlayer insulating layer 122 and the upper interlayer insulating layer 136 may include a plurality of stacked insulating films. The chip guard ring 160 and the conductive structure 162 are electrically connected to the first interlayer insulating layer 122, the second stopper layer 126, the second interlayer insulating layer 130, the first stopper layer 132, May be disposed within the insulating layer 136. The first and second interlayer insulating layers 122 and 130 may include the same insulating material as the upper interlayer insulating layer 136. In addition, the second stopper layer 126 may include the same insulating material as the first stopper layer 132. The interlayer insulating layers 122, 130, and 136 may be formed thicker than the stopper layers 126 and 132.

The chip guard ring 160 formed in the chip boundary region CE includes a first lower via plug 140a, a first lower conductive layer 144a, a first upper via plug 148a, Layer 156a. The conductive structure 162 formed in the main chip area MC is electrically connected to the second conductive via plug 140b, the second lower conductive plug 144b, the second upper via plug 148b, . ≪ / RTI > The first upper via plug 148a of the chip guard ring 160 and the second upper via plug 148b of the conductive structure 162 are formed by vertically aligning the second stopper layer 126 and the first interlayer insulating layer 122 Can penetrate. The first lower conductive layer 144a of the chip guard ring 160 and the second lower conductive layer 144b of the conductive structure 162 are disposed in the second interlayer insulating layer 130 and the first stopper layer 132, And the second stopper layer 126, as shown in FIG. That is, upper and lower surfaces of the first lower conductive layer 144a and the second lower conductive layer 144b are in contact with the first stopper layer 132 and the second stopper layer 126, respectively, and the second interlayer insulating layer 130 And the upper surface and the lower surface of the substrate. The first and second upper via plugs 148a and 148b may be connected to the first and second lower conductive layers 144a and 144b through the upper interlayer insulating layer 136 and the first stopper layer 132, have. The first and second upper conductive layers 156a and 156b may be formed on the upper interlayer insulating layer 136. [

The shield via structure 164 includes a shield via plug 146 extending through the upper interlayer insulating layer 136 and extending into the lower interlayer insulating layer 120 and a third upper conductive layer 162 disposed on the upper interlayer insulating layer 136. [ Lt; RTI ID = 0.0 > 158 < / RTI > For example, the shield via plug 146 vertically penetrates the upper interlayer insulating layer 136, the first stopper layer 132, the second interlayer insulating layer 130, and the second stopper layer 126, It may extend into the interlayer insulating layer 22 and block the interfaces between the stopper layers 126 and 132 and the second interlayer insulating layer 130. The shield via plug 146 surrounds the main chip area MC and may be a loop-shaped pattern in a plan view. The lower surface of the shield via plug 146 may be lower than the lower surface of the first and second lower conductive layers 144b. The shield via structure 164 may include only the shield via plug 146 without the third upper conductive layer 156. [ The shield via structure 164 is not connected to the substrate 100 but is spaced apart from the substrate 100, and is not electrically connected to the floating structure. Thus, the shield via plug 146 can be electrically floated.

15 and 16 are cross-sectional views schematically showing semiconductor devices according to still another embodiment of the present invention, respectively. 15 and 16, each of the components of the semiconductor device has no difference other than the number of the shield via plugs 146 in comparison with each of the components of the semiconductor devices shown and described in Figs. 13 and 14. A pair of shield via plugs 146 formed in the chip boundary region CE are disposed between the chip guard ring 160 and the main chip region MC to prevent the chip guard ring 160 from being damaged Diffusion of copper through the interfaces between the first stopper layer 132 and the lower interlayer insulating layer 120 or between the second interlayer insulating layer 130 and the stopper layers 126 and 132 with the conductive structure 162, Lt; / RTI > In a plan view, the pair of shield via structures 164 may surround the main chip area MC. That is, at least one pair of shield via plugs 146 may surround the main chip area MC. For example, a pair of shield via plugs 146 may continuously surround the side walls of the second upper via plug 148b of the conductive structure 162 and the sidewalls of at least a portion of the second lower conductive layer 144b Or the sidewalls of the second upper via plugs 148b of the conductive structure 162, the sidewalls of the second lower conductive layer 144b and the sidewalls of at least a portion of the second lower via plugs 140b . On the other hand, three or more shield via structures 164 are disposed in the chip boundary region CE between the chip guard ring 160 and the main chip region MC to define the main chip region MC as a continuous . The shield via plug 146 can be electrically floated without being connected to the substrate 100. [

17 to 21 are cross-sectional views schematically showing a semiconductor device according to still another embodiment of the present invention.

12 and 17 to 21, the shield via plug 146 of the shield via structure 164 is connected to the shield via conductive film 146a and shielded via plugs 146a, And an insulating film 146b. 17, the shield via insulating film 146b is disposed below the shield via conductive film 146a and penetrates a part of the upper interlayer insulating layer 136 and the first stopper layer 132, Layer 120 as shown in FIG. Therefore, the shield via-hole insulating film 146b penetrates the interface between the lower interlayer insulating layer 120 and the first stopper layer 132, and thus can prevent copper diffusion from the chip guard ring 160. [ 19, the shield via insulating film 146b penetrates through the upper interlayer insulating layer 136, the first and second stopper layers 132 and 126, and the second interlayer insulating layer 130 And extend into the first interlayer insulating layer 122. Therefore, the copper diffusion from the chip guard ring 160 can be blocked because it penetrates the interfaces between the stopper layers 132 and 126 and the second interlayer insulating layer 130. The first via insulating film 147a may be formed on the sidewall of the first upper via plug 148a and the second via insulating film 147b may be formed on the sidewall of the second upper via plug 148b. 18, 20, and 21, a shield via-hole insulating film 146b is disposed on the side wall of the shield via conductive film 146a to penetrate the upper interlayer insulating layer 136 and the first stopper layer 132 Or extend into the lower interlayer insulating layer 120 or pass through the upper interlayer insulating layer 136, the first and second stopper layers 132 and 126, and the second interlayer insulating layer 130, May extend into the insulating layer 122. The first interlayer insulating layer 20 or the first and second stopper layers 132 and 126 and the second interlayer insulating layer 130 to penetrate the chip guard ring 132 through the interface between the first stopper layer 132 and the lower interlayer insulating layer 20 or between the first and second stopper layers 132 and 126 and the second interlayer insulating layer 130 160 to prevent copper diffusion. The shield via insulating film 146b may surround the side wall of the shield via conductive film 146a. On the other hand, referring to FIG. 21, the shield via insulating film 146b may be disposed on the side wall and the bottom surface of the shield via conductive film 146a. The shield via insulating film 146b may surround the side wall and the bottom surface of the shield via conductive film 146a. In addition, the first and second via insulating films 147a and 147b may not be formed on the sidewalls of the first and second upper via plugs 148a and 148b. As described above, The shielded via plug 146 may be applied between the chip guard ring 160 and the main chip area MC to continuously surround the main chip area MC. The plug 146 may not be connected to the substrate 100 but may be disposed apart from the substrate 100. The shield via plug 146 may be electrically floated.

22 is a block diagram illustrating an example of an electronic system including a semiconductor device in accordance with various embodiments of the present invention.

22, the electronic system 2000 may include a controller 2200, a storage device 2300, and an input / output device 2400. [ The controller 2200, the storage device 2300, and the input / output device 2400 may be coupled through a bus 2100, bus. The bus 2100 may be a path through which data is moved. For example, the controller 2200 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions. The input / output device 2400 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 2300 is a device for storing data. The storage device 2300 may store data and / or instructions executed by the controller 2200, and the like. The storage device 2300 may include a volatile storage element and / or a non-volatile storage element. Alternatively, the storage device 2300 may be formed of a flash memory. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 2000 can stably store a large amount of data in the storage device 2300. The controller 2200 and the memory device 2300 may include a semiconductor device according to various embodiments of the present invention. The electronic system 2000 may further include an interface 2500 for transferring data to or receiving data from the communication network. The interface 2500 may be in wired or wireless form. For example, the interface 2500 may include an antenna or a wired or wireless transceiver.

The foregoing detailed description is illustrative of the present invention. It is also to be understood that the foregoing is illustrative and explanatory of preferred embodiments of the invention only, and that the invention may be used in various other combinations, modifications and environments. That is, it is possible to make changes or modifications within the scope of the concept of the invention disclosed in this specification, the disclosure and the equivalents of the disclosure and / or the scope of the art or knowledge of the present invention. The foregoing embodiments are intended to illustrate the best mode contemplated for carrying out the invention and are not intended to limit the scope of the present invention to other modes of operation known in the art for utilizing other inventions such as the present invention, Various changes are possible. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. It is also to be understood that the appended claims are intended to cover such other embodiments.

Claims (10)

A lower interlayer insulating layer, a first stopper layer, and an upper interlayer insulating layer which are sequentially stacked on a substrate;
A first lower conductive layer and a second lower conductive layer disposed in the lower interlayer insulating layer and separated laterally;
A first upper via plug passing through the upper interlayer insulating layer and the first stopper layer and connected to the first lower conductive layer, and a second upper via plug connected to the second lower conductive layer; And
And at least one shield via plug extending between the first upper via plug and the second upper via plug through the first stopper layer and extending from the upper interlayer insulating layer to the lower interlayer insulating layer,
Wherein the shield via plug is a line-shaped pattern in plan view and includes a conductive film, and is electrically floated. The method according to claim 1,
Wherein the shield via plug surrounds the sidewalls of the second upper via plug and the sidewalls of at least a portion of the second lower conductive layer. The method according to claim 1,
Wherein the first lower conductive layer and the second lower conductive layer comprise copper. The method according to claim 1,
Wherein the shield via plug includes a conductive film, a via insulating film disposed at least on the sidewall thereof, or a conductive film and a via insulating film disposed under the conductive film. The method according to claim 1,
Wherein the lower interlayer insulating layer includes a first interlayer insulating layer, a second stopper layer, and a second interlayer insulating layer between the second stopper layer and the first stopper layer, which are sequentially stacked on the substrate, Wherein the plug extends through the first stopper layer, the second interlayer insulating layer, and the second stopper layer, and extends from the upper interlayer insulating layer into the first interlayer insulating layer. A substrate including a main chip region, a scribe lane region, and a chip boundary region between the main chip region and the scribe lane region;
A plurality of interlayer insulating layers including at least one stopper layer provided on the substrate;
A conductive structure disposed in the plurality of interlayer insulating layers provided in the main chip area;
A chip guard ring disposed in the plurality of interlayer insulating layers provided in the chip boundary region and continuously surrounding the main chip region and connected to the substrate; And
A shielding layer continuously surrounding the main chip area and disposed between the chip guard ring and the main chip area and passing through a part of the plurality of interlayer insulating layers including the at least one stopper layer, Wherein the shield via plug comprises a via plug, the shield via plug comprising a conductive material and electrically floated. The method according to claim 6,
Wherein the chip guard ring and the conductive structure comprise a conductive layer comprising copper. The method according to claim 6,
Wherein the interlayer insulating layer includes a lower interlayer insulating layer, a first stopper layer, and an upper interlayer insulating layer sequentially stacked on the substrate, wherein the shield via plug passes through the first stopper layer, A lower interlayer insulating layer,
Wherein the conductive structure and the chip guard ring each include a lower via plug and a lower conductive layer which are sequentially disposed in the lower interlayer insulating layer and which are stacked in order and which are connected to the lower conductive layer through the upper interlayer insulating layer and the first stopper layer And an upper conductive layer disposed on the upper interlayer insulating layer and connected to the upper via plug. The method according to claim 6,
Wherein the plurality of interlayer insulating layers includes a first interlayer insulating layer, a first stopper layer, a second interlayer insulating layer, a second stopper layer, and a third interlayer insulating layer sequentially stacked on the substrate,
Wherein the shield via plug extends through the third interlayer insulating layer and the second stopper layer, the second interlayer insulating layer, and the first stopper layer and into the lower interlayer insulating layer,
Wherein the conductive structure and the chip guard ring each comprise a lower via plug disposed in the first interlayer insulating layer and the first stopper layer, a lower conductive layer connected to the lower via plug and disposed in the second interlayer insulating layer, An upper via plug connected to the lower conductive layer and penetrating the second stopper layer and the third insulating layer, and an upper conductive layer connected to the upper via plug and disposed on the third interlayer insulating layer, . The method according to claim 6,
Wherein the shield via plug includes a conductive film, a via insulating film disposed at least on the sidewall thereof, or a conductive film and a via insulating film disposed under the conductive film.

Images