KR20150061076A - A array substrate and method of fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate which includes an oxide semiconductor layer, and a manufacturing method thereof. The feature of the present invention is to prevent H_2 from penetrating through the oxide semiconductor layer by forming a buffer layer on the upper side of a first protection layer or a second protection layer which covers a thin film transistor to totally surround the oxide semiconductor layer. Therefore, the reduction of a lifetime due to the degradation of the oxide semiconductor layer is prevented. The feature degradation of the thin film transistor is prevented by preventing the oxide semiconductor layer from being changed into a conductor. Also, the degradation of the display quality due to the non-uniformity of brightness is prevented by preventing the current and voltage properties of the thin film transistor from being shifted in a negative direction. Finally, the reliability of the thin film transistor is improved.

Description

[0001] The present invention relates to an array substrate and method for fabricating the same,

The present invention relates to an array substrate including an oxide semiconductor layer and a method of manufacturing the same.

In recent years, as the society has become a full-fledged information age, a display field for processing and displaying a large amount of information has rapidly developed, and various flat panel display devices have been developed in response to this.

Specific examples of such flat panel display devices include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display (FED) (ELD), organic light emitting diodes (OLED), and the like. These flat panel display devices are excellent in performance of thinning, light weight, and low power consumption, and can be applied to a conventional cathode ray tube ).

Such a flat panel display device includes an array substrate on which a thin film transistor, which is a switching device for turning on / off a pixel, is located on a pixel-by-pixel basis.

A thin film transistor formed on an array substrate is composed of a gate electrode, a gate insulating film, a source and a drain electrode, and a semiconductor layer. Recently, an oxide semiconductor material having a field effect mobility several times to several hundred times larger than a thin film transistor using amorphous silicon Studies on a thin film transistor including an oxide semiconductor layer used have been actively conducted.

Since the oxide semiconductor layer does not need to form the ohmic contact layer, it is not necessary to be exposed to the dry etching for forming the ohmic contact layer, so that the characteristics of the thin film transistor can be prevented from deteriorating.

On the other hand, in the oxide semiconductor layer, a hydrogen (H ₂ ) atom acts as a carrier in a semiconductor thin film by reaction with hydrogen (H ₂ ) gas to deteriorate the oxide semiconductor layer, There is a problem that the oxide semiconductor layer is changed into a conductor.

Since the oxide semiconductor layer is changed to a conductor to reduce the role of the semiconductor layer, the characteristics of the thin film transistor including such an oxide semiconductor layer are lowered and the current-voltage characteristic of the thin film transistor is reduced in the negative direction There is a problem of shifting.

When the thin film transistor having the oxide semiconductor layer is shifted in the negative direction, particularly, when the thin film transistor is used as the driving element, the emission luminance characteristic is changed according to the position in the display device, and the display quality due to the luminance unevenness is also reduced.

SUMMARY OF THE INVENTION It is a first object of the present invention to provide an array substrate capable of preventing deterioration of characteristics of a thin film transistor including an oxide semiconductor layer.

A second object of the present invention is to prevent the occurrence of luminance unevenness.

A third object of the present invention is to realize a narrow bezel of an OLED including a thin film transistor including an oxide semiconductor layer.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a substrate having a plurality of pixel regions defined therein; A gate electrode, a gate insulating film located above the gate electrode, an oxide semiconductor layer located above the gate insulating film, and source and drain regions spaced apart from each other above the oxide semiconductor layer, A thin film transistor including an electrode; A first passivation layer exposing the drain electrode over the thin film transistor; A first buffer layer located above or below the oxide semiconductor layer on the substrate; And a first electrode in contact with the base electrode.

At this time, the first buffer layer is located on the first protective layer, the second protective layer is located on the first protective layer, and the first buffer layer is located on the second protective layer.

A second electrode is formed on the second protection layer, a third protection layer is formed on the second electrode, and the first, second, and third protection layers include a drain contact hole exposing the drain electrode. The first electrode is located above the third passivation layer, and the first buffer layer is located above the gate insulating layer.

The second buffer layer is located on the oxide semiconductor layer, and the first buffer layer is formed of Al 2 O 3, AlON, TiO 2, ZrO 2, HfO 2, Ta 2 O 5, Nb 2 O 5, Y 2 O 3, MbO, CeO 2, La 2 O 3, Ln 2 O 3, PrAlO 3, Er 2 O 3, HfAlO , HfSiO, ZrSiO, ZrAlO, HfON, HfSiON, SrTiO3, BaTiO3, SiN and SiBN.

When the first buffer layer is made of Al2O3, the first buffer layer has a thickness of 500 to 1000 mu m. When the first buffer layer is made of AlON, the first buffer layer has a thickness of 500 to 2000 mu m, The etch stopper may be formed in an island shape at the center of the oxide semiconductor layer or may be formed on the entire surface of the substrate and includes a semiconducting layer contact hole exposing both end surfaces of the oxide semiconductor layer .

A bank formed on the boundary of the pixel regions and overlapping the edge of the first electrode above the first electrode; An organic light emitting layer formed above the first electrode; An anode electrode formed on the organic light emitting layer; And a protective film covering the anode electrode.

At this time, the in-cap substrate is bonded to the top of the protective film through the adhesive layer.

According to the present invention, there is provided a semiconductor device, comprising a gate electrode, an oxide semiconductor layer, and source and drain electrodes spaced apart from each other in each pixel region on a substrate on which a plurality of pixel regions are defined, Forming a thin film transistor having a first buffer layer; And forming a first electrode in contact with a drain electrode of the thin film transistor.

At this time, a gate insulating layer is formed on the gate electrode, the first buffer layer is formed on the gate insulating layer, and the second buffer layer is formed on the oxide semiconductor layer.

A first passivation layer is formed on the source and drain electrodes to expose the drain electrode. The first buffer layer is formed on the first passivation layer, and the second passivation layer is formed on the first passivation layer. And the first buffer layer is formed on the second protective layer.

In this case, the first buffer layer is formed of one selected from Al 2 O 3 and AlON, and is formed through a sputtering process or an ALD (Atomic Layer Deposition) process. The first buffer layer made of Al 2 O 3 injects O 2 gas into the chamber and is subjected to a sputtering process .

The first buffer layer made of AlON is formed by a sputtering process by injecting O2 gas and N2 gas into the chamber, and the first buffer layer is formed by ALD process by injecting H2O and O3 gas or injecting O2 plasma .

As described above, the buffer layer is formed on the first passivation layer or the second passivation layer covering the TFT according to the present invention, and the buffer layer is formed so as to completely surround the oxide semiconductor layer, so that hydrogen (H ₂ ) It is possible to prevent penetration into the layer.

Accordingly, the lifetime of the oxide semiconductor layer can be shortened, or the oxide semiconductor layer can be prevented from being changed into a conductive material, and the characteristics of the thin film transistor can be prevented from deteriorating.

Accordingly, the phenomenon that the current-voltage characteristic of the thin film transistor is shifted in the negative direction is suppressed, thereby preventing display quality deterioration due to the luminance non-uniformity phenomenon, and finally improving the reliability of the thin film transistor.

FIGS. 1 to 4 are cross-sectional views of a portion of a pixel substrate including a thin film transistor, which is cut in an array substrate according to an embodiment of the present invention. FIG.
5A to 5G are cross-sectional views illustrating steps of manufacturing a portion of one pixel region of an array substrate including a thin film transistor according to an embodiment of the present invention.
6 is a cross-sectional view schematically illustrating an OLED including an array substrate according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

FIGS. 1 to 4 are cross-sectional views of a pixel substrate in an array substrate according to an embodiment of the present invention, including a thin film transistor. FIG.

1, the array substrate 100 includes pixel regions P which intersect a plurality of gate wirings (not shown) and gate wirings (not shown) spaced apart from each other by a predetermined distance on a substrate 101, And a data line 117 that defines a data line.

At this time, the thin film transistor T is formed in the switching region TrA near the intersection of the gate wiring (not shown) and the data wiring 117 of each pixel region P, and a display region A pixel electrode 125 is formed.

A gate electrode 103 is formed in the switching region TrA of the array substrate 100 and a gate electrode 103 is formed on the entire surface of the substrate 101 over the gate electrode 103, An insulating film 105 is formed.

An oxide semiconductor layer 107 is formed on the gate insulating film 105. An etch stopper 115 is formed on the oxide semiconductor layer 107. A gate electrode 103 Source and drain electrodes 111 and 113 are formed so as to be spaced apart from each other in correspondence with the source and drain electrodes 111 and 113, respectively.

The gate electrode 103, the gate insulating film 105, the oxide semiconductor layer 107 and the source and drain electrodes 111 and 113 constitute the thin film transistor T.

Here, the thin film transistor T including the oxide semiconductor layer 107 has a field effect mobility of several to several hundred times larger than that of a thin film transistor manufactured using amorphous silicon.

(Al), nickel (Ni), copper (Cu), tantalum (Ta), and tantalum (Ta) The use of an oxide semiconductor made of a material doped with molybdenum (Mo), hydrogen fluoride (Hf), or titanium (Ti) can improve the electric field mobility by 20 times or more as compared with the field effect mobility of amorphous silicon.

Further, the oxide semiconductor layer 107 can obtain high mobility even when formed at a low temperature, and the reliability is also excellent.

A first protective layer 119a made of silicon oxide (SiO ₂ ) is formed on the front surface of the substrate 101 including the thin film transistor T.

Here, the buffer layer 200 is formed on the first passivation layer 119a.

The buffer layer 200 is formed on the first passivation layer 119a so that the buffer layer 200 completely covers the oxide semiconductor layer 107. [ The buffer 200 begins to serve to protect the oxide semiconductor layer 107, and thus the array substrate 100 of the present invention is an oxide semiconductor layer 107 to the water and hydrogen (H ₂₎ from the outside penetrates Can be prevented.

Thus, the life of the oxide semiconductor layer 107 can be shortened or the oxide semiconductor layer 107 can be prevented from being changed into a conductive material, and the characteristics of the thin film transistor T can be prevented from deteriorating.

In addition, since the phenomenon that the current-voltage characteristic of the thin film transistor T is shifted in the negative direction is suppressed, the display quality deterioration due to the luminance non-uniformity phenomenon is prevented, and the effect of improving the reliability of the thin film transistor T . Let's take a closer look at this later.

A second passivation layer 119b having a flat surface is formed on the buffer layer 200. [

A common electrode 121 made of a transparent conductive material is formed on the entire surface of the second protective layer 119b. At this time, the common electrode 121 is partially removed corresponding to each switching region TrA The parasitic capacitance caused by overlapping with the source and drain electrodes 111 and 113 can be reduced.

The third protective layer 119c is provided above the common electrode 121. The first and second protective layers 119a and 119b located below the third protective layer 119c are connected to the switching elements And drain contact holes 114a, 114b, and 114c exposing the respective drain electrodes 113 in the region TrA.

A pixel electrode 125 is formed on the third passivation layer 119c and is in contact with the drain electrode 113 through the drain contact holes 114a, 114b and 114c.

At this time, each pixel electrode 125 is provided with a plurality of openings op having a bar shape for each pixel region P. The array substrate 100 having such a configuration forms a fringe field switching mode.

Here, the buffer layer 200 is a second protective layer (119b) as shown in Figure 2 to form the upper portion, the oxide semiconductor layer 107 with water from the outside and hydrogen (H ₂₎ is also prevented from penetrating have.

The buffer layer 200 is further formed on the first protective layer 119a or the second protective layer 119b so that the oxide semiconductor layer 107 can be removed from the outside it is possible to prevent the water and hydrogen (H ₂₎ penetration.

As a result, the characteristics of the thin film transistor T are not degraded.

On the other hand Looking in more detail, the oxide semiconductor layer 107 is a hydrogen (H ₂₎ by the reaction of the gas and is to act as a carrier (carrier) in the hydrogen (H ₂₎ atoms semiconductor thin oxide semiconductor layer 107 is There is a problem that it deteriorates to reduce its lifetime or change into a conductor.

Accordingly, the present invention includes a first protective layer (119a) or the second protective layer (119b) by further forming the buffer layer 200 to the upper portion, the water and hydrogen (H ₂₎ gas from the outside of the oxide semiconductor layer 107 It is possible to prevent the occurrence of the above-described problems.

Thus, the life of the oxide semiconductor layer 107 can be shortened or the oxide semiconductor layer 107 can be prevented from being changed into a conductive material, and the characteristics of the thin film transistor T can be prevented from deteriorating.

In addition, since the phenomenon that the current-voltage characteristic of the thin film transistor T is shifted in the negative direction is suppressed, the display quality deterioration due to the luminance non-uniformity phenomenon is prevented, and the effect of improving the reliability of the thin film transistor T .

Here, the buffer layer 200 may be made of a metal oxide film or an inorganic _{film, Al 2 O 3, AlON,} TiO 2, ZrO 2, HfO 2, Ta 2 O5, Nb 2 O 5, Y 2 O 3, MbO, CeO ₂ , La ₂ O ₃ , Ln ₂ O ₃ , PrAlO ₃ , Er ₂ O ₃ , HfAlO, HfSiO, ZrSiO, ZrAlO, HfON, HfSiON, SrTiO ₃ , BaTiO ₃ , SiN and SiBN.

At this time, it is preferable to use Al ₂ O ₃ or AlON which does not inject hydrogen (H ₂ ) gas during the formation of the buffer layer 200. That is, in the process of forming the buffer layer 200 on the first passivation layer 119a or the second passivation layer 119b, the oxide semiconductor layer 107 reacts with hydrogen (H ₂ ) gas injected into the chamber It is preferable to use Al ₂ O ₃ or AlON capable of forming the buffer layer 200 without injecting a hydrogen (H ₂ ) series gas.

The buffer layer 200 made of Al ₂ O ₃ or AlON has a transparent property and a high insulating property, and hydrogen (H ₂ ) and moisture blocking effect are very high even at a low thickness.

Here, if the buffer layer 200 is made of _{Al 2 O 3, Al 2 O} 3 in the buffer layer is formed to a thickness of 500 ~ 1000㎛, Al ₂ O ₃ and the buffer layer is preferably formed to a thickness of 500Å, a buffer layer (200 ) Is made of AlON, the AlON buffer layer is formed to a thickness of 500 to 2000 mu m, and the thickness of the AlON buffer layer is preferably 1000 ANGSTROM.

Here, the water vapor transmission rate (WVTR) of the thin film transistor T including the oxide semiconductor layer 107 is excellent at 10-2 g / cm < 2 > day, and the oxide semiconductor layer 107 ), Moisture or hydrogen (H ₂ ) does not permeate.

division Thickness (Å) WVTR (g / cm2day) Al ₂ O ₃
500 3.7 * 10 ^-2 1000 4.4 * 10 ^-2 Alon

500 1.1 * 10 ^-1 1000 2.8 * 10 ^-2 1000 5 * 10 ^-3

Referring to the above table (1), it can be seen that Al ₂ O ₃ satisfies the moisture barrier function of the thin film transistor (T) when the thickness is 500 Å. It can be seen that the ALON satisfies moisture blocking ability of the thin film transistor (T) when the thickness is 1000 ANGSTROM.

Table 2 below shows the experimental results of measuring the threshold voltage of the thin film transistor T of the array substrate 100 including the buffer layer 200 according to the embodiment of the present invention.

Here, the experiment was performed by comparing the present invention in which the buffer layer 200 was formed on the first passivation layer 119a and the case where no buffer layer was formed. The hydrogen source (H ₂ (T) including the oxide semiconductor layer 107 in the process of forming a silicon nitride (SiNx) film by using a source of silicon nitride (SiNx).

Buffer layer Thickness (Å) Threshold voltage change High temperature chamber (85 ℃) Early 15Hr 60Hr 190Hr 500Hr - -1.2 -14.1 Conducting Conducting Conducting Al ₂ O ₃ 150 -0.1 -2.6 -1.4 -3.1 -3.0 500 0.1 -3.2 -5.7 -5.8 -5.6 1000 0.2 -4.9 -3.8 -4.6 -4.8 Alon 1000 0.7 -5.1 -6.6 -9.3 -9.0

Referring to Table 2, it can be seen that the threshold voltage of the thin film transistor without a buffer layer increases by 14.1 when the time passes within 15 hours in the high temperature chamber, compared to the threshold voltage of the initial thin film transistor. in the process of forming a silicon nitride (SiNx) hydrogen (H ₂₎ it is to penetrate into the oxide semiconductor layer of the thin-film transistor, an oxide semiconductor layer is in the hydrogen (H ₂₎ atom is a semiconductor thin film by the reaction of hydrogen (H ₂₎ This is because it serves as a carrier.

It is confirmed that the oxide semiconductor layer 107 becomes conductive after 60 hours of the thin film transistor T has passed.

When the oxide semiconductor layer 107 is made conductive, the characteristics of the thin film transistor T are lowered and the current-voltage characteristic of the thin film transistor T is shifted in the negative direction over time .

When the thin film transistor T having the oxide semiconductor layer 107 is shifted in the negative direction, particularly when such a thin film transistor T is used as a driving element, the light emission luminance characteristics are changed according to positions in the display device, Quality is also being reduced.

On the contrary, the thin film transistor T having the buffer layer 200 formed on the first passivation layer 119a as in the embodiment of the present invention increases the threshold voltage by -2.6% even after 15 hours in the high temperature chamber, It can be confirmed that the amount of change is very small as compared with the case without the buffer layer.

It is also confirmed that the oxide semiconductor layer 107 does not become conductive even after 60 hours have elapsed. It can be confirmed that the threshold voltage of the thin film transistor T no longer changes even if the time elapses.

This is because the buffer layer 200 formed on the first passivation layer 119a blocks the penetration of hydrogen (H ₂ ) into the oxide semiconductor layer 107.

By blocking the penetration of the hydrogen (H ₂ ) into the oxide semiconductor layer 107 as described above, it is possible to prevent the oxide semiconductor layer 107 from being deteriorated to shorten the lifetime, and the oxide semiconductor layer 107 can be prevented from being short- And the characteristics of the thin film transistor T can be prevented from deteriorating.

Further, by suppressing the phenomenon that the current-voltage characteristic of the thin-film transistor T is shifted in the negative direction, there is an effect of preventing the deterioration of the display quality due to the luminance unevenness phenomenon, and finally the reliability of the thin-film transistor T is improved .

The array substrate 100 of the present invention further includes a buffer layer 200 formed on the first passivation layer 119a or the second passivation layer 119b so that the oxide semiconductor layer It is possible to prevent oxygen or hydrogen (H ₂ ) from penetrating into the oxide semiconductor layer 107 through the oxide semiconductor layer 107, thereby preventing the oxide semiconductor layer 107 from deteriorating and shortening the lifetime, It is possible to prevent the problem of changing to the conductor, and it is possible to prevent the characteristics of the thin film transistor T from deteriorating.

Further, by suppressing the phenomenon that the current-voltage characteristic of the thin-film transistor T is shifted in the negative direction, there is an effect of preventing the deterioration of the display quality due to the luminance unevenness phenomenon, and finally the reliability of the thin-film transistor T is improved .

3, the buffer layer 200 is formed on the gate insulating layer 105 so that the buffer layer 200 is formed to surround the lower portion of the oxide semiconductor layer 107 This is to prevent hydrogen (H ₂ ) from penetrating into the oxide semiconductor layer 107 from the gate insulating film 105 made of silicon oxide (SiO 2) or silicon nitride (SiN x).

4, the first buffer layer 200a is formed on the gate insulating layer 105 and the second buffer layer 200b is formed on the upper portion of the oxide semiconductor layer 107, that is, the first protective layer 119a. or 2 to form the upper protective layer (119b), the oxide can be prevented from penetrating the hydrogen (H ₂₎ from the outside to the semiconductor layer 107 from the gate insulating film 105.

Meanwhile, a buffer layer made of Al ₂ O ₃ and a buffer layer made of AlON can be formed through a sputtering process or an ALD (Atomic Layer Deposition) process. Through a sputtering process, a buffer layer made of Al ₂ O ₃ or AlON (H ₂ ) -free gas is not injected during the process, so that the hydrogen-free (H ₂ ) free process can be performed. Therefore, the hydrogen content in the thin film transistor T can be made very low.

When a buffer layer made of Al ₂ O ₃ or AlON is formed through an ALD process, a very homogeneous buffer layer can be formed, and a buffer layer having a very high moisture permeability can be formed.

5A to 5G are cross-sectional views illustrating steps of manufacturing a portion of one pixel region of an array substrate including a thin film transistor (T) according to an embodiment of the present invention.

Here, for convenience of description, a portion where the thin film transistor (T in FIG. 1) in each pixel region P is to be formed will be defined as a switching region TrA.

First, as shown in Fig. 5A, a gate electrode 103, a gate wiring (not shown), a gate insulating film 105, an oxide semiconductor layer 107, an etch stopper 115, a source And drain electrodes 111 and 113 and a data line 117 are formed.

Here, the gate electrode 103, the gate insulating film 105, the oxide semiconductor layer 107, and the source and drain electrodes 111 and 113 form a thin film transistor (T).

The oxide semiconductor layer 107 has an amorphous structure doped with aluminum (Al), nickel (Ni), copper (Cu), tantalum (Ta), molybdenum (Mo), hydrogen fluoride (Hf), or titanium A gate electrode 103 provided in the switching region TrA is formed by depositing zinc oxide, tin oxide, Ga-In-Zn oxide and In-Sn oxide through sputtering, And an island-shaped oxide semiconductor layer 107 is formed so as to overlap with the island-shaped oxide semiconductor layer 107.

Although the etch stopper 115 is formed on the center of the oxide semiconductor layer 107 in the shape of an island in the drawing, the etch stopper 115 is formed on the entire surface of the substrate 101, A semi-conductor contact hole may be provided to expose the single surface.

Next, as shown in FIG. 5B, the source and drain electrodes 111 and 113 are formed by a plasma chemical vapor deposition (PECVD) method. Then, a mask process is performed to pattern the source and drain electrodes 111 and 113 to expose the drain electrode 113 The first passivation layer 119a including the first drain contact hole 114a is formed.

Next, as shown in FIG. 5C, a buffer layer 200 made of Al ₂ O ₃ or AlON is formed on the first protective layer 119a through a sputtering process or an ALD process.

In this case, when the buffer layer 200 is formed of Al ₂ O ₃ , an O ₂ gas is injected into the chamber to form an Al ₂ O ₃ buffer layer on the first protective layer 119a by a sputtering process, In the case of AlON, O ₂ gas and N ₂ gas are injected into the chamber, and an AlON buffer layer is formed on the first passivation layer 119a by a sputtering process.

At this time, in the process of forming the buffer layer 200, a hydrogen (H ₂ ) -type gas is not injected and a hydrogen-free (H ₂ ) free process can be performed. Therefore, the hydrogen (H ₂ ) content in the thin film transistor T can be made very low.

In the case of forming the buffer layer 200 made of Al ₂ O ₃ or AlON through the ALD process, H ₂ O and O ₃ gas are injected or an O ₂ plasma is injected to form a very homogeneous buffer layer 200 can do.

Next, as shown in FIG. 5D, an organic insulating layer (not shown) is formed by coating photoacryl on the entire surface of the substrate 101 over the buffer layer 200, And a second drain contact hole 114b exposing the drain electrode 113 in correspondence with the first drain contact hole 114a of the first passivation layer 119a.

At this time, the buffer layer 200 is patterned through a dry etching process using the second drain contact hole 114b as a mask, thereby exposing the drain electrode 113. [

The first and second drain contact holes 114a and 114b are formed by sequentially laminating a first passivation layer 119a and a second passivation layer 119b on the substrate 101, .

Next, as shown in FIG. 5E, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the second passivation layer 119b, A common electrode 121 having a shape corresponding to the front surface of the display region and exposed to the respective switching regions TrA is formed by patterning.

Next, as shown in FIG. 5F, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the common electrode 121 to form a third protective layer 119c .

The third passivation layer 119c is then patterned to form a third drain contact hole 114c exposing the drain electrode 113 corresponding to the first and second drain contact holes 114a and 114b.

Next, as shown in FIG. 5G, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the third passivation layer 119c and the mask process is performed A plurality of openings op in the form of a bar are formed in contact with the drain electrode 113 through the first to third drain contact holes 114a, 114b and 114c in each pixel region P The pixel electrode 125 is formed to complete the array substrate 100 according to the embodiment of the present invention.

The array substrate 100 thus fabricated has a fringe field switching mode.

Alternatively, the pixel electrodes 125 may be formed in a plate shape for each pixel region P as a modification. At this time, a part of the pixel electrode 125 may be formed so as to overlap with a gate wiring (not shown) to constitute a storage capacitor.

If the plurality of pixel electrodes 125 and the common electrode 121 are arranged on the same layer in each pixel region P, the IPS mode operation may be performed.

Although the buffer layer 200 is formed on the first passivation layer 119a, it is also possible to form the buffer layer 200 on the second passivation layer 119b. At this time, the buffer layer 200 may be patterned through dry etching using the third drain contact hole 114c as a mask to expose the drain electrode 113.

Meanwhile, the array substrate 100 of the present invention has an effect of reducing the bezel of the OLED 300 (see FIG. 6) when applied to the OLED 300 (see FIG. 6) Let's take a look.

6 is a cross-sectional view schematically showing an OLED including an array substrate according to an embodiment of the present invention.

Here, for convenience of description, a region in which the driving TFT and the switching thin film transistor DTr (not shown) are formed in the pixel region P will be defined as the element region A. [

As shown in the drawing, the OLED 300 including the array substrate 100 of FIG. 5G according to the embodiment of the present invention includes an array substrate on which a driving and switching thin film transistor DTr (not shown) and a light emitting diode E are formed 301 and an encapsubstrate 302 for encapsulation.

A thin film transistor DTr (not shown) having an oxide semiconductor layer 303 as a switching or driving element is provided in the pixel region P on the array substrate 301.

Although not shown in the figure, gate lines and data lines which define the pixel regions P in which the driving and switching thin film transistors DTr (not shown) are provided and which intersect with each other are provided.

A gate electrode 303 is formed in the element region A of the array substrate 301 and a gate electrode 303 is formed on the entire surface of the substrate 301 over the gate electrode 303. [ A gate insulating film 305 is formed.

An oxide semiconductor layer 307 is formed on the gate insulating film 305. An etch stopper 315 is formed on the oxide semiconductor layer 307. A gate electrode 303 is formed on the etch stopper 315, The source and drain electrodes 311 and 313 are formed so as to be spaced apart from each other.

At this time, the gate electrode 301, the source and drain electrodes 313 and 315, and the oxide semiconductor layer 307 form a driving thin film transistor DTr.

Though not shown in the figure, the switching thin film transistor (not shown) has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

A first interlayer insulating film 319a is formed on the entire surface of the array substrate 301 above the source and drain electrodes 311 and 313. A first interlayer insulating film 319a is formed on the first interlayer insulating film 319a, Drain contact hole 314a.

A buffer layer 200 made of Al ₂ O ₃ or AlON is formed on the first interlayer insulating film 319 a including the first drain contact hole 314 a.

The buffer layer 200 serves to protect the oxide semiconductor layer 307. The array substrate 301 according to the present invention can prevent moisture and hydrogen (H ₂ ) from penetrating into the oxide semiconductor layer 307 from outside .

As a result, the oxide semiconductor layer 307 can be prevented from being shortened to shorten the lifetime, and the problem of the oxide semiconductor layer 307 being changed into a conductive material can be prevented. Thus, the driving and switching thin film transistor DTr (not shown) Can be prevented from deteriorating.

Further, the phenomenon that the current-voltage characteristics of the driving and switching thin-film transistor (DTr, not shown) is shifted in the negative direction is suppressed, and the display quality deterioration due to the luminance non-uniformity phenomenon is prevented. (DTr, not shown).

A second interlayer insulating film 319b having a flat surface is formed on the buffer layer 200. A second drain contact hole 314b corresponding to the first drain contact hole 314a is formed in the second interlayer insulating film 319b. .

An anode electrode 321 (anode) is formed in a region where the image is substantially displayed on the second interlayer insulating film 319b, connected to the drain electrode 313 of the driving and switching thin film transistor DTr The anode electrode 321 is made of, for example, a material having a relatively high work function value, and serves as a constituent element of the light emitting diode E.

The anode electrode 323 is formed for each pixel region P and a bank 327 is disposed between the anode electrodes 321 formed for each pixel region P. [

That is, the anode 321 is divided into the pixel regions P with the banks 327 as boundary portions for the respective pixel regions P.

An organic emission layer 323 is formed on the anode electrode 321.

Here, the organic light emitting layer 323 may be formed of a single layer made of a light emitting material. In order to increase the light emitting efficiency, a hole injection layer, a hole transport layer, an emitting material layer, , An electron transport layer (electron transport layer), and an electron injection layer (electron injection layer).

In general, the organic light emitting layer 323 may emit red (R), green (G), blue (G), and blue (B) a separate organic material emitting a color is used in a pattern.

A cathode electrode 325 forming a cathode is formed on the organic light emitting layer 323.

At this time, the cathode electrode 325 may be made of an opaque conductive material, for example, aluminum (Al), aluminum alloy (AlNd), silver (Ag), magnesium (Mg) Gold (Au), and aluminum magnesium alloy (AlMg).

When a predetermined voltage is applied to the anode electrode 321 and the cathode electrode 325 according to a selected color signal, the OLED 300 emits electrons supplied from the anode electrode 321 and electrons supplied from the cathode electrode 325, And is transported to the light emitting layer 323 to form an exciton. When the exciton transitions from the excited state to the ground state, light is emitted and emitted in the form of visible light.

At this time, the emitted light passes through the cathode electrode 321 and exits to the outside, so that the OLED 300 realizes an arbitrary image.

A protective film 329 in the form of a thin thin film is formed on the driving and switching thin film transistor DTr and the light emitting diode E and an encaps substrate 302 is provided on the protective film 329 do.

The array substrate 301 and the in-cap substrate 302 are bonded to each other through the adhesive layer 303 having adhesive properties.

Thereby, the OLED 300 is encapsulated.

When the protective film 329 is formed of a single film, the protective film 329 may be formed of silicon nitride (SiNx) ) Or a silicon oxynitride film (SiON).

Or the protective film 329 is a multi-layered film, the protective film 329 may be composed of an organic film / inorganic film or an inorganic film / organic film, wherein each of the inorganic film and the organic film may be formed by stacking two or more films .

The inorganic film may be formed of a silicon oxide film (SiO2), silicon nitride (SiNx), silicon oxide nitride film (SiON), aluminum oxide (AlOx), aluminum nitride (AlO), TIO, ZnO, a monomer or a polymer thin film may be used. Examples of the monomer include acrylate monomer, phenylacetylene, diamine and dianhydride, siloxane, silane, , Parylene, etc. may be used.

As the polymer thin film, an olefin-based polymer (polyethylene, polypropylene), polyethylene terephthalate (PET), fluororesin, polysiloxane, or the like can be used.

Meanwhile, as the hydrogen (H ₂ ) gas is injected in the process of forming the protective film 329, the hydrogen (H ₂ ) reacts with the oxide semiconductor layer 307 of the driving and switching thin film transistor DTr (not shown) The OLED 300 of the present invention can prevent the hydrogen (H ₂ ) from penetrating into the oxide semiconductor layer 307 by forming the buffer layer 200 on the first interlayer insulating film 319 a have.

As a result, the oxide semiconductor layer 307 can be prevented from being shortened to shorten the lifetime, and the problem of the oxide semiconductor layer 307 being changed into a conductive material can be prevented. Thus, the driving and switching thin film transistor DTr (not shown) Can be prevented from deteriorating.

Further, the phenomenon that the current-voltage characteristics of the driving and switching thin-film transistor (DTr, not shown) is shifted in the negative direction is suppressed, and the display quality deterioration due to the luminance non-uniformity phenomenon is prevented. (DTr, not shown).

In recent trends, it is required that the OLED 300 has a bezel region at the outer edge, which is a non-light emitting region excluding an effective light emitting region in which an image is displayed, as small as possible. Oxygen and moisture from the outside are supplied from the outside through the narrow bezel to the OLED The oxide semiconductor layer 307 may be deteriorated to shorten the lifetime and the oxide semiconductor layer 307 may be converted into a conductive material through the OLED 300. The OLED 300 according to the present invention may have a structure The buffer layer 200 is formed on the first interlayer insulating film 319a so that the buffer layer 200 completely covers the oxide semiconductor layer 307 so that the hydrogen H ₂ penetrates into the oxide semiconductor layer 307 Can be prevented.

This makes it possible to prevent the characteristics of the switching and driving thin film transistors (not shown) (DTr) from deteriorating.

That is, the OLED 300 of the present invention can prevent oxygen and moisture from penetrating into the oxide semiconductor layer 307 while implementing a narrow bezel. Therefore, it is possible to prevent the oxide semiconductor layer 307 from deteriorating and to shorten the lifetime and to prevent the oxide semiconductor layer 307 from being changed into a conductive material, so that the thickness of the switching and driving thin film transistor (not shown) It is possible to prevent degradation of characteristics.

In addition, by suppressing the phenomenon that the current-voltage characteristics of the switching and driving thin film transistors (not shown, DTr) are shifted in the negative direction, there is an effect of preventing display quality deterioration due to the luminance non-uniformity phenomenon. Finally, (Not shown, DTr).

In the above description, the bottom gate type in which the gate electrode 301 is located under the oxide semiconductor layer 307 is shown as an example. As a modification of the bottom gate type, the oxide semiconductor layer 307, May be formed as a top gate type transistor located under the gate electrode 301. [

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

100: array substrate
101: substrate
103: gate electrode, 105: gate insulating film, 107: oxide semiconductor layer
111, 113: source and drain electrodes, 115: etch stopper
114a, 114b and 114c: first to third drain contact holes
117: data line, 119a, 119b, 119c: first to third protective layers
121: common electrode, 125: pixel electrode
200: buffer layer

Claims (20)

A substrate on which a plurality of pixel regions are defined;
A gate electrode, a gate insulating film located above the gate electrode, an oxide semiconductor layer located above the gate insulating film, and source and drain regions spaced apart from each other above the oxide semiconductor layer, A thin film transistor including an electrode;
A first passivation layer exposing the drain electrode over the thin film transistor;
A first buffer layer located above or below the oxide semiconductor layer on the substrate;
The first electrode contacting the drain electrode
≪ / RTI >
The method according to claim 1,
Wherein the first buffer layer is located above the first passivation layer.
The method according to claim 1,
A second protective layer is disposed on the first protective layer, and the first buffer layer is located on the second protective layer.
The method of claim 3,
A second electrode is formed on the second protection layer, a third protection layer is formed on the second electrode, and the first to third protection layers include a drain contact hole exposing the drain electrode, Wherein the first electrode is located above the third passivation layer.
The method according to claim 1,
Wherein the first buffer layer is located above the gate insulating film.
5. The method of claim 4,
And a second buffer layer is located above the oxide semiconductor layer.
The method according to claim 1,
The first buffer layer is _{Al 2 O 3, AlON, TiO} 2, ZrO 2, HfO 2, Ta 2 O5, Nb 2 O 5, Y 2 O 3, MbO, CeO 2, La 2 O 3, Ln 2 O 3, Wherein the substrate is made of one selected from the group consisting of PrAlO ₃ , Er ₂ O ₃ , HfAlO, HfSiO, ZrSiO, ZrAlO, HfON, HfSiON, SrTiO ₃ , BaTiO ₃ , SiN and SiBN.
8. The method of claim 7,
When the first buffer layer is made of Al ₂ O ₃ , the first buffer layer has a thickness of 500 to 1000 μm, and when the first buffer layer is made of AlON, the first buffer layer has a thickness of 500 to 2000 μm. .
The method according to claim 1,
And an etch stopper is disposed on the oxide semiconductor layer, wherein the etch stopper is formed in an island shape at a central portion of the oxide semiconductor layer, or formed on the entire surface of the substrate, And a hole is provided on the substrate.
The method according to claim 1,
A bank formed on an edge of the first electrode above the first electrode and formed at a boundary between the pixel regions;
An organic light emitting layer formed above the first electrode;
An anode electrode formed on the organic light emitting layer;
And a protective film covering the anode electrode.
11. The method of claim 10,
And an in-cap substrate is bonded to an upper portion of the protective film through an adhesive layer.
A gate electrode, an oxide semiconductor layer, and source and drain electrodes spaced apart from each other in each pixel region on a substrate on which a plurality of pixel regions are defined, wherein a first buffer layer is provided on an upper portion or a lower portion of the oxide semiconductor layer Thereby forming a thin film transistor;
Forming a first electrode in contact with a drain electrode of the thin film transistor
≪ / RTI >
13. The method of claim 12,
Wherein a gate insulating film is formed on the gate electrode, and the first buffer layer is formed on the gate insulating film.
14. The method of claim 13,
And a second buffer layer is formed on the oxide semiconductor layer.
13. The method of claim 12,
A first passivation layer is formed on the source and drain electrodes to expose the drain electrode, and the first buffer layer is formed on the first passivation layer.
16. The method of claim 15,
A second protective layer is formed on the first protective layer, and the first buffer layer is formed on the second protective layer.
13. The method of claim 12,
The first buffer layer may include Al ₂ O ₃ Or AlON, and is formed through a sputtering process or an ALD (Atomic Layer Deposition) process.
18. The method of claim 17,
Wherein the first buffer layer made of Al ₂ O ₃ is formed by a sputtering process by injecting O 2 gas into the chamber.
18. The method of claim 17,
Wherein the first buffer layer made of AlON is formed by a sputtering process by injecting O ₂ gas and N ₂ gas into the chamber.
18. The method of claim 17,
The first buffer layer is implanted with H ₂ O and O ₃ gas or O ₂ Wherein the plasma is injected to form an ALD process.

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