KR20150060972A - Control system, master programmable controller, slave programmable controller, and control method - Google Patents

Control system, master programmable controller, slave programmable controller, and control method Download PDF

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KR20150060972A
KR20150060972A KR1020157011274A KR20157011274A KR20150060972A KR 20150060972 A KR20150060972 A KR 20150060972A KR 1020157011274 A KR1020157011274 A KR 1020157011274A KR 20157011274 A KR20157011274 A KR 20157011274A KR 20150060972 A KR20150060972 A KR 20150060972A
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programmable controller
delay time
transmission delay
slave
master
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KR101726743B1 (en
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유키테루 유오
아키라 후지모리
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후지 덴키 가부시키가이샤
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/052—Linking several PLC's
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/12—Plc mp multi processor system
    • G05B2219/1215—Master slave system

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

In the control method using a plurality of control units in combination of the controlled device 130 and the programmable controller 120, the programmable controllers establish communication with each other and share the data using the common memory. When receiving the reception complete frame which is a response to the transmission delay time request frame, the master programmable controller calculates the transmission delay time from the difference between the time when the transmission delay time request frame was transmitted and the time when the reception complete frame was received. Calculates a time and transmits a transmission delay time notification frame including the transmission delay time to the slave programmable controller. When the slave programmable controller receives the transmission delay time notification frame, the slave programmable controller calculates the transmission delay time included in the transmission delay time notification frame as And synchronizes the slave programmable controller to the master programmable controller based on the transmission delay time.

Description

CONTROL SYSTEM, MASTER PROGRAMMABLE CONTROLLER, AND Slave Programmable Controller < RTI ID = 0.0 >

The present invention relates to a control system, a master programmable controller, a slave programmable controller, and a control method in which a plurality of programmable controllers each controlling a controlled device are connected so as to be able to communicate with each other.

In a large-scale control system, a layer structure of a controller is taken in view of the ease of construction and maintenance of the system, and the layers are connected by a network. For example, in a control system, a plurality of programmable controllers are connected to one management device via a network, and one or a plurality of controlled devices are connected to each of the programmable controllers. Then, the programmable controller receives the control command from the upper management apparatus, analyzes the control command, and controls the lower controlled apparatus.

In such a control system, when the programmable controller receives a control command from the management apparatus, the control process proceeds in a range in which the programmable controller and the controlled apparatus are closed. Then, the programmable controller transmits only the control result to the management apparatus. Therefore, in the management apparatus, the control results are collected at respective timings within the programmable controller.

It is also possible to establish communication with programmable controllers under the same management device, and transmit and receive control results. For example, a technology is known in which scheduling for transmitting / receiving control data between programmable controllers is performed, and a switch provided between the programmable controllers is switched according to the scheduling (for example, Patent Document 1).

Japanese Patent Application Laid-Open Publication No. 2012-108696

By using the above-described technique, not only the management apparatus but also programmable controllers can exchange information. However, since a plurality of programmable controllers in the control system operate at independent timings in accordance with a control command of the management apparatus, the programmable controller and the controlled apparatus can be synchronized (synchronized), but between the programmable controllers It becomes a state in which synchronization can not be taken.

For example, when the management apparatus collects information from a plurality of programmable controllers, since the timing at which information is generated differs for each programmable controller, the context relationship of the information is unclear and strict control is difficult.

Further, it is not clear whether the information of the other programmable controller and the information of the own programmable controller are generated first, and the generation timing is different from each other, so that the information of the other programmable controller can not be used easily.

Further, when the controlled device is transplanted to another programmable controller in accordance with the change in the arrangement of the controlled devices, the address of the accessed destination and the contents of the control command have to be changed. In addition, since it can not be determined that information on the controlled device is generated at the same timing as before the batch change, it has to be designed in consideration of which programmable controller is connected and how much delay will occur. Further, it was necessary to check again that the problem did not occur due to the design change.

Therefore, even in a control system having substantially the same function, the established application can not be used universally depending on the arrangement and operation of the controlled apparatus in the end user, so that the respective correspondence to the transplantation of the controlled apparatus It was impossible to avoid.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a control system, a master programmable controller, a slave programmable controller, and a control method capable of improving portability and improving control accuracy and stability in order to solve such problems .

In order to solve the above problem, in the control system of the present invention in which a plurality of control units each including a controlled device and a programmable controller that controls a controlled device based on a program are provided, the programmable controller includes: And a common memory for sharing data with other programmable controllers through a communication unit. The programmable controller includes a master programmable controller functioning as a master, a slave functioning as a slave, There is a programmable controller, and the master programmable controller also transmits a transmission delay time request frame for measuring the transmission delay time between the master programmable controller and the slave programmable controller, The transmission delay time request frame and the transmission delay time frame from the difference between the time when the transmission delay time request frame was transmitted and the time when the reception completion time frame was received, And a delay time measuring section for calculating a time and transmitting a transmission delay time notification frame including a transmission delay time to the slave programmable controller. The slave programmable controller also receives the transmission delay time request frame, A delay time receiving section for receiving the transmission delay time notification frame and transmitting the transmission delay time notification frame to the programmable controller and receiving the transmission delay time notification frame; And a synchronization correcting section for synchronizing the synchronization signal with the grayscale controller.

In order to solve the above problems, a master programmable controller of the present invention that controls a controlled device based on a program and functions as a master includes a slave programmable controller functioning as a slave and a communication unit establishing communication with the controlled device A common memory for sharing data with the slave programmable controller through a communication unit and a transmission delay time request frame for measuring a transmission delay time between the master programmable controller and the slave programmable controller are transmitted to the slave programmable controller, Upon receiving the reception complete frame, which is a response to the request frame, the transmission delay time is calculated from the difference between the time when the transmission delay time request frame was transmitted and the time when the reception completion frame was received Acid, and the transmission delay time notification frame including the transmission delay time, characterized in that it includes a delay time measuring unit for transmission to a slave programmable controller.

In order to solve the above problems, a slave programmable controller of the present invention, which controls a controlled device based on a program and functions as a slave, includes a programmable controller and a controlled device including a master programmable controller functioning as a master When receiving a transmission delay time request frame for measuring a transmission delay time between the master programmable controller and the slave programmable controller, When a transmission completion time frame including a transmission time delay frame is received from the master programmable controller, a reception complete frame, which is a response to the time request frame, is transmitted to the master programmable controller. And a synchronization correcting section for synchronizing the slave programmable controller with the master programmable controller based on the transmission delay time.

In order to solve the above problems, in the control method of the present invention in which a plurality of control units are combined using a controlled device and a programmable controller that controls the controlled device on the basis of the program, the programmable controller may be a programmable controller A master programmable controller that establishes communication with a controller and a controlled device and shares data with another programmable controller and a common memory through a communication unit and functions as a master among the programmable controllers includes a master programmable controller and a slave The slave programmable controller transmits a transmission delay time request frame for measuring a transmission delay time with the slave programmable controller to the slave programmable controller, The master programmable controller transmits a reception completion frame, which is a response to the transmission delay time request frame, to the master programmable controller. When the master programmable controller receives the reception completion frame, Calculates a transmission delay time from the difference between the time when the frame is received and the transmission delay time notification frame including the transmission delay time to the slave programmable controller. When the slave programmable controller receives the transmission delay time notification frame , The transmission delay time included in the transmission delay time notification frame is acquired, and the slave programmable controller is synchronized with the master programmable controller based on the transmission delay time.

According to the present invention, the portability of the control system can be enhanced, and the control precision and stability can be improved.

Fig. 1 is an explanatory view showing a schematic relationship of each apparatus constituting the control system.
2 is an explanatory diagram showing a schematic configuration of a control system.
3 is a diagram showing an example of the hardware configuration of the CPU module.
Fig. 4 is a functional block diagram for explaining respective functional units of the CPU module; Fig.
5 is a time chart for explaining an example of the synchronization correction processing.
6 is a diagram showing an example of a schematic sequence of the synchronization correction process.
7 is a time chart for explaining transmission and reception of data in the CPU module.
Fig. 8 is an explanatory view for explaining the change of the arrangement of the controlled devices. Fig.
9 is an explanatory view showing a memory map in the common memory.
10 is an explanatory diagram showing an application example of the common memory.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials and other specific numerical values shown in these embodiments are merely examples for facilitating the understanding of the invention and are not intended to limit the present invention except for the case of specifics. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be omitted, and elements (elements) not directly related to the present invention are not shown.

In a control system applied to a large-scale plant or the like, division control of a control application by a plurality of control units (also referred to as environment setting) is performed according to the complexity of processing of the entire system and the physical arrangement. Here, the control unit mainly shows a combination of a programmable controller and a controlled device controlled by the programmable controller. In the control system, a plurality of such control units are prepared and connected to a management apparatus that controls the entire control system. Each of the devices constituting the control system will be described below.

[Control system (100)]

Fig. 1 is an explanatory view showing a schematic relationship of each device constituting the control system 100, and Fig. 2 is an explanatory diagram showing a schematic configuration of the control system 100. As shown in Fig. The control system 100 includes a management device 110, a plurality of programmable controllers 120, and a plurality of controlled devices 130. The management device 110 and the plurality of programmable controllers 120 are connected to each other by a network wiring 140 by a Ethernet (registered trademark) such as a GigaBase do. The plurality of programmable controllers 120 and the plurality of controlled devices 130 are each connected as a device level network via a dedicated connection wiring 142, for example.

The management apparatus 110 collectively controls a plurality of programmable controllers 120 so that the entire control system 100 operates in accordance with the flow of steps determined for the application. For example, the management apparatus 110 collects status information and control results from the respective programmable controllers 120, and outputs various control commands to the respective programmable controllers 120 in accordance with the collected information .

2, the programmable controller 120 includes a CPU module 122, a communication module 124, an input / output (I / O) module 126, a power module And a plurality of modules such as a memory 128 and the like.

Here, in order to realize an application, the CPU module 122 downloads an execution program divided for each control unit from the management apparatus 110, executes the execution program, or displays the operation status of the control unit It should be displayed on a non-monitor. At this time, based on the control command received from the management device 110, the sensor detection result of the controlled device 130 input via the input / output module 126, and information held by the other programmable controller 120, (130). The CPU module 122 also transmits to the management device 110 data such as status information indicating its own status, detection result of the sensor, and control result.

The communication module 124 is connected to the management apparatus 110, the other programmable controller 120, and other modules via a Ethernet (registered trademark) such as a GigaBase as a controller level network And can establish communication with each other. However, the data may be exchanged between the modules by a bus provided in the base board. In the present embodiment, the communication module 124 is formed integrally with the CPU module 122. [

The input / output module 126 performs input / output management for the controlled device 130. For example, if the controlled device 130 is a sensor, the sensor detection result is collected. If the controlled device 130 is an electric motor, a control command represented by discrete is transmitted and the control result is collected. The power supply module 128 supplies power to each module such as the CPU module 122, the communication module 124, and the input / output module 126.

1, the controlled device 130 is constituted by a sensor for detecting various states in a factory automation (FA), an electric machine such as an electric motor that operates according to the detection result of the sensor, and an encoder.

Such a control system 100 can be applied to various control objects. For example, when the control system 100 is applied to a manufacturing execution system (MES), a center sealer unit, a film unit, a rolling unit A programmable controller 120 is connected to a production apparatus such as a rolling unit.

For example, the programmable controller 120 reads the operation state of the production equipment from the input / output module 126 and controls the rotation of the electric motor in the production equipment through a motor driver or the like. The management apparatus 110 performs the collection of information on a unit basis of each programmable controller 120 and the transmission of a control command. In this manner, it becomes possible to perform overall production support management such as process control, quality control, and production volume management as a whole in the control system 100 as a whole. Hereinafter, the CPU module 122 of the programmable controller 120 will be described in detail.

[CPU module (122)]

3 is a diagram showing an example of a hardware configuration of the CPU module 122. As shown in Fig. 3 includes an input unit 150, an output unit 152, a communication unit 154, a logic circuit 156, a reference signal generation unit 158, a CPU 160, A ROM 162, a RAM 164, and a common memory 166. In addition, The input unit 150, the output unit 152, the logic circuit 156, the CPU 160, the ROM 162, the RAM 164, and the common memory 166 are connected to a common bus So that the data can be moved by the control unit 168.

The input unit 150 includes a keyboard, a pointing device such as a mouse and a touch panel, and an audio input device. The input unit 150 accepts various operations such as execution of a program by a user.

The output unit 152 is constituted by a liquid crystal display, an organic EL (Electro Luminescence) display, and the like, and displays various windows, data, and control programs necessary for operating the CPU module 122 that performs processing in this embodiment Displays status and control results.

The communication unit 154 functions as the communication module 124 described above and establishes communication with the management apparatus 110, the other programmable controller 120, and the input / output module 126 via Ethernet (registered trademark). In the present embodiment, the communication unit 154 is built in the CPU 160. [

The logic circuit 156 includes an integrated circuit capable of rewriting a logic circuit such as a CPLD (Complex Programmable Logic Device) or an FPGA (Field-Programmable Gate Array) Circuit is built in.

The reference signal generating unit 158 is constituted by a hardware counter and performs counting and generates a reference signal for the CPU 160 by reaching a count value at a preset reference value. These coefficient values are periodically counted based on the reference value. Here, the reference value is preset in each of the CPU modules 122, and can be changed from the management device 110 or the input unit 150. [ Although the reference signal generator 158 is shown here as being different from the CPU 160 in this embodiment, the reference signal generator 158 may be implemented using a timer counter built in the CPU 160. [ Here, the term " embedded " means that, for example, only the respective functional units used in the CPU 160 can be accessed to the reference signal generation unit 158. [

The CPU 160 controls the entire processing of the CPU module 122, such as various operations and input / output of data, based on a basic program such as an OS (Operating System) and an execution program. The CPU 160 executes the execution program stored in the ROM 162 and uses the RAM 164 as a workpiece area to store the delay time measurement unit 180, the synchronization frame transmission unit 182, A synchronization correction unit 186, an application execution unit 188, a data updating unit 190, The CPU 160 internally stores the communication unit 154 and communicates with the management apparatus 110, the other programmable controller 120, and the input / output module 126 based on the intermediate intervention processing.

The ROM 162 stores the above-mentioned basic program and execution program. As the auxiliary storage device, a storage device such as a hard disk may be provided. The RAM 164 temporarily stores data (for example, status information, detection results of sensors, control results, and the like) generated by executing a part of the basic program or the execution program or executing the execution program. The common memory 166 is a storage area for sharing information with other CPU modules 122 and may be formed as a part of the RAM 164.

[Each functional unit of the CPU module 122]

Fig. 4 is a functional block diagram for explaining respective functional units of the CPU module 122. Fig. As described above, the CPU 160 includes a delay time measurement unit 180, a synchronization frame transmission unit 182, a delay time reception unit 184, a synchronization correction unit 186, an application execution unit 188, a data updating unit 190 , And functions as a data transmission unit 192 as well. Each of these functional units may or may not function when the programmable controller 120 operates as a master (master programmable controller) or as a slave (slave programmable controller). Here, the CPU module 122 in the master programmable controller is the master CPU module 122a, and the CPU module 122 in the slave programmable controller is the slave CPU module 122b. In Fig. 4, functional portions that do not function depending on whether they are a master or a slave are indicated by broken lines.

The present embodiment is not limited to the above-described configuration, and one CPU module 122 has the same configuration so as to be a master CPU module 122a and a slave CPU module 122b.

The delay time measuring unit 180 calculates a delay time for measuring the transmission delay time between the master CPU module 122a and the slave CPU module 122b when the CPU module 122 functions as the master CPU module 122a, Time request frame to an arbitrary slave CPU module 122b. This transmission delay time request frame is a frame in which the format is substantially the same as the synchronization frame to be described later, and data of a predetermined portion (for example, a command portion) in the synchronization frame is different. This transmission delay time request frame is transmitted in synchronization with the reference signal generated by the reference signal generating section 158 in the master CPU module 122a.

Further, the delay time measuring section 180, after receiving the transmission completion delay frame, receives the reception completion frame from the arbitrary slave CPU module 122b, and acquires the time when the reception completion frame is received. The delay time measuring unit 180 calculates the difference between the time when the transmission delay time request frame was transmitted and the time when the reception completion time frame was received from the master CPU module 122a and the arbitrary slave CPU module 122b Lt; / RTI > is calculated. Then, the delay time measuring unit 180 divides the calculated round trip delay time by 2, and transmits a transmission delay time notification frame including the resultant transmission delay time to an arbitrary slave CPU module ( 122b. In this manner, the arbitrary slave CPU module 122b can be notified of the transmission delay time by the network wiring 140. [

When the CPU module 122 functions as the master CPU module 122a, the synchronization frame transmission unit 182 transmits a synchronization frame prepared in advance to the plurality of slave CPU modules 122b in synchronization with the reference signal. This synchronization frame is a signal for matching the count value of the reference signal generator 158 of the slave CPU module 122b with the count value of the reference signal generator 158 of the master CPU module 122a.

The delay time receiving unit 184 receives the transmission delay time request frame from the master CPU module 122a when the CPU module 122 functions as the slave CPU module 122b, , And transmits a reception completion frame to the master CPU module 122a. When receiving the transmission delay time notification frame from the master CPU module 122a, the delay time receiver 184 saves the transmission delay time included in the frame to the RAM 164 or the like. In this way, the slave CPU module 122b can obtain the transmission delay time between the master CPU module 122a and the slave CPU module 122b.

The synchronous correction unit 186 synchronizes the reference signal generated by the reference signal generation unit 158 in the slave CPU module 122b with the transmission delay time . Specifically, upon receiving the synchronization frame from the master CPU module 122a, the synchronization correction unit 186 acquires the count value from the reference signal generation unit 158 and outputs a value corresponding to the transmission delay time (The time conversion value of the coefficient value conversion unit 158) and the acquired coefficient value, derives the correction reference value by subtracting the correction amount from the reference value, temporarily sets the correction reference value as a new reference value, . Therefore, the correction reference value is represented by a reference value - [value corresponding to the transmission delay time - count value of the reference signal generating section 158].

When the correction reference value is set and the reference signal generating unit 158 completes the counting on the correction reference value, the synchronization correcting unit 186 promptly sets the original reference value to the reference signal generating unit 158 ). In this manner, the reference value can be temporarily advanced only by the transmission delay time. In this example, the correction for the transmission delay time is performed at one time, but the present invention is not limited to this case, and the correction may be performed in a plurality of circuits. In the present embodiment, even if the synchronization correction section 186 receives the synchronization frame without obtaining the transmission delay time from the master CPU module 122a, the transmission delay time is set to zero (0) Correction processing may be performed.

Thus, in this embodiment, the reference signal generator 158 of the master CPU module 122a and the reference signal generator 158 of the slave CPU module 122b can be synchronized with high accuracy. Such a synchronization correction process may be performed continuously or intermittently at predetermined intervals.

The application executing section 188 also receives the reference signal as the intermediate intervening signal in accordance with the reference signal generated by the reference signal generating section 158 in either the master CPU module 122a or the slave CPU module 122b, , Executes the execution program, and controls the controlled device 130 through the input / output module 126. Therefore, the execution program is periodically executed according to the reference signal.

When data (for example, status information, detection result of a sensor, control result, and the like) is generated in either the master CPU module 122a or the slave CPU module 122b, the data updating unit 190 updates And updates the contents of the common memory 166 in its own CPU module 122 with the data. The data updating unit 190 transfers the data to the other CPU module 122. [ The data updating unit 190 updates the contents of the common memory 166 in the CPU module 122 based on such data when the data is transferred from the other CPU module 122. [ In this way, data can be shared with the other CPU module 122. The transmission timing at which the data updating unit 190 transmits the data to the other CPU module 122 is predetermined for each CPU module 122 based on the reference signal generating unit 158. [ This transmission timing will be described later in detail.

The data transmitting unit 192 is configured to transmit a request to the management apparatus 110 from among the data generated by the application executing unit 188 by executing the execution program in either of the master CPU module 122a and the slave CPU module 122b And transmits the data to the management apparatus 110. This transmission timing follows the transmission timing of the data updating unit 190. [ In the present embodiment, since the CPU modules 122 are synchronized with each other, data having the same generation timing is collected in the management device 110. [

Hereinafter, the specific control method of the control system 100 will be described separately for the synchronization correction processing and the data sharing processing.

[Synchronization correction processing]

5 is a time chart for explaining an example of the synchronization correction processing. Here, it is assumed that the reference signal of the slave CPU module 122b is delayed by 10 占 퐏 from the reference signal of the master CPU module 122a. The reference value (processing cycle) is 1000 占 퐏 sec, but the present invention is not limited to this, and the setting can be changed appropriately according to the management apparatus 110, for example. Further, the expression for μ sec for simplicity as μ s in the figure.

In Fig. 5, the reference signal generator 158 of the master CPU module 122a performs counting. When the count value reaches the reference value at the time (1) in Fig. 5, the master CPU module 122a outputs the reference signal. Then, the application executing section 188 executes the execution program in accordance with the reference signal. 5, the area of the triangle indicated by hatching represents the transition of the count value, and is reset when the count value increases with time and reaches the count target (for example, the reference value).

In parallel with the master CPU module 122a, the reference signal generator 158 of the slave CPU module 122b also performs counting. And outputs a reference signal when the count value reaches the reference value at the time (2) in FIG. Then, the application executing section 188 executes the execution program in accordance with the reference signal. As described above, the master CPU module 122a and the slave CPU module 122b perform predetermined processing in accordance with independent reference signals, respectively.

When the synchronization correction processing is started in the master CPU module 122a, the delay time measurement unit 180 of the master CPU module 122a transmits a transmission delay time request frame to calculate the transmission delay time (Fig. 5 (3) of FIG. Upon receiving the transmission delay time request frame from the master CPU module 122a, the delay time receiving unit 184 of the slave CPU module 122b sends a reception completion frame to the master CPU module 122a in accordance with the transmission delay time request frame (Fig. 5 (4)).

Then, the delay time measuring unit 180 of the master CPU module 122a calculates the round trip delay time between the master CPU module 122a and the slave CPU module 122b upon receiving the reception completion frame. Then, the delay time measuring unit 180 sends a transmission delay time notification frame including the transmission delay time (200 mu sec) obtained by dividing the calculated round trip transmission delay time (400 mu sec) by 2 to the slave CPU module 122b (Fig. 5 (5)). Upon receiving the transmission delay time notification frame, the delay time receiver 184 of the slave CPU module 122b saves the round trip transmission delay time (equivalent value) included in the frame to the RAM 164 or the like (6).

After the synchronization correction processing is started, the synchronization frame transmission unit 182 of the master CPU module 122a transmits the synchronization frame as an intermediate intervention signal to the slave CPU module 122b (Fig. 5 (7)). Then, the slave CPU module (122b), upon receiving the sync frame at the time of network wiring 140, one-way transmission delay time (200 μ s) through (8) of Fig. 5 a, the synchronization correction unit 186 , And obtains the count value (corresponding to 190 mu sec) from the reference signal generation unit 158 (Fig. 5 (9)). Then, the synchronization correction unit 186, by using the transmission delay time (200 μ sec) and the reference value (1000 μ sec), the reference value - the value corresponding to the transmission delay time-count value of the reference signal generation section 158 ] to obtain the corrected reference value from the 990 μ sec = 1000 (200-190). Then, the synchronization correction unit 186 temporarily sets the correction reference value as a new reference value in the reference signal generation unit 158 (Fig. 5 (10)).

Thereafter, the reference signal generator 158 restarts because the count value reaches the temporary correction reference value 990 占 at the time of (11) in FIG. In this way, the reference signal of the slave CPU module 122b is synchronized with the reference signal of the master CPU module 122a.

6 is a diagram showing an example of a schematic sequence of the synchronization correction process. 6, the synchronization using the master CPU module 122a and the slave CPU module 122b will be described for convenience of explanation. However, the present embodiment is not limited to this, and one master CPU module 122a, The plurality of slave CPU modules 122b can be synchronized with each other.

6, first, the reference signal generator 158 of the master CPU module 122a generates a reference signal (S11), and the reference signal generator 158 of the slave CPU module 122b generates a reference signal , And generates a reference signal independently of the master CPU module 122a (S12). This process is also performed periodically.

When the synchronization correction processing of the master CPU module 122a is started, the delay time measuring section 180 of the master CPU module 122a transmits a transmission delay time request frame to the slave CPU module 122b to calculate the transmission delay time (S13). Upon receiving the transmission delay time request frame, the delay time receiving unit 184 of the slave CPU module 122b transmits the reception completion frame to the master CPU module 122a (S14).

Upon receiving the reception completion frame, the delay time measuring unit 180 of the master CPU module 122a calculates a transmission delay time (S15), for example, and transmits a transmission delay time notification frame including the calculated transmission delay time and the like (S16). Then, the delay time measuring unit 180 transmits the generated transmission delay time notification frame to the slave CPU module 122b via the network wiring 140 (S17). Upon receiving the transmission delay time notification frame, the delay time receiver 184 of the slave CPU module 122b saves the transmission delay time (converted value) included in the transmission delay time notification frame to the RAM 164 or the like S18).

The synchronization frame transmission section 182 of the master CPU module 122a transmits the synchronization frame as an intervening intervention signal to the slave CPU module 122b in synchronization with the reference signal (S19).

When the slave CPU module 122b receives the synchronization frame, the synchronization correction unit 186 acquires the count value from the reference signal generation unit 158 (S20). Then, the synchronization correction unit 186 calculates the reference value - [the value corresponding to the transmission delay time-the count value of the reference signal generation unit 158] using the transmission delay time and the reference value to obtain the correction reference value (S21 ). Then, the correction reference value is temporarily set as a new reference value in the reference signal generator 158 (S22). When the correction reference value is set and the coefficient on the correction reference value is completed, the synchronization correction unit 186 quickly sets the original reference value in the reference signal generation unit 158 (S23).

This synchronization correction process is executed for all the slave CPU modules 122b included in the control system 100. [ In this manner, the reference signal of the slave CPU module 122b is synchronized with the reference signal of the master CPU module 122a. That is, it is possible to synchronize execution programs (applications) operating on each CPU module 122.

[Data Sharing Processing]

With the above-described configuration, all of the CPU modules 122 included in the control system 100 are synchronized. Further, as described above, since the CPU modules 122 are connected to each other by Ethernet (registered trademark) such as a G-band or the like having a wide bandwidth, time is not required for information exchange. Here, sharing of data among a plurality of CPU modules 122 is attempted through a wide-band network on the premise that the CPU module 122 is synchronized in this way.

FIG. 7 is a time chart for explaining transmission and reception of data in the CPU module 122. FIG. 7, three CPU modules (CPU modules A, B, and C in FIG. 7) are taken as an example of a plurality of CPU modules 122. FIG. Here, the synchronization correction processing is already completed, and the three CPU modules A, B, and C are synchronized. Needless to say, the number of CPU modules is not limited to three.

For example, when paying attention to the CPU module A, the application executing section 188 operates periodically in synchronization with the reference signal. Concretely, the execution of the execution program is started at the timing at which the reference signal generator 158 generates the reference signal, that is, at the timing at which the count value of the reference signal generator 158 is reset to 0, (The detection result of the sensor, the control result, and the like). Here, although the execution program is started when the count value is 0, the process may be started after a predetermined time in consideration of the overhead of the management function process preceding the execution program.

Then, the application execution unit 188 inputs the latched data through the input / output module 126, and performs a predetermined calculation based on the execution program. Then, the common memory 166 in the CPU module A is updated by the data (status information, detection result of the sensor, control result, etc.) to which the calculated control result is added. Upon completion of the predetermined calculation, abnormality monitoring and system control processing of the programmable controller 120 are executed up to the next reference signal.

When the next reference signal is generated, the data updating unit 190 refers to the count value of the reference signal generating unit 158 and measures the transmission timing previously allocated to the CPU module A (here, 0). When the transmission timing arrives, the data updating unit 190 sends the data stored in the common memory 166 to the other CPU modules B and C, and the common memory 166 in the CPU modules B and C Update.

In the CPU modules A, B, and C, different transmission timings are assigned. Here, data is transmitted from the CPU module A to the CPU module B, the CPU module C, the CPU module B to the CPU modules A and C, and the CPU module C to the CPU modules A and B in this order Is transmitted. Then, when data is transmitted from one CPU module, the other CPU module receives the data and reflects the data in each common memory 166.

Although the data updating unit 190 reflects the data to another CPU module every time data is generated in each of the CPU modules A, B, and C, the common memory 166 is synchronized in the control system 100 And the data of the other CPU module is automatically updated when the data of the common memory 166 itself is updated.

In this embodiment, the data updating unit 190 refers to the count values of the reference signal generating unit 158 in each of the CPU modules A, B, and C, However, the present invention is not limited to the reference signal generator 158, and a separate counter for starting counting according to the reference signal may be used.

In the common memory system using the common memory 166 in the present embodiment, data transmitted from each of the CPU modules A, B and C is received by all of the CPU modules A, B and C, And develops the received data in its own CPU module. In this manner, it is possible to execute the execution program using the same memory map in each of the CPU modules A, B, and C.

Therefore, by employing the common memory system and sharing data of another CPU module in a synchronized state by the device level network, the controlled device 130 can be easily transferred to any CPU module.

For example, even if the CPU module to which the controlled device 130 belongs is changed by changing the arrangement of the controlled devices 130, the data is reflected to the same memory address of the common memory 166 in the CPU module after the change, Environment can be formed. Hereinafter, the access to the common memory 166 of the data updating unit 190 will be described in detail.

Fig. 8 is an explanatory view for explaining the arrangement change of the controlled device 130. Fig. 8, three CPU modules (a CPU module A, a CPU module B, and a CPU module C in Fig. 8) are taken as an example of a plurality of CPU modules 122. Fig.

For example, when attention is paid to the CPU module B, as shown in FIG. 8A, the CPU module B is provided with the controlled devices D and E corresponding to the sensors and the controlled devices F Are connected. Here, it is assumed that the control command OUTf is sent to the controlled device F corresponding to the electric motor based on the detection results INd and INe of the controlled devices D and E corresponding to the sensors.

In the example of Fig. 8A, the controlled devices D, E, and F are included in the same control unit and all belong to the same CPU module B, so that the control command OUTf is generated in the control unit . That is, in the CPU module B, the application executing section 188 acquires the sensor detection results INd and INe from the controlled devices (D and E) through the input / output module 126, And outputs the generated control command OUTf to the controlled device F. [

As shown in FIG. 8B, the controlled device F remains as it is and the controlled device D belongs to the CPU module A, It is assumed that the device E belongs to the CPU module C. In this embodiment, even in this case, by sharing the data by the common memory 166, the CPU module B can easily refer to the data of the controlled devices D and E at the timing as it is.

FIG. 9 is an explanatory view showing a memory map in the common memory 166. FIG. Here, the common memories 166a, 166b, and 166c are disposed in the CPU modules A, B, and C, respectively. The controlled device D belongs to the CPU module A, the controlled device F belongs to the CPU module B, and the controlled device E belongs to the CPU module C as shown in FIG. 8 (b) I assume the case of belonging.

9, the detection result INd of the sensor acquired from the controlled device D in the CPU module A is stored in the common memory of the CPU module A of its own CPU module A, (166a), and is also stored in the common memories (166b, 166c) of the other CPU modules (B, C). Here, the data of itself is shown by solid lines, and the duplicated data is shown by broken lines. In the synchronized state, the detection result INe of the sensor acquired from the controlled device E in the CPU module C is stored in the common memory 166c of the CPU module C of the CPU module C, And is also stored in the common memories 166a and 166b.

The application execution unit 188 of the CPU module B reads the sensor detection results INd and INe of the controlled devices D and E from the common memory 166b of the CPU module B and performs a predetermined calculation, (F). The application executing section 188 outputs the control command OUTf to the controlled device F belonging to the CPU module B itself through the input / output module 126. [

Here, even when the arrangement of the controlled devices D and E is changed as shown in Figs. 8A and 8B, the reading destination of the sensor detection results INd and INe in the CPU module B is changed to the common memory 166b), it is possible to avoid an unnecessary number of applications that have been established.

10 is an explanatory view showing an example of application of the common memory 166. FIG. 9, the common memories 166a, 166b, and 166c are disposed in the CPU modules A, B, and C, respectively. Then, the controlled device D belongs to the CPU module A, the controlled device F belongs to the CPU module B, and the controlled device E belongs to the CPU module C. [

In the common memory 166 shown in Fig. 10, the detection result INd of the sensor acquired from the controlled device (D) in the CPU module A and the detection result INe of the sensor acquired from the controlled device (E) In addition, a control command OUTf outputted by the CPU module B to the controlled device F is also stored. Accordingly, the application executing section 188 of the CPU module B reads the control command OUTf from the common memory 166b of the CPU module B and directly outputs the control command OUTf to the controlled It is sufficient to output the control command OUTf to the device F.

In this application example, the sensor detection results INd and INe of the controlled devices D and E are read from the common memory 166b of the CPU module B, and a predetermined operation is performed to control the controlled device F Processing for generating the command OUTf may be performed by any device. In other words, it can be executed only by one of the CPU modules A, B, and C, another CPU module, or the management device 110, so that the processing load can be distributed. FIG. 10 shows an example in which the CPU module A executes.

Since the application implemented in this manner treats only the variables of the common memory 166 as its input and output, no matter which load the load of the programmable controller 120 is in the mounting position of the input / output module 126, the application itself There is no need to modify.

The data transmission unit 192 transmits the data requested to be collected by the management apparatus 110 among the data generated by the application execution unit 188 by executing the execution program to the management apparatus 110 at the transmission timing of the data shown in FIG. (110). In the present embodiment, since the CPU modules 122 are synchronized with each other, data having the same generation timing is collected in the management device 110. [

Therefore, since the timing at which the information is generated is not different for each programmable controller 120, the context relationship becomes clear, and strict control becomes possible.

According to the programmable controller 120 described above, the CPU modules 122 are synchronized with each other to share data among a plurality of CPU modules 122 via a wide-band network. Therefore, it is possible to synchronize the information of the application or the controlled device 130 between the control units, thereby improving the portability of the controlled device 130 or the like and improving the control accuracy and stability of the entire control system 100 Lt; / RTI >

By adopting the control system 100, it is possible to synchronize the electric motor with higher precision in a system in which a plurality of electric motors are simultaneously controlled at high speed, for example, a steel plant such as a rolling system or a paper valve manufacturing plant, Thereby improving the product quality and yield.

Also, in designing the application, it is not necessary to consider the position of the programmable controller 120 and the arrangement of the controlled devices 130, so that it is possible to create an executable program with high portability and versatility.

In addition, it is also possible to store a computer such as a program that makes the computer function as a control system 100, a master programmable controller, a slave programmable controller, a computer-readable flexible disk, a magneto-optical disk, a ROM, a CD, Media is also provided. Here, the program refers to data processing means described in any language or description (description) method.

While the preferred embodiments of the present invention have been described with reference to the accompanying drawings, it is needless to say that the present invention is not limited to these embodiments. It will be apparent to those skilled in the art that various changes and modifications can be made in the scope of the appended claims and that they obviously fall within the technical scope of the present invention.

Each step of the control method of the present invention does not necessarily need to be processed in time series in the order described in the flowchart, but may include processing in parallel or by a subroutine.

[Industrial Availability]

The present invention can be used for a control system, a master programmable controller, a slave programmable controller, and a control method in which a plurality of programmable controllers each controlling a controlled device are connected to communicate with each other.

100 ... Control system
110 ... Management device
120 ... Programmable controller
122 ... CPU module
122a ... Master CPU module
122b ... Slave CPU module
130 ... Controlled device
154 ... Communication section
158 ... The reference-
160 ... CPU
166 ... Common memory
180 ... Delay time measuring section
182 ... Sync frame sender
184 ... Delay time receiver
186 ... The synchronous-
188 ... Application execution section
190 ... The data update unit
192 ... Data transmission unit

Claims (17)

A control system including a plurality of control units each of which is a combination of a controlled device (device) and a programmable controller that controls the controlled device on the basis of the program,
The programmable controller includes:
A communication unit for establishing communication with another programmable controller and the controlled device; And
And a common memory for sharing data with another programmable controller through the communication unit,
The programmable controller includes: a master programmable controller functioning as a master; And a slave programmable controller functioning as a slave,
The master programmable controller includes:
A transmission delay time request frame for measuring a transmission delay time between the master programmable controller and the slave programmable controller to the slave programmable controller and receiving a reception completion frame which is a response to the transmission delay time request frame, The transmission delay time frame is calculated from a difference between a time when the transmission delay time request frame was transmitted and a time when the reception completion time frame was received and a transmission delay time notification frame including the transmission delay time, And a delay time measuring section for transmitting the delay time to the programmable controller,
The slave programmable controller includes:
And a transmission delay time notification frame generation unit configured to generate a transmission delay time frame based on the transmission delay time frame and to transmit the transmission delay time frame to the master programmable controller, A time receiver; And
And a synchronization correcting unit synchronizing (synchronizing) the slave programmable controller to the master programmable controller based on the transmission delay time.
Control system. The method according to claim 1,
The programmable controller includes:
And a data updating unit that updates the common memory of the programmable controller of its own with the data generated in the programmable controller and updates the common memory of the other programmable controller. 3. The method according to claim 1 or 2,
Further comprising a management device for controlling the programmable controller,
The programmable controller includes:
And a data transmission unit for transmitting the data to the management apparatus. 4. The method according to any one of claims 1 to 3,
Wherein the data is a detection result or control result in the controlled device, and the programmable controller can be referred to through the common memory. 5. The method according to any one of claims 1 to 4,
The programmable controller includes:
A reference signal generation unit for generating a reference signal by reaching a count value at a preset reference value; And
And an application execution unit that executes the execution program in accordance with the reference signal,
Wherein the synchronization correcting unit synchronizes the slave programmable controller with the master programmable controller by adjusting a generation timing of the reference signal of the reference signal generator only by the transmission delay time. 6. The method of claim 5,
Wherein the master programmable controller further comprises a synchronization frame transmitter for transmitting a synchronization frame to the slave programmable controller,
Wherein the synchronization correcting unit comprises:
Acquiring a count value of the reference signal generator when the synchronization frame is received, calculating a correction amount which is a difference between the transmission delay time and the count value, deriving a correction reference value by subtracting the correction amount from the reference value, And sets the correction reference value to the reference signal generation unit temporarily as a new reference value. The method according to claim 5 or 6,
Wherein the reference value can be set from a management apparatus that controls the programmable controller. 8. The method according to any one of claims 1 to 7,
Wherein the slave programmable controller includes a CPU for executing an operation in the slave programmable controller,
Wherein the reference signal generator is a counter accessible only by the CPU. A master programmable controller that controls a controlled device based on a program and functions as a master,
A slave programmable controller functioning as a slave and a communication unit establishing communication with the controlled device;
A common memory for sharing data with the slave programmable controller through the communication unit; And
A transmission delay time request frame for measuring a transmission delay time between the master programmable controller and the slave programmable controller to the slave programmable controller and receiving a reception completion frame which is a response to the transmission delay time request frame, Wherein the transmission delay time notification frame is calculated from the difference between the time when the transmission delay time request frame was transmitted and the time when the reception completion time frame was received, A delay time measuring unit for transmitting the delay time to the controller;
A master programmable controller. A slave programmable controller that controls a controlled device based on a program and functions as a slave,
Another programmable controller including a master programmable controller functioning as a master and a communication unit establishing communication with the controlled device;
A common memory for sharing data with another programmable controller through the communication unit;
A reception completion frame which is a response to the transmission delay time request frame to the master programmable controller when receiving a transmission delay time request frame for measuring a transmission delay time between the master programmable controller and the slave programmable controller, A delay time receiving unit for obtaining the transmission delay time included in the transmission delay time notification frame upon receiving the transmission delay time notification frame including the transmission delay time; And
A synchronization correcting unit for synchronizing the slave programmable controller with the master programmable controller based on the transmission delay time;
A slave programmable controller. A control method for controlling a plurality of control units, each of which is a combination of a controlled device and a programmable controller that controls the controlled device based on a program,
The programmable controller includes:
Establish communication with another programmable controller and the controlled device,
Share data with other programmable controllers and common memory,
Among the programmable controllers, a master programmable controller functioning as a master,
A transmission delay time request frame for measuring a transmission delay time between the master programmable controller and a slave programmable controller functioning as a slave to the slave programmable controller,
The slave programmable controller includes:
And when receiving the transmission delay time request frame, transmits a reception completion frame, which is a response to the transmission delay time request frame, to the master programmable controller,
The master programmable controller includes:
A transmission delay time calculating unit that calculates a transmission delay time from a difference between a time when the transmission delay time request frame was transmitted and a time when the reception completion time frame was received, Transmits a delay time notification frame to the slave programmable controller,
The slave programmable controller includes:
When receiving the transmission delay time notification frame, acquires the transmission delay time included in the transmission delay time notification frame,
And synchronizing the slave programmable controller with the master programmable controller based on the transmission delay time,
Control method. 12. The method of claim 11,
The programmable controller includes:
And updates the common memory of the programmable controller of its own with the data generated in the programmable controller, and updates the common memory of the other programmable controller. 13. The method according to claim 11 or 12,
The programmable controller includes:
And transmits data to a management apparatus that controls the programmable controller. 14. The method according to any one of claims 11 to 13,
Wherein the data is a detection result or a control result in the controlled device, and the programmable controller can be referred to through the common memory. 15. The method according to any one of claims 11 to 14,
The programmable controller includes:
A reference signal is generated by reaching a count value at a preset reference value,
Executes an execution program in accordance with the reference signal,
And synchronizing the slave programmable controller with the master programmable controller by adjusting the generation timing of the reference signal by the transmission delay time only. 16. The method of claim 15,
Wherein the master programmable controller transmits a synchronization frame to the slave programmable controller,
In the slave programmable controller,
Acquiring a count value of the reference signal generator when the synchronization frame is received, calculating a correction amount which is a difference between the transmission delay time and the count value, deriving a correction reference value by subtracting the correction amount from the reference value, And the correction reference value is set as a new reference value. 17. The method according to claim 15 or 16,
Wherein the reference value can be set from a management apparatus that controls the programmable controller.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180105562A (en) * 2017-03-15 2018-09-28 오므론 가부시키가이샤 Measurement system, control apparatus, measurement method
KR20210064039A (en) * 2019-11-25 2021-06-02 후지 덴키 가부시키가이샤 Programmable controller system and module

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6535459B2 (en) * 2014-12-08 2019-06-26 株式会社キーエンス Programmable logic controller, basic unit, control method and program
WO2017079920A1 (en) * 2015-11-11 2017-05-18 华为技术有限公司 Method and device for synchronization
KR102510900B1 (en) * 2016-02-04 2023-03-15 삼성전자주식회사 Semiconductor device and method for operating semiconductor device
JP6828624B2 (en) * 2017-07-07 2021-02-10 オムロン株式会社 Control system and control method
JP6984199B2 (en) * 2017-07-07 2021-12-17 オムロン株式会社 Control system and control method
EP3832287B1 (en) * 2018-07-31 2023-10-04 Shimadzu Corporation Material testing machine
CN112424717B (en) * 2018-08-30 2024-04-16 株式会社安川电机 Data acquisition system and motor control device of industrial equipment
JP7003951B2 (en) * 2019-03-14 2022-01-21 オムロン株式会社 Control system
WO2022259379A1 (en) * 2021-06-08 2022-12-15 三菱電機株式会社 Programmable logic controller, moving image management device, moving image management system, moving image management method, and program
CN113630203B (en) * 2021-07-22 2023-10-27 广州致远电子股份有限公司 Multi-device triggering synchronization method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2898387B2 (en) * 1990-09-27 1999-05-31 ファナック株式会社 Synchronous signal generator
JP2001075932A (en) * 1999-09-08 2001-03-23 Canon Inc Line controller, line control method and line system
JP2010147806A (en) * 2008-12-18 2010-07-01 Fujitsu Ltd Delay measurement method and communication device
JP2012108696A (en) 2010-11-17 2012-06-07 Hitachi Ltd Programmable controller and communication control method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179221A (en) * 1988-12-28 1990-07-12 Meidensha Corp Sampling synchronous system for loop digital protective relay
JP4337543B2 (en) * 2003-12-22 2009-09-30 三菱電機株式会社 Communication status monitoring device
JP2007226492A (en) * 2006-02-23 2007-09-06 Yaskawa Electric Corp Motion control system
JP5141972B2 (en) * 2007-12-07 2013-02-13 オムロン株式会社 Industrial controller
CN100595707C (en) * 2008-08-29 2010-03-24 华中科技大学 Numerical control machine tool double-shaft synchronization controller

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2898387B2 (en) * 1990-09-27 1999-05-31 ファナック株式会社 Synchronous signal generator
JP2001075932A (en) * 1999-09-08 2001-03-23 Canon Inc Line controller, line control method and line system
JP2010147806A (en) * 2008-12-18 2010-07-01 Fujitsu Ltd Delay measurement method and communication device
JP2012108696A (en) 2010-11-17 2012-06-07 Hitachi Ltd Programmable controller and communication control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180105562A (en) * 2017-03-15 2018-09-28 오므론 가부시키가이샤 Measurement system, control apparatus, measurement method
KR20210064039A (en) * 2019-11-25 2021-06-02 후지 덴키 가부시키가이샤 Programmable controller system and module

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