KR20150049506A - Mask pattern for hole patterning and method for fabricating semiconductor device using the same - Google Patents

Mask pattern for hole patterning and method for fabricating semiconductor device using the same Download PDF

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KR20150049506A
KR20150049506A KR1020130130170A KR20130130170A KR20150049506A KR 20150049506 A KR20150049506 A KR 20150049506A KR 1020130130170 A KR1020130130170 A KR 1020130130170A KR 20130130170 A KR20130130170 A KR 20130130170A KR 20150049506 A KR20150049506 A KR 20150049506A
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South Korea
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pattern
hard mask
sacrificial
layer
forming
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KR1020130130170A
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Korean (ko)
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강춘수
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에스케이하이닉스 주식회사
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Priority to KR1020130130170A priority Critical patent/KR20150049506A/en
Publication of KR20150049506A publication Critical patent/KR20150049506A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/3007—Imagewise removal using liquid means combined with electrical means, e.g. force fields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method of manufacturing a semiconductor device capable of preventing patterning defects in a cell matrix edge region, the method including forming an etch target layer on a substrate including a first region and a second region; Forming a first hard mask layer on the etch target layer; Forming a first mask structure on the first hard mask layer, the first mask structure including a second hard mask pattern in the form of a spacer located in the first region and a blocking pattern blocking the second region; Etching the first hardmask layer by the first mask structure to form a plurality of first openings; Blocking the plurality of first openings and second regions to form a second mask structure that intersects the second hard mask pattern; Etching the second hard mask pattern and the first hard mask layer by the second mask structure to form a plurality of second openings; And etching the etching target layer by a first hard mask layer having the first openings and the second openings to form a plurality of hole patterns.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a mask pattern for hole patterning and a method for manufacturing a semiconductor device using the mask pattern.

The present invention relates to a semiconductor device manufacturing method, and more particularly, to a mask pattern for hole patterning and a method of manufacturing a semiconductor device using the same.

It is necessary to form a fine line width pattern as the degree of integration of the semiconductor device increases. Spacer patterning technology (SPT) and double pattering technology have been studied due to resolution limitations of exposure equipment.

An embodiment of the present invention provides a method of manufacturing a semiconductor device capable of preventing hole patterning defects in a cell matrix edge region.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first hard mask layer on a layer to be etched; Forming a second hard mask pattern on the first hard mask layer; Etching the first hard mask layer by the second hard mask pattern to form a first open portion; Etching the second hard mask pattern and a first hard mask layer thereunder to form a second open portion spaced apart from the first open portion; And etching the etching target layer with the first hard mask pattern having the first open portion and the second open portion as an etching barrier to form a plurality of patterns.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: forming a first hard mask layer on a layer to be etched; Forming a second hard mask pattern including a first space on the first hard mask layer; Forming a first sacrificial pattern on the second hard mask pattern, the first sacrificial pattern including a second space intersecting the first space; Etching the first hardmask layer exposed by the intersection of the first space and the second space to form a first open portion; Forming a second sacrificial pattern to fill the first opening and the second space; Forming a third sacrificial pattern on a sidewall of the second sacrificial pattern; Etching the second hard mask pattern and the first hard mask layer by the third sacrificial pattern, the second sacrificial pattern, and the first sacrificial pattern to form a second open portion; And etching the etch target layer using a first hard mask layer having the first open portion and the second open portion.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming an etch target layer on a substrate including a first region and a second region; Forming a first hard mask layer on the etch target layer; Forming a first mask structure on the first hard mask layer, the first mask structure including a second hard mask pattern in the form of a spacer located in the first region and a blocking pattern blocking the second region; Etching the first hardmask layer by the first mask structure to form a plurality of first openings; Blocking the plurality of first openings and second regions to form a second mask structure that intersects the second hard mask pattern; Etching the second hard mask pattern and the first hard mask layer by the second mask structure to form a plurality of second openings; And etching the etching target layer by a first hard mask layer having the first openings and the second openings to form a plurality of hole patterns.

The present technique can improve the hole patterning defects of the cell matrix edge region by applying the patterning process in the zigzag direction.

In addition, the technique can adjust the line width of the hole without additional mask.

Therefore, the present technology makes it possible to form a high-density capacitor without hole patterning of 30 nm or less.

1A to 1M are plan views showing a method of manufacturing a semiconductor device according to the first embodiment.
2A to 2M are sectional views taken along the line A-A 'in Figs. 1A to 1M.
3A to 3M are sectional views taken along the line B-B 'in FIGS. 1A to 1M.
4A to 4M are cross-sectional views taken along line C-C 'in Figs. 1A to 1M.
5A and 5B are views showing a method of manufacturing a semiconductor device according to the second embodiment.
6A to 6M are plan views illustrating a method of manufacturing the semiconductor device according to the second embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1A to 1M are plan views showing a method of manufacturing a semiconductor device according to the first embodiment. 2A to 2M are sectional views taken along the line A-A 'in Figs. 1A to 1M. 3A to 3M are sectional views taken along the line B-B 'in FIGS. 1A to 1M. 4A to 4M are cross-sectional views taken along line C-C 'in Figs. 1A to 1M.

An etch target layer 12 is formed on the substrate 11, as shown in FIGS. 1A, 2A, 3A, and 4A. The substrate 11 may comprise a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate. Although not shown, a conductive structure including a conductive layer or a conductive layer may further be formed on the substrate 11. In addition, an impurity region may be formed in the substrate 11. In addition, an insulating layer may be further formed on the substrate 11.

The etch target layer 12 is a material that is etched by a subsequent etch process. The etch target layer 12 may comprise a silicon layer, a metal layer, silicon oxide or silicon nitride. For example, the etch target layer 12 may be formed of phosphor silicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetra ethyl ortho silicate (TEOS) Or high density plasma-chemical vapor deposition (HDP-CVD) oxide. Hereinafter, in the first embodiment, the etching target layer 12 may include silicon oxide.

A first hard mask layer is formed on the etching target layer 12. The first hard mask layer is an etch barrier used when the etching target layer 12 is etched. Thus, the first hard mask layer may be formed of a material having an etch selectivity to the etch target layer 12. [ The first hard mask layer may comprise a single layer or a multilayer structure of two or more layers. For example, the first hard mask layer may be formed of a polysilicon layer, silicon oxide or silicon nitride to form a single layer, or may be laminated to form a multilayer. In the first embodiment, the first hard mask layer is formed by laminating a main first hard mask layer 13A and a sub first hard mask layer 14A . The main first hardmask layer 13A and the sub first hardmask layer 14A comprise different materials with different etch selectivities. In the first embodiment, the main first hardmask layer 13A includes a polysilicon layer, and the sub first hardmask layer 14A may comprise silicon oxide. The main first hardmask layer 13A and the sub first hardmask layer 14A may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

As described above, high aspect ratio etching is possible when the etching target layer 12 is etched by stacking the main first hard mask layer 13A and the sub first hard mask layer 14A.

A first mask pattern 15A is formed on the sub first hard mask layer 14A. The first mask pattern 15A includes a blocking part 15B and a line part 15C. The first mask pattern 15A may be formed by a known photolithography process. The first mask pattern 15A may include a hard mask pattern patterned by a photoresist pattern.

As shown in FIGS. 1B, 2B, 3B and 4B, a second hard mask pattern 16 is formed on the sidewalls of the first mask pattern 15A. The second hard mask pattern 16 has a shape of a spacer surrounding the side wall of the first mask pattern 15A. The second hard mask pattern 16 may be formed of a material having an etching selectivity difference from the etching target layer 12. In addition, the second hard mask pattern 16 may include the same material as the main first hard mask layer 13A. Accordingly, the second hard mask pattern 16 may be formed of a material having an etching selectivity difference from the sub first hardmask layer 14A. The second hard mask pattern 16 may comprise a polysilicon layer. For example, after the polysilicon layer is deposited on the first mask pattern 15A, the second hard mask pattern 16 may be formed by an etch-back process of the polysilicon layer. The etch back process of the polysilicon layer may be performed by an etch gas having an etch selectivity to the sub first hardmask layer 14A. The width of the second hard mask pattern 16 can be adjusted.

As described above, the series of processes for forming the first mask pattern 15 and the second hard mask pattern 16 is referred to as SPT (Spacer Patterning Technology) process.

As shown in Figs. 1C, 2C, 3C and 4C, a part of the first mask pattern 15A is removed. Here, a part of the first mask pattern 15A includes the line part 15C. Thus, by removing the line part 15C, the surface of the sub first hard mask layer 14A between the second hard mask patterns 16 is exposed. A plurality of first spaces 16A defined by the second hard mask pattern 16 are formed. The line width of the second hard mask pattern 16 and the width of the first space 16A may be the same. By adjusting the width of the second hard mask pattern 16, the width of the first space 16A can be varied. The residual first mask pattern 15A becomes the blocking pattern 15. [

A first sacrificial layer 17A is formed on the blocking pattern 15 and the second hard mask pattern 16, as shown in Figs. 1D, 2D, 3D and 4D. The first sacrificial layer 17A is formed on the front surface so as to cover the first space 16A. The first sacrificial layer 17A includes a carbon-containing material. The first sacrificial layer 17A may include an amorphous carbon layer. The first sacrificial layer 17A can be formed by a spin-on coating method. The amorphous carbon layer formed by the spin-on coating method is abbreviated as a 'Spin On Carbon layer (SOC)'.

A second mask pattern 18 is formed on the first sacrificial layer 17A, as shown in Figs. 1E, 2E, 3E and 4E. The second mask pattern 18 extends in a direction intersecting with the second hard mask pattern 16. The second mask pattern 18 extends in a direction intersecting the line part 15C of the first mask pattern 15A in Fig. 1A. The second mask pattern 18 may be formed of a plurality of lines. Therefore, a plurality of second spaces 18A are formed between the second mask patterns 18. The width of the second space 18A can be adjusted. The size of the subsequent open portion can be adjusted by adjusting the width of the first space 16A and the width of the second space 18A. For example, by adjusting the width of the first space 16A, the X-axis length of the open portion can be adjusted. In addition, the Y-axis length of the open portion can be adjusted by adjusting the width of the second space 18A. The step of forming the second mask pattern 18 is abbreviated as a single mask process.

A first sacrificial pattern 17B is formed. The first sacrificial pattern 17B is formed by etching the first sacrificial layer 17A. The first sacrificial layer 17A is etched using the second mask pattern 18 as an etching barrier. The sub first hard mask layer 14A and the second hard mask pattern 16 under the first sacrificial layer 17A are exposed by etching the first sacrificial layer 17A. The first sacrificial pattern 17B becomes a pattern including the third space 19 which is the same as the second space 18A.

As shown in Figs. 1F, 2F, 3F and 4F, a first open portion 20 is formed. The first open portion 20 is formed by etching the sub first hardmask layer 14A. For example, the sub first hard mask layer 14A is etched using the first sacrificial pattern 17B and the second hard mask pattern 16 as an etching barrier. Thus, the first open portion 20 is formed in the sub first hard mask pattern 14. The first open portion 20 has a hole shape. The first open portion 20 is formed by etching the first hard mask layer 14A exposed by crossing the first sacrificial pattern 17B and the second hard mask pattern 16. [ The second mask pattern 18 can be exhausted and removed.

As described above, the first open portion 20 is formed by a series of processes using a combination of the first mask pattern 15A and the second mask pattern 18.

As shown in Figs. 1G, 2G, 3G and 4G, a second sacrificial pattern 21 is formed. The second sacrificial pattern 21 scribes the first open portion 20 and the third space 19. The second sacrificial pattern 21 includes silicon nitride. The second sacrificial pattern 21 is subsequently planarized to expose the upper surface of the first sacrificial pattern 17B. Therefore, the second sacrificial pattern 21 becomes a line pattern that fills the first open portion 20 and the third space 19. The second sacrificial pattern 21 extends in a direction intersecting with the second hard mask pattern 16.

The first sacrificial pattern 17B is recessed (see reference numeral 22), as shown in Figs. 1H, 2H, 3H and 4H. Thereby, a recessed first sacrificial pattern 17C that protrudes the upper portion of the second sacrificial pattern 21 is formed. The first sacrificial pattern 17B may be recessed by an etch-back process.

A third sacrificial pattern 23 is formed. The third sacrificial pattern 23 is formed on the sidewall of the projection of the second sacrificial pattern 21. The third sacrificial pattern 23 includes silicon oxide. For example, after the silicon oxide is formed on the entire surface including the second sacrificial pattern 21, an etch-back process is performed. As a result, a silicon oxide spacer is formed on the side wall of the protrusion of the second sacrificial pattern 21. The silicon oxide spacer becomes the third sacrificial pattern 23.

As described above, the second sacrificial pattern 21 and the third sacrificial pattern 23 become the sacrificial mask layer 24. The sacrificial mask layer 24 becomes an etch barrier for etching the second hard mask pattern 16 and the second hard mask layer 14.

The sacrificial mask layer 24 may extend in a direction that intersects the second hard mask pattern 16.

As shown in Figs. 1I, 2I, 3I and 4I, a second open portion 25 is formed. The second open portion 25 is formed by etching the sub first hard mask pattern 14. For example, the recessed first sacrificial pattern 17C is partially etched using the second sacrificial pattern 21 and the third sacrificial pattern 23 as an etching barrier. At this time, the recessed first sacrificial pattern 17C is etched until the surfaces of the second hard mask pattern 16 and the blocking pattern 15 are exposed. Thus, a first gap pattern 17 of gapfilled remains in the space of the second hard mask pattern 16. The gap field first sacrificial pattern 17, the second sacrificial pattern 21 and the third sacrificial pattern 23 become the sacrificial mask layer 24. A part of the surface of the second hard mask pattern 16 is exposed by the mutual intersection of the gap field first sacrificial pattern 17, the second sacrificial pattern 21 and the third sacrificial pattern 23. [

Subsequently, the second hard mask pattern 16 and the sub first hard mask patterns 14 (14) are formed with the gap field first sacrificial pattern 17, the second sacrificial pattern 21 and the third sacrificial pattern 23 as an etching barrier, ) Are sequentially etched. Thus, the second open portion 25 is formed.

The second open portion 25 is formed by a series of processes using the sacrificial mask layer 24. [

1J, 2J, 3J and 4J, the sacrificial mask layer 24 is removed. Therefore, the sub first hard mask pattern 14, the second hard mask pattern 16, and the blocking pattern 15 remain on the main first hard mask layer 13A.

As described above, the plurality of first openings 20 and the second openings 25 are formed in the sub first hard mask pattern 14. The first open portion 20 and the second open portion 25 are spaced apart from each other by a sufficient distance. The first open portion 20 and the second open portion 25 are formed with a zigzag array. The second open portion 25 is spaced apart from the first open portion 20 in the zigzag direction by a sufficient distance. The first open portion 20 and the second open portion 25 are spaced apart from each other at a predetermined interval. The sizes of the first open portion 20 and the second open portion 25 are the same. The first open portion 20 and the second open portion 25 may each be a circle type opening. The shapes of the first open portion 20 and the second open portion 25 may be variously modified, but they are formed in the same size.

As shown in Figs. 1K, 2K, 3K and 4K, a plurality of open portions 26 are formed. A plurality of open portions 26 are formed by etching the main first hard mask layer 13A. The plurality of open portions 26 are the same as those of the first open portion 20 and the second open portion 25. The plurality of open portions 26 form a zigzag array. The main first hardmask layer 13A is etched with the sub first hardmask pattern 14 as an etch barrier. At this time, the second hard mask pattern 16 may be consumed and removed.

A plurality of open portions 26 are formed in the main first hard mask pattern 13. Each of the open portions 26 is spaced apart at regular intervals. The size of the open portion 26 is the same. The open portion 26 can be a circular opening.

As shown in Figs. 11, 21, 31, and 41, the blocking pattern 15 can be removed. Therefore, the main first hard mask pattern 13 having a plurality of open portions 26 remains.

The etching target layer 12 is etched. Accordingly, a plurality of patterns 27 are formed on the etching target layer 12. The etching target layer 12 is etched using the main first hard mask pattern 13 as an etching barrier. The plurality of patterns 27 have the same shape and arrangement as the plurality of open portions 26. [ Thus, the plurality of patterns 27 form a zigzag array. In the etching process for forming the pattern 27, the sub first hard mask pattern 14 may be consumed and removed.

The main first hard mask pattern 13 may be removed, as shown in Figs. 1M, 2M, 3M and 4M.

According to the first embodiment, the plurality of patterns 27 are formed with uniform spacing and uniform size. Further, it is possible to form a plurality of patterns 27 of a uniform zigzag array in which no parasitic pattern is formed. The pattern 27 may be in the form of an opening including a hole, a line, or a polygon. For example, the pattern 27 may be in the form of a contact hole, a via hole, a trench or a recess.

According to the first embodiment, it is possible to uniformly form the pattern 27 of the zigzag array by using a plurality of hard mask layers and sacrificial mask layers with different etching selection ratios.

 Further, according to the first embodiment, by sequentially applying the SPT process and the single mask process, a mask layout for forming a plurality of patterns can be formed.

5A and 5B are views for explaining a method of manufacturing the semiconductor device according to the second embodiment. For example, a method of manufacturing a capacitor of a DRAM.

As shown in Fig. 5A, the semiconductor substrate 41 includes a plurality of regions. The plurality of regions include a cell matrix region 42 and a peripheral circuit region 43. The cell matrix region 42 includes a cell matrix edge region 44.

A mold layer (45) is formed on the semiconductor substrate (41). The mold layer 45 is formed with a plurality of hole patterns by a subsequent etching process. The storage node of the capacitor is formed in the hole pattern. The mold layer 45 may comprise silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. For example, the mold layer 45 may be a multi-layer structure comprising a plurality of silicon oxides and a plurality of silicon nitrides. Although not shown, transistors, word lines, bit lines, storage node contact plugs, and the like can be formed before the mold layer 45 is formed. The transistor may comprise a buried gate type transistor or a vertical channel transistor. The word line can also serve as the gate electrode of the transistor. The bit line may include a stacked bit line or a buried bit line. The transistor and the bit line can be selectively formed. For example, a vertical channel transistor may be formed after the buried bit line is formed. In addition, a stacked bit line can be formed after the buried gate type transistor is formed. The storage node contact plug may be connected to any one of the source region and the drain region of the transistor. The mold layer 45 may be formed after the storage node contact plug is formed.

A main first hard mask pattern 46 is formed on the mold layer 45. The mold layer 45 is etched by the main first hard mask pattern 46 to form a plurality of hole patterns 59.

The main first hard mask pattern 46 corresponds to the main first hard mask pattern 13 of the first embodiment. The main first hard mask pattern 46 has a plurality of open portions. In the plurality of hole patterns 59, a plurality of open portions are transferred. A hole pattern 59 is formed in the cell matrix region 42. The plurality of hole patterns 59 have an array in the zigzag direction. The hole pattern 59 is not formed in the peripheral circuit region 43 and the cell matrix region 44.

As shown in FIG. 5B, the storage node 60 is formed in the plurality of hole patterns 59. The storage node 60 has a pillar shape. In another embodiment, the storage node 60 may have a cylinder shape.

The plurality of hole patterns 59 may be formed by performing the same or similar processes as those of the pattern 27 according to the first embodiment.

In the second embodiment, the plurality of hole patterns 59 may be formed by a combination of the first mask pattern and the second mask pattern. The first mask pattern and the second mask pattern may be modified and arranged in a manner different from the first embodiment.

Hereinafter, a manufacturing method for forming a plurality of hole patterns 59 will be described. The manufacturing method according to the second embodiment can be formed by the same or similar process as the first embodiment.

6A is a plan view for explaining the method of manufacturing the semiconductor device according to the second embodiment.

A main first hard mask layer (not shown) and a sub first hard mask layer 47A are laminated on the mold layer 45, as shown in Fig. 6A. The main first hardmask layer comprises a polysilicon layer and the sub first hardmask layer 47A may comprise silicon oxide.

A first mask pattern 48A is formed on the sub first hardmask layer 47A. The first mask pattern 48A includes a blocking part 48B and a line part 48C. The first mask pattern 48A may be formed by a known photolithography process. The first mask pattern 48A may comprise a hard mask pattern patterned by a photoresist pattern. The blocking part 48B blocks the peripheral circuit area 43.

As shown in FIG. 6B, a second hard mask pattern 49 is formed on the sidewalls of the first mask pattern 48A. The third hard mask pattern 49 has a spacer shape surrounding the side wall of the first mask pattern 48A. The third hard mask pattern 49 may comprise a polysilicon layer. For example, after depositing a polysilicon layer on the first mask pattern 48A, a second hard mask pattern 49 may be formed by an etch-back process of the polysilicon layer.

As described above, the series of processes for forming the first mask pattern 48 and the second hard mask pattern 49 is referred to as SPT process.

As shown in Fig. 6C, a part of the first mask pattern 48A is removed. Here, a part of the first mask pattern 48A includes the line part 48C. Thus, by removing the line part 48C, the surface of the sub first hard mask layer 47A between the second hard mask patterns 49 is exposed. A plurality of first spaces 49A defined by the second hard mask pattern 49 are formed. The line width of the second hard mask pattern 49 and the width of the first space 49A may be the same. By adjusting the width of the second hard mask pattern 49, the width of the first space 49A can be varied. The residual first mask pattern 48A becomes the blocking pattern 48. [ The blocking pattern 48 covers the upper portion of the peripheral circuit region 43. The cell mattress edge area 44 is covered by the outermost second hard mask pattern 49. [

A first sacrificial layer 50A is formed on the blocking pattern 48 and the second hard mask pattern 49, as shown in Fig. 6D. The first sacrificial layer 50A is formed on the front surface so as to cover the first space 49A. The first sacrificial layer 50A includes a carbon-containing material. The first sacrificial layer 50A may include an amorphous carbon layer. The first sacrificial layer 50A includes a spin-on-carbon layer (SOC).

As shown in FIG. 6E, a second mask pattern 51 is formed on the first sacrificial layer 50A. The second mask pattern 51 extends in a direction intersecting the second hard mask pattern 49. The second mask pattern 51 extends in a direction crossing the first mask pattern 48A. The second mask pattern 51 may be formed of a plurality of line patterns. Therefore, a plurality of second spaces 52 are formed between the second mask patterns 51. The width of the second space 52 can be adjusted. The size of the subsequent open portion can be adjusted by adjusting the width of the first space 49A and the width of the second space 52. For example, the X-axis length of the open portion can be adjusted by adjusting the width of the first space 49A. In addition, by adjusting the width of the second space 52, the Y-axis length of the open portion can be adjusted. The step of forming the second mask pattern 51 is abbreviated as a single mask process.

Next, first sacrificial patterns 50B and 50C are formed. The first sacrificial patterns 50B and 50C are formed by etching the first sacrificial layer 50A. The first sacrificial layer 50A is partially etched using the second mask pattern 51 as an etching barrier. The sub first hard mask layer 47A and the second hard mask pattern 49 are exposed by partially etching the first sacrificial layer 50A. That is, partial etching is performed until the sub first hard mask layer 47A and the second hard mask pattern 49 are exposed. Therefore, a line-shaped first sacrificial pattern (50C in Fig. 6F) remains below the second mask pattern 51, and a blocking first sacrificial pattern 50B remains in the peripheral circuit area.

As shown in Fig. 6F, a first open portion 53 is formed. The first open portion 53 is formed by etching the sub first hard mask layer 47A. For example, the sub first hard mask layer 47A is etched using the first sacrificial patterns 50B and 50C and the second hard mask pattern 49 as an etching barrier. Thus, the sub first hard mask pattern 47B remains below the line-shaped first sacrificial pattern 50C and the first open portion 53 is formed in the sub first hard mask pattern 47B. The first open portion 53 has a hole shape. The first open portion 53 is formed by etching the sub first hard mask layer 47A exposed by crossing the line-shaped first sacrificial pattern 50C and the second hard mask layer 49. [

The second mask pattern 51 is removed.

As shown in Fig. 6G, a second sacrificial pattern 54 is formed. The second sacrificial pattern 54 scribes the first open portion 53 and the second space 52. The second sacrificial pattern 54 comprises silicon nitride. The second sacrificial pattern 54 is subsequently planarized to expose the upper surface of the line-shaped first sacrificial pattern 50C. Therefore, the second sacrificial pattern 54 becomes a line pattern that fills the first open portion 53 and the second space 52. The second sacrificial pattern 54 extends in a direction intersecting with the second hard mask pattern 49. The second sacrificial pattern 54 covers the peripheral circuit region 43 and the cell matrix edge region 44.

As shown in Fig. 6H, the line-shaped first sacrificial pattern 50C is recessed. Thereby, a recessed first sacrificial pattern 50D is formed which projects the upper portion of the second sacrificial pattern 54. [ The line-shaped first sacrificial pattern 50C can be recessed by an etch-back process.

A third sacrificial pattern 55 is formed. The third sacrificial pattern 55 is formed on the side wall of the protrusion of the second sacrificial pattern 54. The third sacrificial pattern 55 includes silicon oxide. For example, after the silicon oxide is formed on the entire surface including the second sacrificial pattern 54, an etch-back process is performed. As a result, a silicon oxide spacer is formed on the sidewall of the protrusion of the second sacrificial pattern 54. The silicon oxide spacer becomes the third sacrificial pattern 55. The third sacrificial pattern 55 is formed in the cell region 42 and covers a portion of the peripheral circuit region 43 and the cell matrix edge region 44.

As described above, the second sacrificial pattern 54 and the third sacrificial pattern 55 become an etching barrier for etching the second hard mask pattern 49 and the sub first hard mask pattern 47B.

The second sacrificial pattern 54 and the third sacrificial pattern 55 may extend in a direction crossing the second hard mask layer 49.

As shown in Fig. 6I, a second open portion 57 is formed. The second open portion 57 is formed by etching the sub first hard mask pattern 47A. For example, the recessed first sacrificial pattern 50D is partially etched using the second sacrificial pattern 54 and the third sacrificial pattern 55 as an etching barrier. At this time, the recessed first sacrificial pattern 50D is etched until the surface of the second hard mask pattern 49 is exposed. Thus, the first sacrificial pattern 50 of the gap field remains in the first space of the second hard mask pattern 49.

The gap field first sacrificial pattern 50, the second sacrificial pattern 54 and the third sacrificial pattern 55 become the sacrificial mask pattern 56. [ A part of the surface of the second hard mask pattern 49 is exposed by the mutual intersection of the gap field first sacrificial pattern 50, the second sacrificial pattern 54, and the third sacrificial pattern 55.

Subsequently, the second hard mask pattern 49 and the sub first hard mask pattern 47 (second hard mask pattern) are etched using the gap field first sacrificial pattern 50, the second sacrificial pattern 54 and the third sacrificial pattern 55 as an etching barrier. ) Are sequentially etched. Thus, the second open portion 57 is formed. The second open portion 57 is formed in the cell matrix region 42. The second open portion 57 is not formed in the cell matrix edge region 44 and the peripheral circuit region 43. [ This is because the second sacrificial pattern 54 and the third sacrificial pattern 55 cover the cell matrix edge region 44 and the peripheral circuit region 43.

As shown in FIG. 6J, the sacrificial mask pattern 56 is removed. Therefore, the sub first hard mask pattern 47, the second hard mask pattern 49, and the blocking pattern 48 remain on the main first hard mask layer.

As described above, the plurality of first openings 53 and the second openings 57 are formed in the sub first hard mask pattern 47. The first open portion 53 and the second open portion 57 are spaced apart from each other by a sufficient distance. The first open portion 53 and the second open portion 57 are formed with a zigzag array. The second open portion 57 is spaced apart from the first open portion 53 by a sufficient distance in the zigzag direction. The first open portion 53 and the second open portion 57 are spaced apart from each other at a constant interval. The sizes of the first open portion 53 and the second open portion 57 are the same. The first open portion 53 and the second open portion 57 may each be a circle type opening. The shapes of the first open portion 53 and the second open portion 57 may be variously modified, but they are formed in the same size.

As shown in Fig. 6K, a plurality of open portions 58 are formed. A plurality of open portions 58 are formed by etching the main first hard mask layer. The plurality of open portions 58 are the same as those of the first open portion 53 and the second open portion 57. The plurality of open portions 58 form a zigzag array. The main first hardmask layer is etched with the sub first hard mask pattern 47 and the blocking pattern 48 as an etch barrier. At this time, the second hard mask pattern 49 may be consumed and removed.

In each of the plurality of open portions 58, each of the open portions 58 is spaced apart at regular intervals. The size of the open portion 58 is the same. The open portion 58 can be a circular opening.

As shown in FIG. 61, the blocking pattern 48 may be removed. Therefore, the main first hard mask pattern 46 having a plurality of open portions 58 remains. The open portion 58 is formed with a zigzag array in the cell matrix region 42. The open portion 58 is not formed in the peripheral circuit region 43 and the cell matrix edge region 44.

As shown in FIG. 6M, the mold layer 45 is etched. As a result, a plurality of hole patterns 59 are formed in the mold 45. The mold layer 45 is etched with the first hard mask pattern 46 as an etching barrier. The plurality of hole patterns (59) have the same shape and arrangement as the plurality of open portions (58). Thus, the plurality of hole patterns 59 have a zigzag array. The hole pattern 59 is formed with a zigzag array in the cell matrix region 42. The hole pattern 59 is not formed in the peripheral circuit region 43 and the cell matrix edge region 44.

According to the second embodiment, the plurality of hole patterns 59 are formed with uniform spacing and uniform size. In addition, the hole pattern 59 is not formed in the peripheral circuit region 43 and the cell matrix edge region 44.

According to the second embodiment, it is possible to uniformly form the hole patterns 59 of the zigzag array by using a plurality of hard mask layers and sacrifice mask layers having different etch selectivity ratios.

 According to the second embodiment, parasitic hole patterns are not formed in the peripheral circuit region 43 and the cell matrix edge region 44 by sequentially applying the SPT process and the single mask process, and only the cell matrix region 42 A mask layout for forming a plurality of hole patterns 59 can be formed.

As a comparative example of these embodiments, there is a LELE method, a double-quadrangular linear mesh SPT method, or a composite mesh SPT method.

A plurality of hole patterns are formed by the LELE (Litho-Etch-Litho-Etch) method. However, in the LELE method, since the hard mask pattern is formed by the SPT process, it is difficult to control the bar CD between the CD pattern and the hole pattern of the hole pattern. Particularly, a parasitic hole pattern must be formed in the cell matrix edge region.

As a double quadrilateral linear mesh SPT method, a hard mask pattern having a mesh-like open portion is formed by patterning twice in the diagonal direction. However, there is a problem that the double-quadrangular linear mesh SPT method also forms a parasitic hole pattern in the cell matrix edge region.

The composite mesh SPT pattern is patterned once in the horizontal direction and twice in the oblique direction to form a hard mask pattern having a mesh-like open portion. However, in the composite mesh SPT method, a parasitic hole pattern is formed in the cell matrix edge region. In addition, the CD of the parasitic hole pattern is larger than the hole pattern formed in the cell mattress area.

As a result, these embodiments prevent the parasitic hole pattern from being formed in the cell matrix edge region. Further, CD control of the hole pattern formed in the cell matrix region is easy.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

41: substrate 42: cell matrix region
43: peripheral circuit area 44: cell matrix edge area
45: mold layer 46: main first hard mask pattern
47: Sub first hard mask pattern 48: Blocking pattern
48A: first mask pattern 49: second hard mask pattern
51: second mask pattern 53: first open portion
56: sacrificial mask pattern 57: second open portion
58: open part 59: hole pattern
60: storage node

Claims (22)

Forming a first hard mask layer on the etch target layer;
Forming a second hard mask pattern on the first hard mask layer;
Etching the first hard mask layer by the second hard mask pattern to form a first open portion;
Etching the second hard mask pattern and a first hard mask layer thereunder to form a second open portion spaced apart from the first open portion; And
Forming a plurality of patterns by etching the object layer with the first hard mask pattern having the first open portion and the second open portion as an etching barrier
≪ / RTI >
The method according to claim 1,
Wherein the first open portion and the second open portion are spaced apart from each other in the zigzag direction.
The method according to claim 1,
Wherein forming the second hard mask pattern comprises:
Forming a first mask pattern on the first hard mask layer;
Forming a second hard mask layer on the entire surface including the first mask pattern; And
Forming a second hard mask pattern having a spacer shape on a sidewall of the first mask pattern by etching the second hard mask layer
≪ / RTI >
The method according to claim 1,
Wherein forming the first openings comprises:
Forming a first sacrificial layer on the second hard mask pattern;
Forming a second mask pattern in a direction crossing the second hard mask pattern on the first sacrificial layer;
Etching the first sacrificial layer by the second mask pattern to form a first sacrificial pattern; And
Etching the first hard mask layer by the first sacrificial pattern and the second hard mask pattern to form the first open portion
≪ / RTI >
5. The method of claim 4,
Wherein forming the second open portion comprises:
Forming a second sacrificial pattern between the first sacrificial patterns and filling the first openings;
Recessing the first sacrificial pattern to protrude the upper portion of the second sacrificial pattern;
Forming a third sacrificial pattern on a sidewall of the projection of the second sacrificial pattern;
Partially etching the first sacrificial pattern to expose the second hard mask pattern by the third sacrificial pattern and the second sacrificial pattern;
Etching the second hard mask pattern and the first hard mask layer by the first sacrificial pattern, the second sacrificial pattern, and the third sacrificial pattern; And
Removing the first sacrificial pattern, the second sacrificial pattern, and the third sacrificial pattern
≪ / RTI >
6. The method of claim 5,
Wherein the first sacrificial pattern comprises a carbon containing material, the second sacrificial pattern comprises silicon nitride, and the third sacrificial pattern comprises silicon oxide.
Forming a first hard mask layer on the etch target layer;
Forming a second hard mask pattern including a first space on the first hard mask layer;
Forming a first sacrificial pattern on the second hard mask pattern, the first sacrificial pattern including a second space intersecting the first space;
Etching the first hardmask layer exposed by the intersection of the first space and the second space to form a first open portion;
Forming a second sacrificial pattern to fill the first opening and the second space;
Forming a third sacrificial pattern on a sidewall of the second sacrificial pattern;
Etching the second hard mask pattern and the first hard mask layer by the third sacrificial pattern, the second sacrificial pattern, and the first sacrificial pattern to form a second open portion; And
Etching the etch target layer using a first hard mask layer having the first open portion and the second open portion
≪ / RTI >
8. The method of claim 7,
Wherein forming the second hard mask pattern comprises:
Forming a first mask pattern on the first hard mask layer;
Forming a second hard mask layer on the entire surface including the first mask pattern;
Forming a second hard mask pattern having a spacer shape on a sidewall of the first mask pattern by etching the second hard mask layer; And
Removing the first mask pattern to form the first space
≪ / RTI >
8. The method of claim 7,
Wherein forming the first sacrificial pattern comprises:
Forming a first sacrificial layer on the second hard mask pattern to fill the first space;
Forming a second mask pattern in a direction crossing the second hard mask pattern on the first sacrificial layer; And
Etching the first sacrificial layer by the second mask pattern
≪ / RTI >
8. The method of claim 7,
Wherein the first sacrificial pattern includes a line pattern having a line width larger than the line width of the first space.
8. The method of claim 7,
Wherein the first space and the second space have the same line width.
8. The method of claim 7,
Wherein forming the third sacrificial pattern comprises:
Recessing the first sacrificial pattern; And
Forming a spacer-shaped third sacrificial pattern on the side wall of the projection of the second sacrificial pattern
≪ / RTI >
8. The method of claim 7,
Wherein forming the second open portion comprises:
Partially etching the first sacrificial pattern until the second hard mask pattern is exposed by the third sacrificial pattern and the second sacrificial pattern; And
Etching the second hard mask pattern and the first hard mask layer by the third sacrificial pattern, the second sacrificial pattern, and the first sacrificial pattern,
≪ / RTI >
8. The method of claim 7,
Wherein the first open portion and the second open portion have a zigzag array.
Forming an etching target layer on a substrate including a first region and a second region;
Forming a first hard mask layer on the etch target layer;
Forming a first mask structure on the first hard mask layer, the first mask structure including a second hard mask pattern in the form of a spacer located in the first region and a blocking pattern blocking the second region;
Etching the first hardmask layer by the first mask structure to form a plurality of first openings;
Blocking the plurality of first openings and second regions to form a second mask structure that intersects the second hard mask pattern;
Etching the second hard mask pattern and the first hard mask layer by the second mask structure to form a plurality of second openings; And
Forming a plurality of hole patterns by etching the etch target layer with a first hard mask layer having the first openings and the second openings,
≪ / RTI >
16. The method of claim 15,
Wherein forming the first mask structure comprises:
Forming a first mask pattern on the first hard mask layer, the first mask pattern including a line part partially covering the first area and a blocking part blocking the second area;
Forming the second hard mask pattern on a sidewall of the first mask pattern;
Selectively removing a line part of the first mask pattern to form the blocking pattern;
Forming a first sacrificial layer on the second hard mask pattern and the blocking pattern;
Forming a second mask pattern including a plurality of lines partially covering the first region on the first sacrificial layer; And
Etching the first sacrificial layer by the second mask pattern to form a first sacrificial pattern that intersects the second hard mask pattern
≪ / RTI >
17. The method of claim 16,
Wherein forming the plurality of first openings comprises:
Etching the first hardmask layer exposed by the intersection of the second hard mask pattern and the first sacrificial pattern to form a plurality of first openings
≪ / RTI >
18. The method of claim 17,
Wherein forming the second mask structure comprises:
Forming a second sacrificial pattern filling the plurality of first openings and blocking the second areas;
Recessing the first sacrificial pattern;
Forming a third sacrificial pattern on a sidewall of the second sacrificial pattern
≪ / RTI >
16. The method of claim 15,
Wherein the first region includes a cell matrix region, and the second region includes a peripheral circuit region.
16. The method of claim 15,
Wherein the plurality of first openings and the second openings form an array in a zigzag direction.
16. The method of claim 15,
Wherein the first hardmask layer is formed by laminating a polysilicon layer and silicon oxide, and the second hardmask pattern comprises a polysilicon layer.
16. The method of claim 15,
After forming the plurality of hole patterns,
And forming a storage node in each of the plurality of hole patterns.
KR1020130130170A 2013-10-30 2013-10-30 Mask pattern for hole patterning and method for fabricating semiconductor device using the same KR20150049506A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10050129B2 (en) 2016-03-03 2018-08-14 Samsung Electronics Co., Ltd. Method of forming fine patterns
CN113823553A (en) * 2020-06-19 2021-12-21 中国科学院微电子研究所 Double-pattern mask and manufacturing method thereof, semiconductor device and electronic equipment
CN113964089A (en) * 2021-09-29 2022-01-21 长鑫存储技术有限公司 Semiconductor structure forming method and semiconductor structure
US11637174B2 (en) 2020-03-18 2023-04-25 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
CN113823553B (en) * 2020-06-19 2024-05-31 中国科学院微电子研究所 Double-pattern mask, manufacturing method thereof, semiconductor device and electronic equipment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10050129B2 (en) 2016-03-03 2018-08-14 Samsung Electronics Co., Ltd. Method of forming fine patterns
US10439048B2 (en) 2016-03-03 2019-10-08 Samsung Electronics Co., Ltd. Photomask layout, methods of forming fine patterns and method of manufacturing semiconductor devices
US11637174B2 (en) 2020-03-18 2023-04-25 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
CN113823553A (en) * 2020-06-19 2021-12-21 中国科学院微电子研究所 Double-pattern mask and manufacturing method thereof, semiconductor device and electronic equipment
CN113823553B (en) * 2020-06-19 2024-05-31 中国科学院微电子研究所 Double-pattern mask, manufacturing method thereof, semiconductor device and electronic equipment
CN113964089A (en) * 2021-09-29 2022-01-21 长鑫存储技术有限公司 Semiconductor structure forming method and semiconductor structure
CN113964089B (en) * 2021-09-29 2024-05-17 长鑫存储技术有限公司 Method for forming semiconductor structure and semiconductor structure

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