KR20150039699A - Inductor structure with magnetic material and method for forming the same - Google Patents

Abstract

Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inductor structure having a magnetic material,

The present invention relates to an inductor structure having a magnetic material and a method of forming the same.

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductive material layer over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements on the substrate do.

Generally, an inductor is a passive electrical component that can store energy in a magnetic field created by the current through the inductor. The inductor may be configured as a conductive material surrounding the core of the dielectric material. One inductor parameter that can be measured is the magnetic energy storage capability of the inductor, also known as the inductance of the inductor. Another parameter that can be measured is the quality (Q) coefficient of the inductor. The Q factor of the inductor is a measure of the inductor efficiency and can be calculated as the ratio of the inductance reactance of the inductor to the inductor's resistance at a given frequency.

Inductors can be used in a wide variety of applications. Such an inductor application may be a choke in which the inductor is designed to have or block a high inductive reactance for a signal having a particular frequency in an electrical circuit while allowing the passage of another signal of a different frequency in the electrical circuit . The chokes can be made, for example, to block radio frequencies (RF) and can be referred to as RF chokes used in wireless communications.

However, there are many challenges to form an inductor.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present disclosure and the advantages of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: Fig.
Figures 1A-1C show cross-sectional views of various stages of forming an inductor structure according to some embodiments of the present disclosure.
2A-2H illustrate cross-sectional views of various steps for forming an inductor structure in accordance with some embodiments of the present disclosure.
Figure 3a shows a top view of an inductor structure according to some embodiments of the present disclosure.
FIG. 3B shows a cross-sectional view of the inductor structure according to BB 'in FIG. 3A, in accordance with some embodiments of the present disclosure.
Figure 3C shows a cross-sectional view of an inductor structure along CB 'in Figure 3A, according to some embodiments of the present disclosure.

The manufacture and use of embodiments of the present invention are described in detail below. It should be appreciated, however, that the embodiments may be practiced in a wide variety of specific environments. The particular embodiments discussed are merely illustrative and are not intended to limit the scope of the disclosure.

It should be understood that the following inventive disclosures provide a number of different embodiments or examples for implementing different features of the disclosure of the present invention. Specific examples of components and arrangements for simplifying the disclosure of the present invention are described below. Of course, these are for illustrative purposes only and are not intended to be limiting. In addition, in the following detailed description, performing the first process before the second process may include an embodiment in which the second process is performed immediately after the first process, and further, between the first process and the second process, May also be performed. Various features may be arbitrarily drawn at different scales for simplicity and clarity. In addition, forming the first feature on or in the second feature may include embodiments in which the first and second features are formed in direct or indirect contact.

Variations of some embodiments are described. Throughout the drawings and the illustrative embodiments, the same reference numerals are used to indicate the same elements.

An embodiment of a mechanism for forming the inductor structure 100 is provided. 1A-1C show cross-sectional views of various steps for forming an inductor structure 100 in accordance with some embodiments of the present disclosure. However, Figures 1A-1C have been simplified to further clarify the inventive concepts of the present disclosure. Additional features may be added in the inductor structure 100, and some of the following features may be replaced or eliminated.

Referring to FIG. 1A, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be made of silicon or other semiconductor material. Alternatively or additionally, the semiconductor substrate 102 may comprise another elemental semiconductor material such as germanium. In some embodiments, the semiconductor substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 102 is comprised of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 102 comprises an epitaxial layer. For example, the semiconductor substrate 102 has an epitaxial layer overlying the bulk semiconductor.

The semiconductor substrate 102 may further include isolation features such as a shallow trench isolation (STI) feature or a local oxidation of silicon (LOCOS) feature. Isolation features can define and isolate various integrated circuit devices. A metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high-voltage transistor, a high- And / or an integrated circuit device, such as an n-channel field effect transistor (pFET / NFET), a diode, or other suitable elements are formed in and / or on semiconductor substrate 102.

The semiconductor substrate 102 may also include various p-type doped regions and / or n-type doped regions, which are performed by processes such as ion implantation and / or ion diffusion. These doped regions may be selected from the group consisting of a resistor, a capacitor, an inductor, a diode, a metal oxide semiconductor field effect transistor (MOSFET), a complementary MOS (CMOS) transistor, a bipolar junction transistor (BJT), a lateral diffusion MOS (LDMOS) (N-well), a p-well (n-well), and a p-well, each of which is configured to form a variety of integrated circuit (IC) devices such as a pin-shaped field effect transistor (FinFET), an imaging sensor, a light emitting diode Light doped region (LDD), heavily doped source and drain (S / D), and various channel doping profiles.

The semiconductor substrate 102 may also include a gate stack formed by a dielectric layer and an electrode layer. The dielectric layer may include an inter-layer IL and a high-k (HK) dielectric layer. The dielectric layer can be deposited by any suitable technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, do. The electrode layer may comprise a single layer or multiple layers, such as a metal layer, a liner layer, a wetting layer and an adhesive layer formed by ALD, PVD, CVD or other applicable processes.

As shown in FIG. 1A, the interconnect structure 110 is formed on the semiconductor substrate 102. In some embodiments, the interconnect structure 110 is embedded in an inter-metal dielectric (IMD) layer 114. The interconnect structure 110 is configured to be coupled to a variety of p-type and n-type doped regions and other functional features (e.g., gate electrodes) resulting in a functional integrated circuit. The interconnect structure 110 includes a first metal layer 112, a contact (not shown), and via features (not shown). In some embodiments, the first metal layer 112 is a topmost metal layer and is referred to as M _top . The first metal layer 112 provides horizontal electrical routing. The contacts provide a vertical connection between the silicon substrate and the metal lines while the via features provide a vertical connection between the metal lines in the different layers. In some embodiments, the intermetal dielectric (IMD) layer 114 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, BSG, BPSG, low-k or ultra low-k dielectrics.

In some embodiments, interconnect structure 110 is formed in a back-end-of-line (BEOL) process. The first metal layer 112 may be made of a conductive material such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy or applicable material. In some embodiments, the first metal layer 112 comprises copper or a copper alloy. In some embodiments, the first metal layer 112 is formed by a single and / or dual damascene process.

As shown in FIG. 1A, an etch stop layer 120 is formed over the interconnect structure 110. In some embodiments, the etch stop layer 120 is comprised of silicon nitride.

After the etch stop layer 120 is formed on the interconnect structure 110, a magnetic layer 130 is formed on the etch stop layer 120. The magnetic layer 130 is insulated from the metal line 112 by the etch stop layer 120. The magnetic layer 130 includes Co, Zr, Ta, and Nb, Re, Ne, Pr, or Dy.

In some embodiments, the magnetic layer 130 comprises an amorphous cobalt (Co) alloy including cobalt (Co) and zirconium (Zr). Zirconium (Zr) helps to form cobalt (Co) amorphous. In some embodiments, the magnetic layer 130 includes a cobalt-zirconium (CoZr) alloy having one or more additional elements such as tantalum (Ta), niobium (Nb), and the like. In some other embodiments, the magnetic layer 130 includes a cobalt-zirconium (CoZr) alloy having one or more additional elements, such as a rare earth element, which helps to increase the ferromagnetic resonance of the cobalt-zirconium (CoZr) alloy. The rare earth element includes rhenium (Re), neodymium (Nd), praseodymium (Pr) or dysprosium (Dy).

Thereafter, a photoresist layer 150 is formed on the magnetic layer 130. The photoresist layer 150 is patterned by a photolithography process to form a patterned photoresist layer 150. In some embodiments, photoresist layer 150 is a positive photoresist and includes a photo-solubilized polymer upon exposure to light. In some embodiments, the photoresist layer 150 is formed by a spin-on coating process.

After forming a patterned photoresist layer 150 over the magnetic layer 130, an etch process 11 is performed on the magnetic layer 130, as shown in Figure IB according to some embodiments of the present disclosure . The etching process 11 is used to remove a portion of the magnetic layer 130. In some embodiments, the etchant used in the etching step (11) comprises HF, HNO ₃ and water. In some embodiments, the etching process 11 is operated at a temperature in the range of about 15 캜 to about 40 캜.

However, as shown in FIG. 1B, the lateral direction etching rate of the X-direction etching step 11 is larger than the vertical direction etching rate of the Y-direction etching step 11. Therefore, the side portion of the magnetic layer 130 is etched more than the vertical portion of the magnetic layer 130. [ As a result, the volume of the magnetic layer 130 is greatly reduced by the etching process 11.

A second intermetal dielectric (IMD) layer 140 is then formed over the magnetic layer 130 and the etch stop layer 120, as shown in Figure 1C according to some embodiments of the present disclosure. A trench is formed in the second IMD layer 140 by a photolithography process and an etching process. A conductive material is filled into the trenches to form the vias 160 and the second metal layer 162. In some embodiments, a spiral structure is formed by the first metal layer 112, the via 160, and the second metal layer 162.

Vias 160 are formed in the second IMD layer 140 and a second metal layer 162 is formed on the vias 160 and the second IMD layer 140. The vias 160 and the second metal layer 162 may be independently formed of a conductive material such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, . In some embodiments, the inductor structure 100 is comprised of a magnetic layer 130, a first metal layer 112, a via 160, and a second metal layer 162.

As mentioned above, the lateral etch rate of the X-direction etch process 11 is greater than the vertical etch rate of the Y-direction etch process 11. Therefore, the volume of the magnetic layer 130 is greatly reduced by the etching step 11. In addition, the performance of the inductor structure 100 is reduced by the small volume of the magnetic layer 130. For example, the Q factor of the inductor structure 100 is reduced due to the small volume of the magnetic layer 130. In order to improve the performance of the inductor structure 100, a large-volume magnetic layer 130 is required.

2A-2H illustrate cross-sectional views of various steps for forming an inductor structure 100 in accordance with some embodiments of the present disclosure. Referring to FIG. 2A, an oxide layer 124 is deposited on the etch stop layer 120. In some embodiments, the oxide layer 124 is comprised of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, borosilicate glass (BSG), and borophosphosilicate glass (BPSG). After the oxide layer 124 is formed, a photoresist layer 150 is formed over the oxide layer 124. Thereafter, the photoresist layer 150 is patterned by a photolithography process to form a patterned photoresist layer 150.

After forming the patterned photoresist layer 150, the oxide layer 124 may be patterned as a mask to form the patterned oxide layer 124, as shown in FIG. 2B, according to some embodiments of the present disclosure. Is patterned by using a patterned photoresist layer (150). In some embodiments, the material of the oxide layer 124 is the same as the material of the intermetal dielectric (IMD) layer 114. In some embodiments, the oxide layer 124 has a height within the range of about 0.5 [mu] m to about 20 [mu] m. 2B, an opening 125 is formed in the oxide layer 124

2C according to some embodiments of the present disclosure, the magnetic layer 130 may be formed conformally on the oxide layer 124 to be filled with the openings 125, . To increase the inductance of the inductor structure 100, a magnetic layer 130 is disposed in the central portion (or core) of the inductor structure 100 (as shown in FIG. 3A).

The magnetic layer 130 has two portions, including a first portion 131 over the etch stop layer and a second portion 132 over the oxide layer 124. The first portion further includes a horizontal portion 131h and a vertical portion 131v and the vertical portion 131v forms a line with the side wall of the opening 125. [ The horizontal portion 131h of the first portion 131 of the magnetic layer 130 has a height H ₂ . In some embodiments, the height H ₁ of the oxide layer 124 is greater than or equal to the height H ₂ of the horizontal portion 131h. In some embodiments, the ratio of height H ₁ to height H ₂ (H ₁ / H ₂ ) is in the range of about 0.2 to about 5.

After the magnetic layer 130 is formed on top of the etch stop layer 120 and the oxide layer 124, as shown in FIG. 2D according to some embodiments of the disclosure of the present invention, the magnetic layer 130 is formed on the first portion of the magnetic layer 130 The second photoresist layer 150 'is conformally formed. In some embodiments, the mask used to form the patterned photoresist layer 150 in FIG. 2A has a clear tone and is used to form the second patterned photoresist layer 150 ' The same mask has a dark tone. Thus, the patterned photoresist layer 150 and the second patterned photoresist layer 150 'are formed using the same mask without two masks.

After the second patterned photoresist layer 150 'is formed on top of the magnetic layer 130, an etch process 11 may be performed on the magnetic layer 130, as shown in Figure 2E, according to some embodiments of the present disclosure. . The etching process 11 is used to remove a portion of the magnetic layer 130. In some embodiments, the etchant used in the etch process 11 comprises HF in the range of about 3% to about 15%, HNO _{3 in} the range of about 10% to about 50%, and HNO _{3 in} the range of about 30% to about 90% Water in the range. In some embodiments, the etching process 11 is operated at a temperature in the range of about 15 캜 to about 40 캜.

As mentioned above, the lateral etch rate of the X-direction etch process 11 is greater than the vertical etch rate of the Y-direction etch process 11. It should be noted that this is because the oxide layer 124 is formed under the magnetic layer 130 to lift up a portion of the magnetic layer 130. The upper surface of the second portion 132 of the magnetic layer 130 is higher than the upper surface of the first portion 131 of the magnetic layer 130. The second portion 132 of the magnetic layer 130 is first etched and the first portion of the magnetic layer 130 is etched as the etch rate of the etch process 11 is greater than the perpendicular etch rate 131 are later etched. Therefore, the horizontal portion 131h of the first portion of the magnetic layer 130 is slightly etched by the protection of the oxide layer 124. [

It should be noted that the oxide layer 124 provides a base for lifting a portion of the magnetic layer 130. In addition, the oxide layer 124 becomes a protective layer for protecting the magnetic layer 130 from excess etching. Therefore, the volume of the magnetic layer 130 is not greatly reduced by the etching process 11. [

After the etching process 11, the magnetic layer 130 has a polygonal structure, as shown in Figure 2F according to some embodiments of the present disclosure. 2F, the magnetic layer 130 has an octagonal structure. The magnetic layer 130 includes an upper surface 130T, a first sidewall surface 130a, a second sidewall surface 130b, a third sidewall surface 130c, a bottom surface 130B, a fourth sidewall surface 130d, A wall surface 130e, and a sixth sidewall surface 130f. The upper surface 130T is the upper plane and the lower surface 130B is the lower plane. The upper surface 130T is parallel to the bottom surface 130B.

The magnetic layer 130 has a right side wall surface and a left side wall surface which are disposed opposite to each other. The right side wall surface includes a first sidewall surface 130a, a second sidewall surface 130b, and a third sidewall surface 130c. The left side wall surface includes a first sidewall surface 130a, a second sidewall surface 130b, and a third sidewall surface 130c. The right side wall surface of the magnetic layer 130 has three intersection points. The first intersection point P ₁ is formed between the upper surface 130T and the first sidewall surface 130a and the second intersection point P ₂ is formed between the first sidewall surface 130a and the second sidewall surface 130b And the third intersection point P _{3 is} formed between the second sidewall surface 130b and the third sidewall surface 130c. Similarly, the left side wall surface of the magnetic layer 130 has at least two intersection points including the fourth intersection P ₄ , the fifth intersection P ₅ , and the sixth intersection P ₆ .

In some embodiments, the angle? ₁ between the first sidewall surface 130a and the second sidewall surface 130b is in a range between about 30 degrees and about 85 degrees. In some embodiments, the angle [alpha] ₂ between the second sidewall surface 130b and the third sidewall surface 130c is in a range between about 95 degrees and about 150 degrees.

In some other embodiments, as shown in Figure 2f 'in accordance with some embodiments of the present disclosure, the magnetic layer 130' has a trapezoidal structure. The magnetic layer 130 'has an upper surface 130'T, a first sidewall surface 130'a, a second sidewall surface 130'b, a bottom surface 130'B, a third sidewall surface 130'c, And a fourth sidewall surface 130'd. The top surface 130'T is the top plane and the bottom surface 130'B is the bottom plane. The top surface 130'T is parallel to the bottom surface 130'B.

The right side wall surface of the magnetic layer 130 'has two intersecting points. A first intersecting point (P ₁ ') is formed between the upper surface (130'T) and the first side wall surface (130'a), the second intersecting point (P _2') and is the first side wall surface (130'a) 2 side wall face 130'b. Likewise, the left side wall surface of the magnetic layer 130 'has at least two intersection points including the third intersection P ₃ ' and the fourth intersection P ₄ '.

In some embodiments, the angle beta ₁ between the first sidewall surface 130'a and the second sidewall surface 130'b is in a range between about 120 degrees and about 175 degrees. In some embodiments, the angle? ₂ between the second sidewall surface 130'b and the third sidewall surface 130'c is in a range between about 95 degrees to about 150 degrees.

After the magnetic layer 130 is etched by the etching process 11, a second intermetal dielectric (IMD) layer 140 is deposited over the oxide layer 124, as shown in Figure 2G, according to some embodiments of the present disclosure. And the magnetic layer 130.

2H, a trench is formed in the second IMD layer 140 by a photolithography process and an etching process. A conductive material is filled into the trenches to form the vias 160 and the second metal layer 162. The second metal layer 162 is electrically connected to the first metal layer 112 via the via 160. The inductor structure 100 is comprised of a first metal layer 114, a second metal layer 162, and a magnetic layer 130.

It should be noted that a portion of the magnetic layer 130 is formed on the oxide layer 124 (as shown in Figure 2D). Hence, the vertical portion of the magnetic layer 130, which is in line with the sidewalls of the openings 125, is first etched by the etching process 11 (as indicated by the etching direction indicated by arrow 11a). Compared to the magnetic layer 130 shown in FIG. 1C, the magnetic layer 130 shown in FIGS. 2F and 2F 'has a larger volume. As a result, the inductor structure 100 including the large volume magnetic layer 130 has better performance (high Q factor).

Figure 3a shows a top view of an inductor structure 100 according to some embodiments of the present disclosure. The spiral structure is formed by the first metal layer 112, the via 160, and the second metal layer 162. The magnetic layer 130 formed by the processes of FIGS. 2A through 2H is disposed in the central portion of the inductor structure 100 and is surrounded by the spiral structure. The magnetic layer 130 has a polygonal structure, such as an octagonal or trapezoidal structure, having a large volume to increase the Q factor of the inductor structure 100.

FIG. 3B shows a cross-sectional view of the inductor structure 100 according to BB 'in FIG. 3A, in accordance with some embodiments of the present disclosure. The first metal layer 114 is electrically connected to the second metal layer 162 via the via 160 and the second metal layer 162 is electrically connected to the third metal layer (not shown) through the second via 164 Respectively.

FIG. 3C shows a cross-sectional view of an inductor structure 100 along CB 'in FIG. 3A, in accordance with some embodiments of the present disclosure. The magnetic layer 130 has an octagonal structure with a large volume to increase the Q factor of the inductor structure 100.

An embodiment of a mechanism for forming an inductor structure is provided. To increase the inductance of the inductor structure, a magnetic layer is disposed in the central portion (or core) of the inductor structure. An oxide layer is formed below a portion of the magnetic layer to protect the magnetic layer from excess etching. Therefore, a large-volume inductor structure is obtained. The performance of the inductor structure is improved by increasing the volume of the inductor structure. In addition, the Q factor of the inductor structure is further improved.

In some embodiments, an inductor structure is provided. The inductor structure includes a substrate and a first dielectric layer formed on the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer on the first metal layer. The inductor structure further includes a magnetic layer formed on the first dielectric layer, and the magnetic layer has a top surface, a bottom surface, and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points.

In some embodiments, an inductor structure is provided. The inductor structure includes a substrate and a first metal layer formed in the first dielectric layer. The inductor structure includes a magnetic layer formed on the first dielectric layer, and the magnetic layer has an octagonal or trapezoidal structure. The inductor structure also includes an oxide layer formed adjacent to the magnetic layer. The inductor structure includes a second dielectric layer formed on the magnetic layer and the oxide layer, and a second metal layer formed on the second dielectric layer.

In some embodiments, a method of forming an inductor structure is provided. The method includes providing a substrate and a first metal layer formed in the first dielectric layer. The method also includes forming and patterning an oxide layer to form an opening in the oxide layer, and forming the magnetic material conformally on the oxide and in the opening. The method also includes forming a photoresist layer over the magnetic material, and performing a wet etch process on the magnetic material to form the magnetic layer. The method further comprises forming a second dielectric layer on the magnetic layer and forming a second metal layer on the second dielectric layer.

Although the embodiments of the present disclosure and the advantages thereof have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the scope and spirit of the present disclosure as defined by the appended claims . It will be readily appreciated by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied and remain within the scope of the disclosure of the present invention. Further, the scope of the present application is not intended to be limited to the specific embodiments of the materials, means, methods, and steps of the process, machine, manufacture, composition of matter described herein. Means, methods, or steps of a material, means, method, or step to be developed that will perform substantially the same function or achieve substantially the same result as those of the corresponding embodiments described herein, It will be readily appreciated from the disclosure of the disclosure of the present invention that manufacture, composition can be used according to the disclosure of the present invention. Accordingly, the appended claims are intended to cover within the scope of the claims the process, machine, manufacture, composition of such material, means, method, or step.

Claims (10)

In an inductor structure,
Board;
A first dielectric layer formed on the substrate;
A first metal layer formed in the first dielectric layer;
A second dielectric layer on the first metal layer;
The first dielectric layer
/ RTI >
Wherein the magnetic layer has a top surface, a bottom surface, and sidewall surfaces between the top surface and the bottom surface, the sidewall surfaces having at least two intersection points. The method according to claim 1,
Wherein the sidewall surfaces include a first sidewall surface, a second sidewall surface, and a third sidewall surface, the first sidewall surface is connected to the upper surface, and the angle between the first sidewall surface and the second sidewall surface is 30 Lt; RTI ID = 0.0 > 85 degrees. ≪ / RTI > The method according to claim 1,
Wherein the sidewall surfaces include a first sidewall surface and a second sidewall surface, the first sidewall surface is connected to the upper surface, and the angle between the upper surface and the first sidewall surface is within a range of 120 to 175 degrees Inductor structure. The method according to claim 1,
The magnetic layer may include one or more of Co, Zr, Ta and Nb, Re, Ne, Pr, Ds or combinations thereof Inductor structure. The method according to claim 1,
Wherein the first metal layer, the vias, and the second metal layer form a spiral structure. The method according to claim 1,
Wherein the magnetic layer is surrounded by the helical structure. The method according to claim 1,
The etch stop layer formed on the first metal layer
Wherein the magnetic layer is insulated from the first metal layer by the etch stop layer. The method according to claim 1,
Vias formed in the second dielectric layer; And
The second metal layer
Wherein the second metal layer is electrically connected to the first metal layer by the vias. In an inductor structure,
Board;
A first metal layer formed in the first dielectric layer;
A magnetic layer having an octagonal or trapezoidal structure and formed on the first dielectric layer;
An oxide layer formed adjacent to the magnetic layer;
A second dielectric layer formed on the magnetic layer and the oxide layer; And
The second metal layer formed on the second dielectric layer
. ≪ / RTI > A method of forming an inductor structure,
Providing a substrate;
Forming a first metal layer in the first dielectric layer;
Forming and patterning an oxide layer to form an opening in the oxide layer;
Forming a magnetic material conformally on the oxide layer and in the opening;
Forming a photoresist layer on the magnetic material;
Performing a wet etching process on the magnetic material to form a magnetic layer;
Forming a second dielectric layer on the magnetic layer; And
Forming a second metal layer on the second dielectric layer
/ RTI >

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