KR20150031496A - Nonvolatile semiconductor memory device - Google Patents

Abstract

A nonvolatile memory having a memory capacity other than a power of two is disclosed. The non-volatile memory device includes at least one plane. Wherein the at least one plane comprises a plurality of blocks, each of the plurality of blocks is divided into a plurality of pages, each of the plurality of blocks is arranged along a first dimension by a first number of memory cells for storing data, Is defined along the second dimension by a second number of memory cells for storing data. The non-volatile memory has a capacity that is not a power of 2 proportional to the total number of memory cells in at least one plane. The nonvolatile memory also includes a plurality of row decoders. In this non-volatile memory device, there is at least a substantially one-to-one relationship to the number of row decoders for the number of pages. Each of the plurality of row decoders is configured to facilitate a read operation on an associated page of the non-volatile memory device.

Description

[0001] NONVOLATILE SEMICONDUCTOR MEMORY DEVICE [0002]

Background of the present disclosure

Today, many electronic devices include memory systems to store information. For example, some memory systems store digitized audio or video information for playback by each media player. Other memory systems store software and related information to perform different types of processing functions. Some types of memory systems, such as, for example, a dynamic random access memory (DRAM) system and a static random access memory (SRAM) system, are volatile memory systems in which data stored when power is turned off are not maintained, Other types of memory systems, such as NAND flash memory systems and NOR flash memory systems, are nonvolatile memory systems where stored data is maintained when power is turned off.

Typically, the memory capacity of a memory system is doubled for every occurrence due to the nature of the binary address bit structure in the computing system, whether the system is "volatile" or "non-volatile". It is generally understood that among those skilled in the art, the doubled memory capacity (memory capacity being a power of two) is a requirement that must be followed when used in a main memory system. Also, in volatile memory systems, there have been some previous proposals for having a memory capacity other than a power of two, but at least in the context of a non-volatile memory system, a memory system that currently has a memory capacity other than a power of two is produced There is clearly no practical way to do this.

Of course, it would be useful to be able to produce a non-volatile memory system with a memory capacity other than a power of two. In this regard, one problem with doubling the memory capacity without scaling down the process technology is that generally associated circuitry and components of larger size are limited, for example, to an increase in physical size in one dimension And that the required size increase can no longer be fitted into the same package due to physical constraints such as being outside of the definite limit for any potential size increase. Also, changing the package may not be an option because the industry adopts a standard package such as the 48-pin TSOP-1, for example. Thus, the effect of switching from a standard package to a non-standard package may result in some cases such as redesigning the entire printed circuit board.

If these problems are raised by increasing the physical size while being kept in the same package, scaling down the process technology is the remaining alternative option to be considered; Reducing the scale of process technology is a huge investment. In many situations, it will be substantially more expensive to increase memory capacity without having to scale down the process technology.

summary

It is an object of the present invention to provide an improved nonvolatile memory.

According to an aspect of the invention, there is provided a non-volatile memory device comprising at least one plane. Wherein the at least one plane comprises a plurality of blocks, each of the plurality of blocks is divided into a plurality of pages, each of the plurality of blocks is arranged along a first dimension by a first number of memory cells for storing data, Is defined along the second dimension by a second number of memory cells for storing data. The non-volatile memory has a capacity that is not a power of 2 proportional to the total number of memory cells in the data section of at least one plane. The nonvolatile memory also includes a plurality of row decoders. In this non-volatile memory device, there is at least a substantially one-to-one relationship to the number of row decoders for the number of pages. Each of the plurality of row decoders is configured to facilitate a read operation on an associated page of the non-volatile memory device.

According to another aspect of the present invention, there is provided a memory system including at least one non-volatile memory device having at least one plane. The at least one plane includes a plurality of blocks, and each of the plurality of blocks is divided into a plurality of pages. Each of the plurality of blocks is defined along a first dimension by a first number of memory cells for storing data and along a second dimension by a second number of memory cells for storing data. The at least one non-volatile memory device has a capacity that is not a power of two in proportion to the total number of memory cells in the data section of at least one plane. The controller communicates with the at least one non-volatile memory device. The controller includes a storage and management module. Storage stores map tables. The management module is configured to access the map table to perform the conversion of logical addresses into physical addresses. An invalid physical address due to a non-power-of-two power of the at least one non-volatile memory device is mapped out in the map table.

According to another aspect of the present invention, a method of populating a memory controller table with data is provided. This memory controller table is stored in the RAM (Random Access Memory) of the memory controller. The memory controller communicates with at least one non-volatile memory device having at least one memory cell array for storing data for management functions of the memory controller. At least one memory cell array has a capacity that is not a power of two. A method of populating the memory controller table with data includes extracting data from at least one memory cell array. The method of populating the memory controller table with data also includes processing the data in the memory controller to determine an invalid physical address due to a non-power of two of the at least one memory cell array. The method of populating the memory controller table with data also includes altering the memory controller table to map out an invalid physical address.

According to yet another aspect of the present invention, there is provided a network capable of transmitting and receiving communications transmitted over the Internet. The network includes at least one server and at least one data store in communication with the at least one server. The at least one server may receive data comprising information corresponding to an order for at least one item comprising at least one non-volatile memory chip having a capacity that is not a power of two. The at least one server may also process the data to make it eligible for storage in the at least one data store. The at least one server may also generate an electronic notification suitable for transmission over the Internet to provide the customer with confirmation of receipt of the order.

Thus, an improved nonvolatile memory has been provided.

Hereinafter, reference will be made to the accompanying drawings as embodiments.
1 is a block diagram of an exemplary NAND flash chip floor plan.
2 is a functional block diagram of an exemplary NAND flash memory.
3 is a block diagram of a host system and memory system, which in some embodiments includes a plurality of memory devices each corresponding to the flash memory shown in Fig.
4A is a block diagram illustrating a read operation in an exemplary NAND flash device.
4B is a block diagram illustrating program operation in an exemplary NAND flash device.
5 is a block diagram of an exemplary floor plan for a NAND flash chip manufactured in accordance with one exemplary embodiment.
6 is a block diagram of an exemplary floor plan for a NAND flash chip fabricated in accordance with another exemplary embodiment.
7 is a block diagram of an exemplary floor plan for a NAND flash chip made in accordance with another exemplary embodiment.
8 is a block diagram of an exemplary plane of a NAND flash chip, which shows redundant sections and other sections of this plane.
Figure 9 is a block diagram of a communications arrangement between a memory device manufacturer and a customer company.
10 is a block diagram of a communication arrangement between a customer and a company selling memory products.
11 is a flow diagram of a method of ordering a memory device or memory product in accordance with some exemplary embodiments.
12 is a diagram illustrating portions of an exemplary graphical user interface (GUI) in accordance with an exemplary embodiment.
13 is a diagram illustrating portions of another exemplary GUI in accordance with another exemplary embodiment.
14 is a block diagram of a communications arrangement that facilitates non-volatile memory media update in accordance with some example embodiments.
Similar or identical reference numerals may be used in different drawings to indicate similar components.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

For many electronic devices, memory systems often include a controller and one or more corresponding flash memory devices. Typically, the controller includes circuitry configured to generate a signal for a memory device for retrieval and storage of data from the flash memory device.

Referring now to the drawings, FIG. 1 is a block diagram of an exemplary NAND flash chip floor plan 100 illustrating the actual placement of key components within a chip area of a flash memory device. In this floor plan 100, two row decoder regions 110 and 112 extend between adjacent memory cell array regions 114 and 116 and 118 and 120, respectively. With respect to the row decoder areas 110 and 112, within these row decoder areas, a row decoder of the flash memory device can be found. With respect to memory cell array regions 114, 116, 118, and 120, within these memory cell array regions, a memory cell array of flash memory devices can be found.

The input / output pad regions 124 and 126 extend along the widthwise edges of the floor plan 100 and the high voltage generator regions 130 and 132 and the peripheral circuit region 134 extend along the longitudinal edges of the floor plan 100. [ Lt; / RTI > With respect to the input / output pad areas 124 and 126, within these input / output pad areas, the input / output pads of the flash memory device can be found. With respect to the high voltage generator regions 130 and 132, a high voltage generator of a flash memory device, such as a charge pump, for example, is found within these high voltage generator regions. With respect to the peripheral circuit region 134, other circuits that are important for device operation, such as, for example, control circuits, may be found within this peripheral circuit region. In addition, there are additional circuit regions 140 and 142 adjacent the peripheral circuit region 134. Within these additional circuit areas, page buffers and column decoders of flash memory devices can be found.

Those skilled in the art will recognize that the chip floor plan for non-volatile memory varies depending on the designer's choice within the operating constraints and specifications. For example, the Toshiba Corporation produces a non-volatile memory device having a row decoder region extending between two relatively adjacent edges of an area of these two planes of some two planes. By comparing the floor plan 100 and the floor plan of the Toshiba memory device, the following differences (a list that does not cover everything) may be found: an input / output pad area extending along an edge adjacent to the peripheral circuit area, Rather than having one high voltage generator region, two spaced row decoder regions, the row decoder region extends below the center of the floor plan.

Referring now to Figure 2, a functional block diagram of an exemplary NAND flash memory device 200 is shown. The NAND flash memory device 200 includes a common input / output port (I / O pin 0 to I / O pin) for transferring input / output data, commands and addresses to and from the device 200 7). In addition, the illustrated device 200 includes a Command Latch Enable (CLE) port. The CLE input signal to this port is used to control the loading of the operation mode command into the internal command register 210. The command is latched from the I / O port to the command register 210 at the rising edge of the / WE signal while CLE is logic high. In addition, the illustrated device 200 includes an Address Latch Enable (ALE) port. The ALE signal to this port is used to control the loading of address information into the internal address register 212. Address information is latched from the I / O port to the address register 212 at the rising edge of the / WE signal while ALE is logic high. Along with the address latch enable (ALE) port, the illustrated device 200 further includes a chip enable (/ CE) port. In particular, the device 200 enters a low power standby mode when / CE goes to logic high when the device is in the ready state. On the other hand, when the device 200 is in the busy state (i.e., / RB is logic low), such as during a program operation or an erase or read operation, the / CE signal is ignored and the device / The control unit 200 will not enter the standby mode.

In addition, the illustrated device 200 includes ports for enabling write and read operations. The write enable (/ WE) port receives the / WE signal, which is used to control the acquisition of data from the I / O port. The read enable (/ RE) port receives the RE signal for controlling the serial data output. Data is available after the falling edge of / RE. Also, on this falling edge, the internal column address counter (not explicitly shown) is incremented (address = address + 1).

Also, the illustrated device 200 includes a write protection (/ WP) port. The / WP port receives the / WP signal used to protect the device 200 from accidental programming or erasure. / WP is logic low, the internal voltage regulator (high voltage generator 218) is reset. Generally, the / WP signal is used to protect data during power on / off sequences when the input signal is invalid. With the write protection (/ WP) port, the illustrated device 200 further includes a ready / busy (/ R-B) port. The / R-B port includes an open drain pin, and the transmitted output signal is used to indicate the operating state of the device. During programming, erasing and reading operations, the / R-B signal is in the busy state (/ R-B is a logic low) and will return to the ready state after completion of this operation (/ R-B is a logic high).

Still referring to FIG. 2, the memory core of the illustrated device 200 includes a memory cell array 222, a row decoder 226, a sense amplifier and page buffer 230, and a column decoder 234. With respect to the row decoder 226, a page for either the read operation or the program operation is selected by the row decoder. In the erase operation, row decoder 226 includes a memory cell array (not shown) defined along a first dimension by a first number of memory cells storing data and by a second number of other memory cells along a second dimension 222 are selected. It will also be appreciated that, in the context of Flash and other similar non-volatile memory, the block is a subdivision of the memory cell array 222 that is larger than the page. With respect to the subdivision layer, the plane of the memory device includes a plurality of blocks, each of which is divided into a plurality of pages.

Continuing with the description of the operation, with respect to the data of the page selected by the row decoder 226 with respect to the read operation, this data is sensed and latched into the sense amplifier and page buffer 230 during the read operation. Thereafter, the data stored in the page buffer is sequentially read out through the column decoder 234 and the global buffer 238. [ The global buffer 238 temporarily holds and buffers input and output data through the common I / O pins. During programming, the input data from the global buffer 238 is sequentially loaded into the page buffer via the column decoder 234. [ Finally, the input data latched in the page buffer is programmed to the selected page.

The memory cell array 222 is electrically connected to the high voltage generator 218. The high voltage generator 218 provides the necessary high voltage and reference voltage during the read operation, the program operation and the erase operation. To track device status during a read, program, or erase operation, the illustrated device 200 includes a status register 244. Also, the / R-B pin coupled to the / prepare-busy (/ R-B) circuit 246 together provide another indicator for the device status. In at least some embodiments, the / RB circuit 246 includes an open drain transistor (not explicitly shown).

In addition, the illustrated device 200 includes a control circuit 250, which is a central unit in at least some embodiments. The control circuit 250 enables control of the device 200 during various operating modes. A control buffer 252, which acts as a buffer for the control circuit 250, is in electrical communication with the control circuit 250.

In addition, the illustrated device 200 includes a row pre-decoder 254 and a column pre-decoder 256. The low-pre-decoder 254 is halfway between the address register 212 and the row decoder 226. The row pre-decoder 254 multiplexes the row address stored in the address register 212 and transfers the multiplexed row address to the row decoder 226. The column pre-decoder 256 is halfway between the address register 212 and the column decoder 234. The column pre-decoder 256 multiplexes the column addresses stored in the address register 212 and transmits the multiplexed column addresses to the column decoder 234. [

Hereinafter, reference will be made to FIG. 3 is a block diagram of a host system 302 and a memory system 306 that are capable of communicating with one another. The memory system 306 includes a plurality of memory devices 308. In some embodiments, each of the memory devices 308 corresponds to the flash memory 200 shown in FIG. In another embodiment, only a portion of the memory device 308 corresponds to the flash memory 200 shown in FIG. 2 and the remaining memory devices 308 correspond to some other type (e.g., Or types) nonvolatile memory devices. In yet another embodiment, no memory device 308 corresponds to the flash memory 200 shown in FIG. 2, and instead all of the memory devices 308 are part of a memory system 306 that can function within the memory system 306 Volatile memory devices of different types (or types).

The memory system 306 also includes a memory controller 312 as shown in accordance with some embodiments. The illustrated memory controller 312 includes a physical interface 316, a host interface 318, and a control module 322. The physical interface 316 enables the memory controller 312 to communicate with the memory device 308 and also enables the memory device 308 to communicate with the memory controller 312. The host interface 318 enables the memory controller 312 to communicate with the host system 302 and also enables the host system 302 to communicate with the memory controller 312. The illustrated host interface 318 is shown in the memory controller 312; In an alternate embodiment, the host interface may be implemented within the system in communication with the memory controller 312 or as a separate device.

Still referring to FIG. 3, the illustrated control module 322 includes a file / memory management submodule 330. Among other possible functions, the file / memory management submodule 330 provides a mapping of logical addresses to physical addresses, so that the physical address of the requested data can be determined. This mapping is performed by distributing and redistributing the data stored in the device to improve performance or so-called " wear-leveling ", and if required, the physical address corresponding to the bad memory cell May not be available or will not be available. This latter mapping aspect is generally referred to as "mapping out ", which is not limited to the mapping out of bad memory cells in the context of the exemplary embodiment. In particular, there is an explanation later on in this disclosure of how this "mapping out" can play a role in handling invalid addresses in non-power-of-two capacitive memory devices.

In at least some embodiments of the memory controller 312, the control module 322 is shown as being a component of the file / memory management submodule 330: allocator, cleaner, and static Wear-leveler. The allocator handles the translation of logical addresses into physical addresses according to any one of the known translation mechanisms understood by those skilled in the art, such as, for example, the NAND flash translation layer (NFTL). With respect to a cleaner, the cleaner handles garbage collection to reclaim pages of invalid data in a manner understood by those skilled in the art. Regarding the static weir-leveler, this static ware-leveler uses data (e.g., data) that is performed in a manner consistent with achieving the intended purpose of evenly distributing the number of erasures for each block (because of a limitation on the number of erasures for the block) Handling wear-leveling featuring redistribution. The motivation for static wear-leveling is to prevent any "cold" data (as opposed to "hot" data) from being held in any block for a long period of time. This synchronization is to minimize the maximum erase-count difference of any two blocks so that the lifetime of the flash memory may be extended.

Hereinafter, reference will be made to FIG. 4A. 4A is a block diagram illustrating a read operation in an exemplary NAND flash device. The internal memory array 410 of the NAND flash device is accessed based on the page (note the example selected page 414). In the illustrated embodiment of Figures 2 and 4A, after writing the address to the device 200 via the common I / O pins (I / O 0 to I / O 7) following the READ command, do. The sense amplifier and page buffer 230 sense and transmit 4224 bytes of data in the selected page 414 within tR (the data transfer time from the flash array to the page buffer). Once the 4224 bytes of data are sensed and transmitted from the selected page 414 in the cell array 410 to the page buffer, the data in the page buffer can be read out sequentially from the device 200. [ As shown in FIG. 4A, for all pages of data, there will be a spare field (in the illustrated embodiment, the spare field is 128 bytes; in other embodiments, the spare field may be any suitable number of bytes) . The purpose of the spare field is as follows: Upon power-up of the memory system 306 and the memory controller 312 (see FIG. 3), the control module 322 generates a set of unequal / variable information for the memory device 308 (E.g., information related to wear-leveling and address mapping). This is done by dumping at least a portion of the data stored in the spare field into SRAM storage (not explicitly shown) in the memory controller 312. Once the data from the spare field is stored locally in the memory controller 312, the control module 322 can use this data to perform its function appropriately. For example, the map table in SRAM storage is accessed in connection with performing the conversion of logical addresses to physical addresses.

In addition to what the memory controller 312 can read from the spare field, the memory controller 312 can also update the data in the spare field. 4B is a block diagram illustrating program operation in an exemplary NAND flash device. With respect to the programming operation of the illustrated embodiment, the PROGRAM command is followed by 4,224 bytes of input data and address via the common I / O pins (I / O 0 to I / O 7) to the device 200 . 4,224 bytes of data are transferred to the page buffer during the input data loading cycle and finally programmed into the selected page 430 of the cell array 434 within tPROG (page program time). As illustrated, 4,224 bytes of data includes 128 bytes of spare field data, and the memory controller 312 (see FIG. 3) is the originator (or originating modifier) of this additional data, The spare field data is communicated from the memory controller 312 to the memory device 308 while in Figure 4A the spare field data is communicated from the memory device 308 to the memory controller 312. [

Reference is now made to Fig. 5, which is a block diagram of an exemplary floor plan 500 for a NAND flash chip fabricated in accordance with one exemplary embodiment. With reference to FIG. 5, for ease of illustration, it is to be appreciated that although some exemplary split units of memory, such as planar and bit lines, are shown, other representative split units such as, for example, pages and blocks, are not shown.

5, two row decoder regions 510 and 512 are formed between adjacent memory cell array regions 514 and 516 and 518 and 520, respectively, in the floor plan 500 of FIG. 5, Respectively. Also, extension regions 528 and 529 extend along the edge of the memory cell region within which the page buffer and column decoder of the flash memory device (as described above) can be found. A plurality of substantially long bit lines 532 extend perpendicular to the lengths of the regions 528 and 529. [ As will be appreciated by those skilled in the art, this bit line 532 is typically electrically connected to the page buffer in regions 528 and 529 in a distributively proportional manner.

If the memory capacity device is a power of two, since the bit line 532 is much longer than the bit line found in this memory device, a correspondingly increased capacity is possible. In particular, it will be appreciated that a longer bit line facilitates the fabrication of a device having a greater number of word lines and hence a greater number of blocks. For example, each plane in a memory capacity device that is a power of two may have 2048 blocks (i.e., blocks of binary numbers), while a memory capacity other than a power of 2 with a longer bit line 532 Each plane in the device may have 2560 blocks (or some other suitable non-binary number of blocks).

It will be appreciated that the effect of fabrication on longer bit line 532 may be more efficient chip area utilization. In particular, with respect to at least some exemplary embodiments, the size of the various chip regions that are not part of the memory cell array do not increase proportionally as the size of the memory cell array regions 514, 516, 518, and 520 increases. In this regard, although the bit line 532 is considerably longer than the bit line in the memory cell array shown in Figure 1, the following areas shown in Figure 5: high voltage generator regions 540 and 542, peripheral circuit region 543, And regions 528 and 529 may be at least similar (or otherwise identical) in size compared to the corresponding regions shown in FIG. For many applications, higher currents on the Vcc side may be expected; These higher currents are of great concern and should not be so large.

Reference is now made to Fig. 6, which is a block diagram of an exemplary floor plan 600 for a NAND flash chip fabricated in accordance with another exemplary embodiment. With reference to FIG. 6, for ease of illustration, some exemplary divided units of memory, such as planar and word lines, are shown, but it will be appreciated that other exemplary divided units such as, for example, pages and blocks, are not shown.

It should be noted that, in the illustrated exemplary embodiment, there are three row decoders 610-612, one for each plane labeled plane 0, plane 1 and plane 2. Thus, in the exemplary embodiment of FIG. 6, the number of non-powers of 2, as opposed to the NAND flash chip illustrated in FIG. 1, having two row decoders and a plane (i. E., The number is a power of two) (3) are present. In the illustrated exemplary embodiment, the number of non-powers of two is three, while in other exemplary embodiments, the number of non-power-of-two decoders and planes may be, for example, five, six , 7, 9, etc. < / RTI > In addition, for the NAND flash device of the illustrated exemplary embodiment, the total number of word lines 620 is 3n (where n is the total number of word lines per plane), such that the total number of word lines is 2 It is to be understood that the multiplication factor 3 is a number other than a power of 2, because it is a non-power number. Because the total number of word lines is a number that is not a power of two, the memory device manufactured in accordance with the illustrated exemplary embodiment can have a power of 2, as can be shown by a capacity calculation that can be easily performed by one skilled in the art Should have capacity.

Still referring to the exemplary embodiment illustrated in FIG. 6, from a chip area utilization perspective, the dimensional difference of the peripheral circuit region 640 with respect to the peripheral circuit region 134 (see FIG. 1) is outstanding. The length of the peripheral circuit area 640 (as measured from one input / output pad to the other input / output pad) is greater than the length of the peripheral circuit area 134. In addition, the opposite dimension of the peripheral circuit region 640 is smaller than the corresponding dimension of the peripheral circuit region 134. Similar to pizza dough or pancakes, the peripheral circuit area was flattened (squeegeeed).

Reference is now made to Fig. 7, which is a block diagram of an exemplary floor plan 700 for a NAND flash chip fabricated in accordance with another exemplary embodiment. There are also three row decoders 710-712 shown in the illustrated exemplary embodiment, one for each plane labeled plane 0, plane 1 and plane 2. Similarly, the total number of word lines 720 is 3n (where n is the total number of word lines per plane), and thus the total number of word lines is a number not a power of two because the multiplication factor 3 This is because the number is not a power of 2. The main difference between the exemplary embodiment of FIG. 7 and the exemplary embodiment of FIG. 6 is the presence of three high voltage generator regions 750-752 versus two high voltage generator regions 650-651. Thus, there is an additional high voltage generator in the exemplary embodiment of FIG. 7 as compared to the exemplary embodiment of FIG. Because of this additional high voltage generator, those skilled in the art will appreciate that such a design is advantageous in that the higher performance benefit achieved with respect to memory device operation for other designs is greater than that measured with respect to the chip area including memory cells for the total chip area. Those skilled in the art will appreciate that the invention may be chosen for other designs with less voltage generators in certain cases, such as overcoming less efficient chip area utilization. For many applications, higher currents may be expected for both Vcc and Vpp in conjunction with the exemplary embodiment of FIG. 7; These higher currents are of great concern and should not be so large.

Different combinations of the number of planes and the number of high voltage generators are expected. For example, five planes and three, four or five high voltage generators, six planes and four, five or six high voltage generators.

It will be appreciated that in the course of going from a memory capacity device that is a power of two to a memory capacity device that is not a power of two with a higher capacity, an increase in address length by at least one bit is expected. In one embodiment, if a 24-bit address is used in a first memory device having a memory capacity that is a power of two, then for a second memory device having a memory capacity greater than the first device and not a power of two , The address would be expected to be at least 25 bits long.

With respect to a memory capacity device that is a power of two, it is theoretically possible for each and every logical address to correspond to a valid physical address (which is not possible, for example, because of the mapping out of a bad cell, for example). However, for a memory capacity device that is not a power of two, it is not. Because the logical address is binary, the total count of all possible logical addresses will be a number that is approximately a power of two. So, for example, for a capacitive memory device of 24 GB (not a power of 2), approximately 32 billion would be the total count of all possible logical addresses, which means that approximately 8 billion logical addresses correspond to valid physical addresses Will not be expected. Nevertheless, the mapping out of invalid physical addresses is processed on the controller side by the file / memory management submodule 330 shown in FIG. 3, in a manner similar to the mapping out of bad cells as understood by those skilled in the art .

It will be appreciated that the term "capacity" as used herein is a capacity other than non-data capacity or alternate capacity. In this regard, FIG. 8 is a block diagram of an exemplary plane 800 of a NAND flash chip, which is included in the figures to clarify the data capacity different from the non-data capacity (or alternate capacity). The illustrated exemplary plane 800 includes four sections: a data section 802, a spare field section 804, a redundant column (s) section 806, and a redundant block (s) section 808 In some embodiments, this plane may not have redundant column (s) section 806, or it may not have redundant block (s) section 808, Or there may be some other type of secondary section having a related purpose similar to the currently described secondary section). The spare field section 804 is a section of the plane 800 corresponding to the spare field of the memory page as described above. It will be appreciated that the spare field section 804 has an associated non-data capacity. The redundant column (s) section 806 includes a plane 800 corresponding to the redundant column (s) of the plane 800 that can serve as a replacement column for the column in the data section 802, ). It will be appreciated that the redundant column (s) section 806 has an associated replacement capacity. The redundant block (s) section 808 is a section of the plane 800 corresponding to the redundant block (s) providing a purpose similar to the redundant column (s) in the redundant column (s) It will be appreciated that the redundant block (s) section 808 has an associated replacement capacity. The remaining section is the data section 802. For a conventional NAND flash, the following holds: 1) the data section 802 has a capacity that is a power of 2; 2) The data field in the data section 802, which is part of the page except for the spare field, has a capacity that is a power of two.

Some exemplary embodiments described herein relate to non-volatile memory systems having a memory capacity other than a power of two, regardless of the particular application in which the non-volatile memory system may be used. Other exemplary embodiments described herein are directed to the use of non-volatile memory systems having memory capacities other than a power of two in a particular application, or to memory capacities typically used in certain large systems or products, To a non-volatile memory system having a non-power-of-two memory capacity of the non-volatile memory system.

Hereinafter, reference will be made to Fig. A block diagram of the communication arrangement between the memory device manufacturer and the customer company is shown. The customer company has a computer system 902 that communicates with a memory device manufacturer's computer system 906 via a communication network 908 (e.g., the Internet).

For a customer company computer system 902, these computer systems 902 include a network 912 and a plurality of client computers 916. The network 912 may include any suitable combination of LAN (Local Area Network), VPN (Virtual Private Network), server, data store (e.g., database) Each of the client computers 916 may include a personal computer, a mobile computing device, a smartphone, or other computer capable of transmitting and receiving communications, at least as facilitated by the network 912.

Similarly, for a memory device manufacturer's computer system 906, these computer systems 906 include a network 920 and a plurality of client computers 926. Network 920 may include any suitable combination of LAN (Local Area Network), VPN (Virtual Private Network), server, data store (e.g., database) Each of the client computers 926 may include a personal computer, a mobile computing device, a smart phone, or other computer capable of transmitting and receiving communications, at least as facilitated by the network 920.

In some embodiments, the manufacturer that drives the computer system 906 may be a memory chip, a memory system, or the like integrated into a large product that is manufactured, assembled, or produced by a customer company that drives the computer system 902 We are engaged in manufacturing business. In one embodiment, the customer company may purchase a flash memory chip from a manufacturer, which is then used in the production of a portable media player. In another embodiment, the customer company may purchase a flash memory chip from a manufacturer, which is then used in the production of a wireless enabled telephone.

In some embodiments, the hardware used to implement the computer systems 902, 906 and communication network 908 described above is conventional. However, in accordance with one exemplary embodiment, a novel ordering method of a memory device performed in the communication arrangement of FIG. 9 is provided. This method will be described in more detail in the description below of alternative communication arrangements.

Hereinafter, reference will be made to FIG. A block diagram of a communications arrangement between a customer and a company that sells memory products, such as, for example, a memory stick, a Secure Digital (SD) flash card, a solid state drive (SSD) Also, in some cases, the nonvolatile medium sold is a blank; In other cases, content for non-volatile media will be included. For example, the company may be selling non-volatile memory game cartridges, for example, or flash memory cards with pre-installed mobile device application (s). Sales of large products including memory products are also expected. For example, the company may sell, for example, an MP3 player with a flash card, a cell phone with a flash card, or a desktop / mobile computer with an SSD.

Still referring to FIG. 10, a customer has a client computer 1002 that communicates with a memory product company's computer system 1006 via a communications network 908 (e.g., the Internet). It is also understood that client computer 1002 may include a personal computer, a mobile computing device, a smartphone, or other computer capable of transmitting and receiving communications, such as facilitated by at least communication network 908 Will be.

For a memory product company computer system 1006, these computer systems 1006 include a network 1020 and a plurality of client computers 1026. Network 1020 may include any suitable combination of LAN (Local Area Network), VPN (Virtual Private Network), server, data store (e.g., database) Each of the client computers 1026 may include a personal computer, a mobile computing device, a smartphone, or other computer capable of transmitting and receiving communications, at least as facilitated by the network 1020. [

If the network 920 or 1020 includes a server, one of ordinary skill in the art will recognize that such a server can typically send and receive communications over the Internet. According to some exemplary embodiments, the server may receive data comprising information corresponding to an order for at least one item (as described in more detail below). In these exemplary embodiments, the server may also process the data and make it eligible for storage in the at least one data store. Those skilled in the art will understand how data needs to be adapted for storage. In only one simple embodiment, the data received at the server may include the portion (s) not stored in at least one data store. For example, the data may include one or more encryption portions present in the data to ensure security during transmission over the Internet. Such encryption portion (s) may be processed by the server.

It will be appreciated that variations to the communication arrangement other than the communication arrangement described with reference to Figures 9 and 10 are contemplated. For example, as a variant from that shown in FIG. 10, a person (client) may access a network 912 (see FIG. 9) from its home, 1002 may not be operated. Instead, a person may be using the computer in an office, an Internet cafe, or using a mobile computer in a WiFi hotspot in a public area such as an airplane. In such a situation, there may be a customer side network similar to the network 912.

Reference is now made to FIG. 11, which is a flow diagram of a method 1100 of ordering a memory device or memory product in accordance with some exemplary embodiments. The method 1100 is described from "start" to "end " below, taking into account that some variation from the illustrated operation is expected. For example, in some cases, some of these operations may occur in a different order than the illustrated order. It should also be understood that any reference to a "customer" in the following description can be broadly interpreted in a broad sense, for example, a customer company in the context of the embodiment corresponding to FIG. 9, or a person in the context of the embodiment corresponding to FIG. . Similarly, any reference to a "vendor" in the following description may be taken in a broad sense, for example, in the context of a memory device manufacturer in the context of the embodiment corresponding to FIG. 9, or in the context of the embodiment corresponding to FIG. 10 Is a term that includes memory products companies.

At operation 1104 shown immediately after the "start", the customer loads the application on the client computer 916 (see FIG. 9) or the client computer 1002 (see FIG. 10). In some embodiments, the application may be an Internet browser-based application (e.g., Microsoft's Internet Explorer®), but in other embodiments the application may include an application that does not require the loading of an Internet browser But may take some other form. Also, at operation 1104, communication is established between the client computer and the vendor's network. In one embodiment, in this regard, a form-based graphical user interface (GUI) configured from information stored on a vendor's network server may appear on the display of the customer's computer.

At operation 1108, a selection is made to the customer for the item the customer wishes to order, i.e., non-volatile memory device (s) or non-volatile memory product (s). According to some embodiments, this is achieved as an interactive, fillable form presented on a display screen.

Referring to FIG. 12, one possible fillable portion 1202 is shown on the display screen 1204. (It should be appreciated that fillable fill forms are typically provided for the input of at least several fill details, and that only a portion of the form for one fill detail is currently shown, but this is merely for convenience of illustration. )

Still referring to FIG. 12, from a request to "select the capacity of the memory device ", the customer needs to input details of what capacity the memory device (s) he / she wants the customer as part of the order It will be obvious. In the illustrated embodiment, the customer has five selections 1210a-1210e for the capacity of the memory device (s) desired by the customer. Selections 1210a and 1210e are capacities that are powers of two. Selections 1210b, 1210c, and 1210d are capacities that are not powers of two.

Referring now to FIG. 11, in operation 1112 in the illustrated ordering method, the customer enters the order for non-volatile memory device (s) or non-volatile memory product (s). In the illustrated exemplary GUI of FIG. 12, operation 1112 involves completing a fillable form. As part of this process, the customer can select and move the cursor 1220 over one of the radio buttons 1222a-1222e (each of which corresponds to each of the selections 1210a-1210e). The customer can then move the cursor 1220 to another portion of a form that can be filled in to enter additional details about the order. As described, fillable order forms are typically provided for the input of at least several order details. As a single embodiment of another possible ordering detail, the customer may be able to input the number of non-volatile memory device (s) or non-volatile memory product (s) the customer desires to order. In this regard, a company customer may be more likely to order a relatively large number of device (s) / product (s) while an individual customer may be more likely to order a relatively small number of device (s) / product (s) .

The input details in the embodiment of FIG. 12 are via radio buttons, but those skilled in the GUI design will recognize that various alternatives to radio buttons exist for inputting the same or similar details. Figure 13 shows one such alternative.

In Fig. 13, an alternative fillable portion 1302 is shown on the display screen 1204. Again, the customer needs to enter details of what capacity the memory device (s) the customer wants as part of the order. In the illustrated embodiment, the customer types the capacity in the text field 1310 at the cursor 1314. Optionally, the GUI may include interactive logic to verify that the details are being typed and that the input capacity is valid input (i. E., A memory device or devices matching the capacity required by the customer are available) . If the input capacity is not an effective input, for example, a notice such as a text of a few words near the text field 1310 may appear.

In addition to the differences described above, the embodiment of FIG. 13 may be similar to the embodiment of FIG. For example, after the customer completes entering the capacity details in the text field 1310, the customer then moves the cursor 1220 to another portion of a form that can be filled in to enter additional details about the order Can be moved.

Not all exemplary embodiments are limited to order entry through the GUI. In fact, it is expected that the customer may not need to look at the display screen at all. In at least one exemplary embodiment, a customer may place the order on a telephone of a type in which customer input is accepted via DTMF (Dual-Tone Multi-Frequency) signaling generated by using a touchtone keypad in response to a voice prompt Can be entered through a service-type application. In this exemplary embodiment, the details of the order will be entered after the successive voice prompts one by one. (This type of order is known to exist in other contexts, such as, for example, stock orders and home shopping orders.) Other alternative exemplary embodiments are also contemplated.

Hereinafter, reference will also be made to operation 1116, which is the following illustrative operation in Figure 11, particularly in the flow charts after operation 1112. In this operation, the customer enters payment information. In some embodiments, the customer may, for example, pay the credit card by entering the credit card number and expiration date into the field of the GUI. In another embodiment, the customer may pay by using some other form of payment, e. G. PayPal (TM). Alternative variations are expected. For example, a customer may not need to enter their credit card information if the vendor's computer system has some way of retrieving the credit card information through association with the customer's identity. See, for example, U.S. Patent No. 5,960,411 to Hartman et al. (The so-called "one-click" patent). As another embodiment, the customer may not pay at the time of purchase. For example, a customer may later invoice with an order to place a subsequent order within a one-hour period from the invoice date.

At act 1120, the information needed to complete the order has been obtained, and this order is then stored for later processing. In particular, the order will typically be stored in a suitable storage in the vendor's computer system. This suitable storage may take the form of a database on a computer readable medium; Other types of suitable storage may be possible as will be appreciated by those skilled in the art.

At act 1124, an acknowledgment of the order is sent to the customer. Typically, this confirmation will take the form of one or more electronic notifications (s) sent to the customer. Examples of electronic notification (s) include, for example, an e-mail message, a text message, a browser page displayable to the customer, and the like. 9 and 10, an electronic notification confirming receipt of an order may, in some cases, be sent immediately after transmission via the communication network 908, for immediate or last reception by each of the client computers 916 or 1002 Is generated by a server in the network 920 or 1020.

Reference is now made to Fig. 14, which is a block diagram of a communications arrangement that facilitates updating non-volatile memory media in accordance with some exemplary embodiments. 14, the computer 1402 may communicate with the remote computer system (s) 1404 via a communication network 1406 (e.g., the Internet). Alternatively, the computer 1402 may communicate with the remote computer system (s) 1404 via both the local network 1408 and the communication network 1406.

With respect to the computer 1402, the computer 1402 may be a personal computer, a mobile computing device, a mobile GPS (Global) device (whether in conjunction with one or more other communicatively coupled computers 1402 or separately) Positioning System devices, smart phones, mobile (handheld) gaming systems, non-mobile gaming systems, or other computers capable of sending and receiving communications as facilitated by at least the communications network 1406 have. The computer 1402 includes an interface device 1420 that allows the computer 1402 to communicatively interface with the memory product 1424. A non-exhaustive list of exemplary possible interface devices includes Universal Serial Bus (USB) ports, flash card readers, cartridge readers, Ethernet ports, Wi-fi transceivers, and the like, or any suitable combination thereof. Examples of memory products 1424 include non-volatile memory sticks, flash cards, non-volatile memory game cartridges, private non-volatile memory devices, solid state drives (SSDs), and the like.

The illustrated memory product 1424 includes at least one non-volatile memory chip 1430 having a capacity that is not a power of two. According to some exemplary embodiments, a substantial amount of files (data and / or computer-readable instructions) that occupy rather than all of the capacity of memory chip 1430 are pre-installed on memory chip 1430 May be stored on the memory chip 1430 at or prior to the sale of the memory product 1424 to the product user or may be stored on the memory chip 1430 at some point during the manufacturing, ). ≪ / RTI > Typically, files stored on memory chip 1430 will include software code. In one embodiment discussed below as a first embodiment, when the computer 1402 includes a mobile GPS device, a GPS application and / or a load map may be stored on the memory chip 1430. [ As another embodiment described below as a second embodiment, when the computer 1402 includes a gaming system, a video game may be stored on the memory chip 1430. [ Other similar embodiments are also contemplated.

With respect to the exemplary embodiment still described above, it is also convenient for a user of memory product 1424 to provide a remote computer (not shown) for storage on one or more non-volatile memory chips of non-volatile memory chip 1430 having a non- It may be improved by using the computer 1402 to download additional file (s) from the system (s). Again with respect to the first embodiment, the additional file (s) may be, for example, an additional load map. For the second embodiment, the additional file (s) may be an additional level, for example in a video game. Also, in accordance with at least one exemplary embodiment, it is possible that one or both of the additional file (s) may be stored on the same memory chip 1430 storing pre-installed files, This is because the installed file does not occupy the entire capacity of the memory chip 1430. Additionally, in various cases, the memory chip 1430 may be sized to be flexible because the memory chip 1430 is sized to be flexible in that the memory chip 1430 need not be selected from memory chips having a capacity that is a power of two. The creators of the files and applications stored on the memory chip are expected to be less restrictive about trying to optimize the size of applications and files for capacitive memory chips that are powers of two.

Certain adaptations and modifications of the described embodiments can be made. Therefore, the above-described embodiments are considered to be illustrative rather than restrictive.

Claims (10)

CLAIMS What is claimed is: 1. A method of populating a memory controller table with data,
Wherein the memory controller table is stored in a random access memory of a memory controller and the memory controller is in communication with a memory chip having at least one memory cell array for storing the data for management functions of the memory controller,
The method of populating the memory controller table with data comprises:
Extracting the data from the at least one memory cell array of the memory chip having a capacity other than a power of two;
Processing the data in the memory controller to determine invalid physical addresses resulting from a non-power of two of the at least one memory cell array of the memory chip; And
And modifying the memory controller table to map out the invalid physical addresses. The method according to claim 1,
Wherein the at least one memory cell array of the memory chip is more than two memory cell arrays,
Wherein the number greater than two is a non-power of two number. The method according to claim 1,
Further comprising modifying the memory controller table to map out bad memory cells. The method according to claim 1,
Wherein the data is fetched from spare fields of pages of the at least one memory cell array of the memory chip. 1. A network capable of transmitting and receiving communications transmitted over the Internet,
At least one server; And
At least one data store in communication with the at least one server,
Wherein the at least one server is configured to: i) receive data comprising information corresponding to an order for at least one item comprising at least one non-volatile memory chip having a capacity that is not a power of two; Ii) processing said data to make said data suitable for storage in said at least one data store; Iii) generate an electronic notification suitable for transmission over the Internet to provide a confirmation of receipt of the order to the customer. 6. The method of claim 5,
Wherein the at least one server is a server of a memory device manufacturer. 6. The method of claim 5,
Wherein the electronic notification is e-mail. 6. The method of claim 5,
Wherein the customer is a corporate entity. 6. The method of claim 5,
Wherein the at least one non-volatile memory chip has a number of row decoders that is not a power of two. 6. The method of claim 5,
Wherein the at least one non-volatile memory chip has a number of planes other than a power of two.

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