KR20150020023A - Refresh method for flash memory and related memory controller thereof - Google Patents

Refresh method for flash memory and related memory controller thereof Download PDF

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KR20150020023A
KR20150020023A KR20140041013A KR20140041013A KR20150020023A KR 20150020023 A KR20150020023 A KR 20150020023A KR 20140041013 A KR20140041013 A KR 20140041013A KR 20140041013 A KR20140041013 A KR 20140041013A KR 20150020023 A KR20150020023 A KR 20150020023A
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storage space
flash memory
input data
reproducing
threshold voltage
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KR20140041013A
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Korean (ko)
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KR101653293B1 (en
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충-치에 양
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실리콘 모션 인코포레이티드
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Abstract

A refresh method for a flash memory includes at least the following steps: performing a write operation to store input data in a storage space in the flash memory; checking reliability of the storage space with the input data stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data in the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space at original storage locations in the storage space.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flash memory,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data management stored in a flash memory, and more particularly, to a flash memory reproduction method and a memory controller therefor.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device according to operating characteristics. Volatile memory devices perform write / read operations at high speed, but lose stored data when there is no power supply. On the other hand, a non-volatile memory device can retain stored data even when there is no power supply. The so-called 'flash memory' is a kind of nonvolatile memory that provides a high memory cell density. Accordingly, the flash memory can be employed as a data storage medium such as a solid-state drive (SSD).

With the development of flash memory, one memory cell can store one or more data bits. However, programming of flash memory cells, each of which can thus store multiple data bits, requires precise control of the threshold voltage distribution corresponding to the differently programmed data values, respectively. Specifically, as the degree of integration of the flash memory increases, the minimum feature size of the memory cell constituting the flash memory must be reduced. At the same time, the coupling effect between the floating gates of the constituent memory cells may increase, which may compromise the reliability of the flash memory.

Also, because of the increased integration of the flash memory, the size of the floating gate becomes smaller, so data maintenance failure is an important issue to solve. In one conventional design, a complex soft decoding algorithm is used to recover data stored in a block through multiple read operations if data retention failures occur within the block after the data has been stored in the block. After the stored data has been successfully restored, a replacement block found in the flash memory is selected and programmed to store the restored data, and the previous block is deleted and becomes an empty block. However, since the conventional data retention method increases the number of program / erase (P / E) cycles, the life of the flash memory is inevitably shortened.

A method of reproducing a flash memory and a memory controller therefor according to an embodiment of the present invention are disclosed.

According to a first aspect of the present invention, an example of a method of reproducing a flash memory is introduced. An example of a method of reproducing a flash memory includes at least the following steps: performing a write operation to store input data in a storage space in a flash memory; Checking reliability of the storage space in which the input data is stored; And performing a refresh operation on the storage space based on the input data if the reliability of the storage space satisfies a predetermined criterion.

In one embodiment, the step of checking the reliability of the storage space includes detecting whether there is a data-retention disturbance in the storage space in which the input data is stored.

In one embodiment, the storage space is comprised of a plurality of N-bit multi-level cells, where N is a positive value greater than two.

In one embodiment, the writing operation stores the input data in the storage space through an initial program operation and at least one reprogram operation following the initial program operation, Is an additional reprogram operation that is applied to the storage space to program the input data recovered from space to the original storage location in the storage space.

In one embodiment, the input data stored in the storage space by the recording operation is read based on a reference threshold voltage value of a first initial setting, and the input data, which is stored in the storage space by the reproducing operation, Wherein the reference voltage value is read out on the basis of a reference voltage value of a second initial setting different from a reference voltage value of the first initial setting and the highest reference voltage value determined based on the reference voltage value of the second initial setting, 1 is greater than the highest reference threshold voltage determined at the reference threshold voltage value of the initial setting. The reproducing method of the present flash memory further includes storing an indicator indicating a reference threshold voltage value of the second initial setting after performing the reproducing operation on the storage space.

In one exemplary design, the storage space is part of a block of the flash memory. The reproducing method of the present flash memory further includes performing a reproducing operation on the remaining portion of the block of the flash memory if the reliability of the storage space satisfies the predetermined criterion.

According to a second aspect of the present invention, an example of a memory controller of a flash memory is introduced. An example of a memory controller includes a recording circuit, a checking circuit and a reproducing circuit. The write circuit is coupled to the flash memory and is configured to store the input data in a storage space within the flash memory. The checking circuit is configured to check the reliability of the storage space in which the input data is stored. A reproducing circuit is coupled to the inspection circuit and the flash memory and is configured to reproduce the storage space based on the input data if the reliability of the storage space meets a predetermined criterion.

In one embodiment, the checking circuit checks the reliability of the storage space by sensing whether there is a data maintenance failure in the storage space in which the input data is stored.

In one embodiment, the storage space accessed by the memory controller is comprised of a plurality of N-bit multi-level cells, where N is a positive value greater than two.

In one embodiment, the recording circuit stores the input data in the storage space through an initial program operation and at least one reprogram operation following the initial program operation, and the playback circuit restores the input data from the storage space And performs an additional reprogram operation with respect to the storage space to program the input data to an original storage location in the storage space.

In one embodiment, the input data stored in the storage space by the recording circuit is read based on a reference threshold voltage value of a first initial setting, and the reproduction circuit stores the input data stored in the storage space And a second initial threshold voltage value that is different from a reference threshold voltage value of the first initial setting and is read based on the reference voltage value of the second initial setting, Is greater than the highest reference threshold voltage value determined at the reference threshold voltage value of the first initial setting. Also, after reproducing the storage space, the reproducing circuit stores an indicator indicating a reference threshold voltage value of a second initial setting.

In one embodiment, the storage space accessed by the memory controller is part of a block of the flash memory. The reproducing circuit is further configured to reproduce the remaining portion of the block of the flash memory if the reliability of the storage space meets the predetermined criterion.

Various objects of the present invention will become apparent to those skilled in the art after reading the detailed description of the preferred embodiments described in the various drawings and the drawings.

1 is a diagram illustrating a flash memory device according to an embodiment of the present invention.
2 is a diagram showing the threshold voltage distribution of a memory cell after the execution of the first program operation (i.e., the initial program operation).
Fig. 3 is a diagram showing the threshold voltage distribution of the memory cell after the execution of the second program operation (i.e., the first reprogramming operation).
4 is a diagram showing the threshold voltage distribution of the memory cell after the execution of the third program operation (i.e., the second reprogramming operation).
5 is a diagram showing threshold voltage distribution of a memory cell when a data maintenance failure occurs.
6 is a diagram showing the threshold voltage distribution of the memory cell after the reproducing operation is performed.
Fig. 7 is a diagram showing an example of the first list L1 and the second list L2 recorded by the inspection circuit.
Fig. 8 is a diagram showing an example of an updated first list L1 and an updated second list L2, which are recorded by an inspection circuit.

Certain terms are used throughout the description and the claims that follow to indicate a particular component. Manufacturers may refer to components by other designations and will be appreciated by those skilled in the art. This specification has been written to distinguish components by their functional differences rather than by designations. In the following detailed description and the claims, the terms 'comprise' and 'comprise' are used in a non-limiting fashion and should be interpreted to mean 'including, but not limited to'. In addition, the term 'couple' is used to mean an indirect or direct electrical connection. Thus, when one device is coupled to another device, it may be a direct electrical connection or a connection via another device and an indirect electrical connection through the connection.

The present invention solves the problem of data maintenance failure without increasing the number of program / erase (P / E) cycles by performing a replay operation that reprograms the data to the original storage location in the flash memory. Further, the data retention method to be proposed is described in detail below.

1, which is a diagram illustrating a flash memory device according to an embodiment of the present invention. A flash memory device 100 includes a memory controller 102 and a flash memory 104. The memory controller 102 is coupled to the flash memory 104 and is arranged in control accesses (i.e., write and read) of the flash memory 104. The memory controller 102 includes a write circuit 112, a check circuit 114, a refresh circuit 116, and other circuitry 118, The other circuit 118 may include a read circuit, an erase circuit, an error checking and correcting circuit (ECC circuit), and the like. The write circuit 112 is coupled to the flash memory 104 and is configured to store the input data D_IN in a storage space within the flash memory 104 and the storage space is located within a single page memory cell or word line Memory cells, and the like. The checking circuit 114 is configured to check the reliability of the storage space in which the input data D_IN is stored. The reproduction circuit 116 is coupled to the inspection circuit 114 and the flash memory 104 and is configured to reproduce the storage space based on the input data D_IN when the reliability of the storage space meets predetermined criteria. The operation of the recording circuit 112, the checking circuit 114 and the reproducing circuit 116 will be described later in detail. Since the present invention focuses on the playback scheme applied to the flash memory 104, details of the erase operation, the read operation, and the ECC decoding operation performed by the circuit components included in the other circuit 118 are described in detail Are omitted herein for brevity. In addition, the recording circuit 112, the checking circuit 114, the reproducing circuit 116, and other circuitry 118 may be designed with a circuit that executes a particular software or firmware code, and at least two of the circuits The same hardware that performs different operations under the control of the corresponding software or firmware can be shared.

With respect to the flash memory 104, this includes a plurality of blocks BK 0 , BK 1 , ..., , BK M , and M may be any positive value depending on the actual design requirements. Each block has a different word line WL 0 , WL 1 , WL 2 , ... And a plurality of memory cells 122 located at WL L , where L may be any positive value according to actual design requirements. For example, L = 86. The memory cell 122 located in each word line belongs to the K page, and K can be any positive value according to the actual design requirements. For example, K = 3.

With respect to the data access of the flash memory 104, a page-based read operation can be performed on the flash memory 104 to read the stored data from the memory cell 122 included in the designed page, A page-based write operation may be performed on the flash memory 104 to program the data stored in the memory cell 122 and the data stored in all the memory cells 122 included in the designed block A block-based erase operation can be performed on the memory 104. [ In this embodiment, each memory cell 122 may be an N-bit multi-level cell, where N is a positive value greater than two. For example, each memory cell 122 may be a 3-bit multi-level cell (known as a TLC (Triple-Level Cell)).

The coupling effect between the floating gates of adjacent memory cells may cause shifting and / or expansion of the threshold voltage distribution. Such shifting and / or expansion of the threshold voltage distribution worsens the read margin, and thus a read data error occurs. In order to mitigate the shifting and / or expansion of the threshold voltage distribution resulting from the coupling effect between the floating gates of adjacent memory cells, the write circuit 112 includes an initial program operation and at least one reprogram following the initial program operation reprogram operation to perform a write operation.

If the flash memory 104 is a TLC flash memory, each memory cell 122 will be programmed to have one of eight states for storing three bits of data. When the writing circuit 112 writes the input data D_IN in the storage space of the flash memory 104 (for example, the memory cell 122 in the word line WL 0 of the block BK 0 ) Lt; RTI ID = 0.0 > 122 < / RTI > 2 is a diagram showing the threshold voltage distribution of a memory cell after the execution of the first program operation (i.e., the initial program operation). For each memory cell 122, an initial program operation causes the memory cell 122 to be programmed to a 3-bit data-based target state to be stored. As shown in FIG. 2, reference threshold voltage 0 and V TH1 -V TH6 are used to distinguish between different states. Even if the initial program operation is performed, it is difficult to clearly distinguish between the different states due to the disturbed threshold voltage distribution due to the coupling effect between the floating gates of adjacent memory cells. More specifically, there is an ambiguous data value area (indicated by an oblique line). Thus, the first reprogramming operation is performed. Fig. 3 is a diagram showing the threshold voltage distribution of the memory cell after the execution of the second program operation (i.e., the first reprogramming operation). The first reprogramming operation is used to improve the threshold voltage distribution resulting from the initial program operation. As can be seen from Figure 3, the size of the ambiguous data region is reduced because the second programming operation (i.e., the first reprogramming operation) makes the threshold voltage distribution for different states more apparent. However, there still exists the possibility of erroneously reading the programmed memory cell with the threshold voltage of the ambiguous data value region. Thus, the second reprogramming operation is performed. 4 is a diagram showing the threshold voltage distribution of the memory cell after the execution of the third program operation (i.e., the second reprogramming operation). As can be seen from FIG. 4, when the second reprogramming operation is performed, each threshold voltage distribution for different states can all be reliably distinguished.

The reprogram based method applied by the write circuitry 112 may be performed within a desired range to enable a threshold voltage distribution to be narrower and a read operation to follow to accurately distinguish between the different states held by the programmed memory cell Obviously, a data retention fault in the programmed memory cell 122 may still occur. When a data maintenance failure occurs, the threshold voltage distribution for different states can be shifted down while expanding into a bell shape. 5 is a diagram showing threshold voltage distribution of a memory cell when a data maintenance failure occurs. As the threshold voltage distribution changes due to the data maintenance failure, it may be that the data error is read using the initial reference threshold voltage. That is, when the reliability of the storage space where the input data D_IN is stored (for example, the memory cell 122 in the word line WL 0 of the block BK 0 ) is lowered, the memory controller 102 It may be difficult to accurately read the stored data from the storage space. In this embodiment, the checking circuit 114 checks the reliability of the storage space in which the input data is stored, and when the reliability of the storage space meets a predetermined criterion, the reproducing circuit 116 determines, based on the input data D_IN, Lt; / RTI > For example, the inspection circuit 114 detects whether or not there is a data maintenance failure in the storage space in which the input data D_IN is stored, and when the occurrence of the data maintenance failure is detected, the determination circuit 114 determines that the reliability of the storage space . In one embodiment of the design, the test circuitry 114 may indicate information provided by the ECC circuitry included in other circuitry 118 that determines whether a data retention fault has occurred. For example, when an ECC circuit fails to decode or applies a decoding operation (e.g., hard decoding operation or soft decoding) on the stored data read from the storage space in the flash memory 104, The checking circuit 114 determines that there is a data maintenance failure in the memory cell 122 in the storage space. Restoration data holding of the reproduction based may enable restoring the data stored in the storage space (e.g., the word line WL of the block BK 0 0). For example, a complex decoding algorithm (e. G., A soft decoding algorithm) is executed by the ECC circuit so that the stored data is recovered through a plurality of read operations.

In general, a TLC block may require three SLC blocks to buffer the recovered data of a TLC block. In one embodiment of the design, the memory controller 102 may store the restored data of one TLC block in three SLC blocks allocated in the flash memory. In an alternative embodiment of the design, the reconstructed data of one TLC block may be stored in the internal buffer of the memory controller 102.

Stored data (that is, the input data D_IN) is after the successfully restored from the storage space in the data holding impaired, the reproduction circuit 116 is storage (e.g., memory cells in the word line WL 0 of block BK 0 (122 ) From the test circuit 114 to perform a reproducing operation. In this embodiment, since the recording circuit 112 uses the reprogrammable method for recording the input data D_IN in the storage space of the flash memory 104, the reproducing operation performed by the reproducing circuit 116 is performed by the recording Is an additional reprogram operation that is applied to the storage space to write the input data D_IN restored from space to the original storage location in the storage space. Thus, the threshold voltage distribution shown in FIG. 54 is improved by an additional reprogram operation performed by the regeneration circuit 116. 6 is a diagram showing the threshold voltage distribution of the memory cell after the reproducing operation is performed. In a preferred embodiment, the regeneration circuit 116 is configured to indicate the input data D_IN restored from the storage space to write the memory cell 122 located at the original storage location in the storage space to a higher threshold value, As the noise margin improves, the threshold voltage distribution becomes elaborate. In other words, the input data D_IN stored in the storage space by the recording circuit 112 is read based on the reference threshold voltage value of the first initial setting (i.e., 0 and V TH1 -V TH6 shown in FIG. 4) The input data stored in the storage space by the circuit 116 is compared with a reference threshold voltage value of a second initial setting (i.e., 0 and V TH1 '-V TH6 shown in FIG. 6) different from the reference threshold voltage value of the first initial setting '). In addition, the highest reference threshold voltage value (i.e., V TH6 ') determined from the reference threshold voltage value of the second initial setting is the highest reference threshold voltage value (i.e., V TH6 ).

As described above, the reference threshold voltage values (i.e., 0 and V TH1 '-V TH6 ') of the second initial setting are the reference threshold voltage values of the first initial setting after the completion of the reproducing operation (i.e., 0 and V TH1 - V TH6 ). Thus, to facilitate subsequent read operations, the regeneration circuit 116 is configured to further store an indicator IT that indicates a reference threshold voltage value of a second initialization. In this way, the read circuit included in the other circuit 118 uses the correct reference threshold voltage value 0, V TH1 '-V TH6 ' to perform a read operation on the storage space reproduced by the reproduction circuit 116 Indicator IT can be instructed to do so. The indicator IT indicating the reference threshold voltage value of the second initialization may be stored in a correspondence table in the memory controller 102. [

Since the data of the same block can be stored sequentially (e.g., storage during short time intervals), the playback operation proposed herein may be a block-based operation. For example, if the data stored in one of the word lines in the block is found to have been affected by a data retention failure, then all of the blocks may be recovered by the recovery circuit 116. For example, the test circuit 114, when the memory cell 122 in the word line WL 0 of block BK 0 found that data retention fault, recovery circuit 116 is all of the word lines of the same block BK 0 WL 0 -WL L can be played. Preferably, for better threshold voltage distribution improvement, the word line reproduction order of the block follows the data writing order to the word line of the block. For example, the write circuit 112, a case using the method re-program the data is recorded to the word line WL 0 -WL L of the block BK 0 in sequence, the reproduction circuit 116 has a word line WL of the block BK 0 0 - And sequentially applies the reproducing operation to WL L.

In a preferred embodiment, playback-based data retention is performed without interference in the general data access environment of flash memory 104. [ For example, the test circuit 114 may be configured to detect the occurrence of a data maintenance failure in at least one of the blocks BK 0 -BK M each time the flash memory device 100 is activated, The read circuit and the ECC circuit. The checking circuit 114 may maintain the first list L1 and the second list L2 while the first list L1 is recorded by the recording circuit 112 but in ascending order of recording or in descending order of recording The second list L2 records index values that are not reproduced by the reproduction circuit 116 and the second list L2 is a list of indexes reproduced by the reproduction circuit 116 in ascending order of reproduction or in descending order of reproduction Record the value. 7 is a diagram showing an example of the first list L1 and the second list L2 recorded by the checking circuit 114. In FIG. A first list (L1) of an example is and recorded as an index value of '3', '1' and '2' in order, which is the data in the block BK 3 before recording the data write circuit 112 in the block BK 1 And the recording circuit 112 records the data in the block BK 1 before writing the data in the block BK 2 . The second list L2 of the example records the index values '0' and '4' in order, which means that the playback circuit 116 reproduces the block BK 0 before playing the block BK 4 . With the aid of the first list L1, the checking circuit 114 determines that the block BK 3 stores data at the earliest recording time and thus has the highest probability of data maintenance failure among the blocks BK 1 , BK 2 , BK 3 . Similarly, with the aid of the second list L2, the checking circuit 114 determines that the block BK 0 stores the data at the earliest playback point and thus has the highest probability of causing a data maintenance failure among the blocks BK 0 and BK 4 . When the flash device 100 is activated, the checking circuit 114 reads the stored data (for example, data of one word line) from the block BK 3 and performs a hard decoding operation on the data read from the block BK 3 Instructs the read circuit and the ECC circuit included in the other circuit 118 to execute. In addition, when the flash device 100 is activated (or at some other predetermined time, or when the memory controller 102 is idle), the checking circuit 114 may compare the stored data (e.g., (The data of the word line) from block BK 0 and perform a hard decoding operation on the data read from block BK 0 , in addition to the read circuit and the ECC circuit included in the other circuit 118. If there is a decoding error in the hard decoding of the data read from BK 3 , BK 3 is activated to perform the above-described playback operation on BK 3 . When it to the hard decoding of the read data from BK 0 coming from the decoding error, it does no longer keep the data restore is not applicable to the BK 0. When the above-described reproducing operation performed on BK 3, corresponding to the first list (L1) and the second list (L2) by the test circuit 114 is updated. Figure 8 is a diagram illustrating an example of an updated first list L1 and an updated second list L2, which are recorded by the checking circuit 114. [ As shown in FIG. 8, the updated first list L1 now records the indicator values '1' and '2' in order, and the updated second list L2 now stores the indicator values '0' 4 'and' 3 'are recorded in order. Accordingly, when the flash device 100 is in operation after the, (block BK 1 and BK are two probability failure held in the data is the highest as indicated by the first list (L1)) block BK 1, and (block BK 0 , The data stored in block BK 0 (indicated by the second list L2 as having the highest probability of occurrence of a data maintenance failure among BK 4 and BK 3 ) will be examined.

Assume that there is a decoding error in the hard decoding of the data read from the block BK 0 (indicated by the second list L2) that has the highest probability of occurrence of data retention failure among all the reproduced blocks. In one example of a design, the playback circuit 116 may be activated to perform a playback operation again for block BK 0 . In another example of the design, a conventional data retention recovery scheme may be activated in which data recovered from block BK 0 is programmed into a replacement block and block BK 0 is deleted.

Compared with the conventional data retention method for erasing a block having a data retention failure, the proposed data retention method of the present invention reproduces a block instead of deleting the block. By doing this, the number of P / E cycles in the flash memory 104 does not increase. Also, compared with the conventional data retention method for transferring data of a block having a data retention failure to another block, the proposed data retention method of the present invention reproduces a block without moving any data. Therefore, it is not necessary to update a logical-to-physical address mapping table, and a table that maps a logical address to a physical address can be used in page mode or block mode. More specifically, when a table that maps logical addresses to physical addresses is used in page mode, a table that maps logical addresses to physical addresses is quoted to translate logical pages into physical pages. When a table mapping a logical address to a physical address is used in block mode, a table that maps the logical address to a physical address is quoted to convert the logical block to a physical block.

It will be readily apparent to those skilled in the art that various changes and modifications can be made to the apparatus and method while maintaining the gist of the present invention. Accordingly, the foregoing should be interpreted only as being limited to the limits and boundaries of the appended claims.

Claims (20)

Performing a write operation to store input data in a storage space in the flash memory;
Checking reliability of the storage space in which the input data is stored; And
Performing a refresh operation on the storage space based on the input data if the reliability of the storage space satisfies a predetermined criterion
And reproducing the flash memory. The method according to claim 1,
The step of checking the reliability of the storage space
And detecting whether there is a data-retention disturbance in the storage space in which the input data is stored.
A method of reproducing a flash memory. The method according to claim 1,
Wherein the storage space is comprised of a plurality of N-bit multi-level cells, and wherein N is a positive value greater than two,
A method of reproducing a flash memory. The method according to claim 1,
Wherein the recording operation stores the input data in the storage space through an initial program operation and at least one reprogram operation following the initial program operation,
A method of reproducing a flash memory. 5. The method of claim 4,
Wherein the reproducing operation is an additional reprogramming operation applied to the storage space to program the input data recovered from the storage space to an original storage location in the storage space,
A method of reproducing a flash memory. The method according to claim 1,
The input data stored in the storage space by the recording operation is read based on a reference threshold voltage value of a first initial setting,
Wherein the input data stored in the storage space is read out based on a reference threshold voltage value of a second initial setting different from the reference threshold voltage value of the first initial setting by the reproducing operation,
A method of reproducing a flash memory. The method according to claim 6,
Wherein the highest reference threshold voltage value determined at the reference threshold voltage value of the second initial setting is greater than the highest reference threshold voltage value set at the reference threshold voltage value of the first initial setting,
A method of reproducing a flash memory. The method according to claim 6,
Further comprising the step of storing an indicator indicating a reference threshold voltage value of the second initial setting after performing the reproducing operation on the storage space
A method of reproducing a flash memory. The method according to claim 1,
Wherein the storage space is part of a block of the flash memory,
A method of reproducing a flash memory. 10. The method of claim 9,
And if the reliability of the storage space meets the predetermined criterion, performing a reproducing operation on the remaining portion of the block of the flash memory
A method of reproducing a flash memory. A write circuit coupled to the flash memory and configured to store input data in a storage space in the flash memory;
An inspection circuit configured to check reliability of the storage space in which the input data is stored; And
A playback circuit coupled to the test circuit and the flash memory and configured to play back the storage space based on the input data if the reliability of the storage space meets a predetermined criterion,
Wherein the flash memory is a flash memory. 12. The method of claim 11,
Wherein the checking circuit checks the reliability of the storage space by sensing whether there is a data-retention disturbance in the storage space in which the input data is stored,
Memory controller in flash memory. 12. The method of claim 11,
Wherein the storage space accessed by the memory controller is comprised of a plurality of N-bit multi-level cells, and wherein N is a positive value greater than two,
Memory controller in flash memory. 12. The method of claim 11,
Wherein the recording circuit stores the input data in the storage space through at least one reprogram operation following the initial program operation and the initial program operation,
Memory controller in flash memory. 15. The method of claim 14,
Wherein the playback circuit performs an additional reprogramming operation on the storage space to program the input data recovered from the storage space to an original storage location in the storage space.
Memory controller in flash memory. 12. The method of claim 11,
The input data stored in the storage space by the recording circuit is read based on a reference threshold voltage value of a first initial setting,
Wherein the reproducing circuit reads the input data stored in the storage space based on a reference voltage value of a second initial setting different from the reference voltage value of the first initial setting,
Memory controller in flash memory. 17. The method of claim 16,
Wherein the highest reference threshold voltage value determined at the reference threshold voltage value of the second initial setting is greater than the highest reference threshold voltage value set at the reference threshold voltage value of the first initial setting,
Memory controller in flash memory. 17. The method of claim 16,
Wherein the reproducing circuit stores an indicator indicating a reference threshold voltage value of a second initial setting after reproducing the storage space,
Memory controller in flash memory. 12. The method of claim 11,
Wherein the storage space accessed by the memory controller is part of a block of the flash memory,
Memory controller in flash memory. 20. The method of claim 19,
Wherein the playback circuit is further configured to play the remaining portion of the block of the flash memory if the reliability of the storage space meets the predetermined criteria,
Memory controller in flash memory.
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