KR20150017647A - Multi channel memory device having channel independently power nets - Google Patents

Abstract

A multi-channel memory device having an efficient power supply structure is disclosed. Such a multi-channel memory device includes at least a first channel memory and a second channel memory which are accessed independently from each other in the same chip. Also, the multi-channel memory device includes a decoupling unit operatively separating the first and second external power channel connection lines of the first and second channel memories in response to a decoupling driving signal, And a switching controller for applying the decoupling driving signal to the decoupling unit in response to a channel power control signal so that external power sources independently applied to the plurality of channels are used in corresponding channels. Since the power supply network is independently configured for each channel, independent operation is assured for each channel, and interference between power supply noise between channels is eliminated or minimized.

Description

[0001] The present invention relates to a multi-channel memory device having a channel independent power supply structure,

The present invention relates to semiconductor memory devices, and more particularly, to a multi-channel memory device having channel memories that are accessed independently from each other within the same chip.

The processing system may employ a multi-channel memory device that operates independently on different channels in a single chip.

A multi-channel memory device that can be configured with volatile memory, such as a DRAM (DRAM), may have more than one channel memory. Each of the channel memories is connected to a corresponding processor so that data read and data write operations can be performed independently.

It is necessary that the external power supply and the internal power supply be more efficiently supplied to the plurality of channel memories in the multi-channel memory device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-channel memory device having a channel independent power supply structure and a power supply network control method therefor.

According to an aspect of the concept of the present invention to achieve the above object,

A first channel memory and a second channel memory that are accessed independently from each other in the same chip;

A decoupling unit operatively separating the first and second external power channel connection lines of the first and second channel memories in response to a decoupling driving signal; And

And a switching controller for applying the decoupling driving signal to the decoupling unit in response to a channel power control signal so that external power sources independently applied to the first and second channel memories are used in corresponding channels do.

According to a conceptual embodiment of the present invention, the first and second channel memories may comprise DRAM cells or MRAM cells.

According to the conceptual embodiment of the present invention, the first and second external power channel connection lines may be connected to each other when the external power sources are applied.

According to the conceptual embodiment of the present invention, the first and second external power channel connection lines may be separated from each other when the external power sources are applied.

According to the conceptual embodiment of the present invention, the decoupling unit may short-circuit the DC component of the external power supply and open the AC component of the external power supply in the decoupling operation.

According to a conceptual embodiment of the present invention, the decoupling unit may be an RC filter or a transmission gate.

According to another aspect of the inventive concept for achieving the above object, a multi-channel memory device includes:

A first channel memory and a second channel memory that are accessed independently from each other in the same chip;

First and second internal power generators for applying first and second internal power supplies independent of each other to the corresponding first and second channel memories;

A decoupling unit operatively separating the first and second internal power channel connection lines of the first and second channel memories in response to a decoupling driving signal; And

And a switching control unit for applying the decoupling driving signal to the decoupling unit in response to a channel power control signal so that the first and second internal power supplies are used in corresponding channels.

According to a conceptual embodiment of the present invention, each of the first and second internal power generation units generates at least one of an internal power supply voltage, a high power supply voltage higher than the internal power supply voltage, and a substrate power supply voltage lower than the internal power supply voltage .

According to a conceptual embodiment of the present invention, the first and second channel memories may include a DRAM cell consisting of one access transistor and one storage capacitor.

According to the conceptual embodiment of the present invention, when the first and second internal power supply channel connection lines are connected to each other, one power supply network is formed in the first and second channel memories as a whole, When the power channel connection lines are separated from each other, the first and second channel memories may have independent power supply networks.

According to the conceptual embodiment of the present invention, the first and second channel memories may have different storage capacities.

According to the conceptual embodiment of the present invention, the decoupling unit may cause the DC components of the first and second internal power supplies to be short-circuited and the AC component of the external power supply to be open during the decoupling operation.

According to a conceptual embodiment of the present invention, the decoupling section may be a MOS transistor.

According to a conceptual embodiment of the present invention, the multi-channel memory device may be mounted on a mobile device.

According to a conceptual embodiment of the present invention, the channel power control signal may be provided as a mode register set signal upon power up of the multi-channel memory device.

According to still another aspect of the concept of the present invention to achieve the above technical object,

A power supply network control method in a multi-channel memory device having a first channel memory and a second channel memory that are accessed independently of each other in the same chip,

First and second internal power supplies or external power supplies independent of each other are applied to the corresponding first and second channel memories;

When the decoupling request signal is generated, the first and second internal power supply networks of the first and second channel memories or the first and second external power supply networks are operatively separated from each other.

According to an exemplary embodiment of the present invention, since the power supply network is independently configured for each channel, independent operation is assured for each channel and interference between power supply noise between channels is eliminated or minimized. It is also possible to implement one power supply network over the entire channel as required.

1 is a block diagram of a multi-channel memory device in accordance with the concepts of the present invention;
Figure 2 is a block diagram of the device of the first embodiment according to Figure 1;
3 is a block diagram of a device according to a second embodiment according to Fig.
4 is a block diagram of a device according to a third embodiment according to Fig.
FIG. 5 is an exemplary implementation of the decoupling unit of FIG. 1. FIG.
FIG. 6 is another embodiment of the decoupling unit in FIG. 1; FIG.
Fig. 7 is an equivalent circuit diagram of Fig. 5 or Fig. 6; Fig.
8 is a circuit block diagram of the channel memory of FIG.
9A to 9D are diagrams illustrating applications of the present invention applied to a memory system having various interfaces.
10 shows an application of the invention applied to a memory system stacked via a TSV;
11 is a diagram showing an application example of the present invention applied to an electronic system.
12 is a block diagram illustrating an application of the invention applied to a computing device;
13 is a block diagram illustrating an application example of the present invention applied to a smartphone;
14 is a block diagram illustrating an application example of the present invention applied to a mobile device.
15 is a block diagram showing an application example of the present invention applied to an optical I / O schema;
16 is a block diagram showing an application example of the present invention applied to a portable multimedia device;
17 is a block diagram showing an application example of the present invention applied to a personal computer.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent from the following description of preferred embodiments with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, without intention other than to provide an understanding of the present invention.

In this specification, when it is mentioned that some element or lines are connected to a target element block, it also includes a direct connection as well as a meaning indirectly connected to the target element block via some other element.

In addition, the same or similar reference numerals shown in the drawings denote the same or similar components as possible. In some drawings, the connection relationship of elements and lines is shown for an effective explanation of the technical contents, and other elements or circuit blocks may be further provided.

Each of the embodiments described and exemplified herein may also include its complementary embodiment, and details of the basic data access operations and internal functional circuits for the DRAM, and details of a typical power network, Please note that it is not described in detail for the sake of brevity.

1 is a block diagram of a multi-channel memory device in accordance with the concepts of the present invention.

Referring to the drawings, a multi-channel memory device 100 includes a multi-channel memory 120 and a switching controller 140.

The multi-channel memory 120 basically includes a first channel memory 122 and a second channel memory 124 that are independently accessed within the same chip. That is, the multi-channel memory 120 may include at least two channel memories. Each channel memory may be implemented as a DRAM or an MRAM. The first and second channel memories 122 and 124 are represented by an A-channel memory and a B-channel memory for convenience in FIG.

Each channel memory receives addresses, data, and commands channel-independent.

When the multi-channel memory 120 includes two channel memories, a decoupling unit 130 is provided between the channel memories. The decoupling unit 130 operatively isolates the first and second external power channel connection lines of the first and second channel memories 122 and 124 in response to a decoupling driving signal. Depending on the operating frequency characteristics of the decoupling unit 130, the DC current is shorted and the AC current such as power supply noise is open.

The power supply network of the first and second channel memories 122 and 124 may be formed as one unit over the entirety of the multi-channel memory device 100 according to the activation of the decoupling unit 130, have.

The switching controller 140 controls the switching control unit 140 in response to a channel power control signal CON in order to allow the external power sources independently applied to the first and second channel memories 122 and 124 to be used in corresponding channels, And applies the decoupling driving signal to the decoupling unit 130.

Let it be assumed that the first channel memory 122 performs a refresh operation and the second channel memory 124 performs a write operation when the power supply network is not configured in a channel independent manner. The refresh operation of all the banks of the first channel memory 122 is subjected to an active and a precharge operation. In this case, noise due to the consumption of the high power supply voltage VPP, which is the word line voltage, is generated in the first channel memory 122. Also, in the process of restoring the cell data, power consumption of the array voltage (VINTA) occurs in the first channel memory 122. The noise generated in the refresh operation may affect the write operation or the read operation of the second channel memory 124 even if the refresh cycle time tRFC is longer than the write or read operation time. On the contrary, the noise generated in the write operation of the second channel memory 124 affects the refresh operation of the first channel memory 122, and cell data restoration can be prevented.

Therefore, the decoupling unit 130 is selectively controlled to independently configure the power supply network in a channel-independent manner.

Fig. 2 is a block diagram of the apparatus of the first embodiment according to Fig. 1. Fig.

Referring to FIG. 1, a connection structure of a power source network of a ground power source (VSS) among external power sources is exemplarily shown in a multi-channel memory 120 including first and second channel memories 122 and 124. In the first channel memory 122, the first external power channel connection lines include first through n-th channel connection lines VSS1-A, VSS2-A, ..., VSSn-A. Here, n is a natural number of 2 or more. The first to n-th channel connection lines VSS1-A, VSS2-A, ..., VSSn-A receive the ground power VSS through an external power supply pad not shown.

In the second channel memory 124, the second external power channel connection lines include first through n-th channel connection lines VSS1-B, VSS2-B, ..., VSSn-B. Similarly, the first to n-th channel connection lines VSS1-B, VSS2-B, ..., VSSn-B receive the ground power VSS through an external power supply pad not shown.

When the first switch S1 in the decoupling unit 130 is opened, the first external power supply first channel connection line VSS1-A in the first channel memory 122 is connected to the second channel memory 124 are operatively separated from the second external power supply first channel connection line (VSS1-B). In this case, two power supply networks may be formed in a channel independent manner.

When the first switch S1 in the decoupling unit 130 is closed, the first external power supply first channel connection line VSS1-A in the first channel memory 122 is connected to the second channel And is operatively coupled to a second external power first channel connection line (VSS1-B) in the memory (124). In this case, one power source network may be formed in the multi-channel memory 120 as a whole.

Similarly, when the n-th switch Sn in the decoupling unit 130 is in the open state, the first external power supply n-channel connection line VSSn-A in the first channel memory 122 is connected to the second And is operatively separated from the second external power supply channel connection line (VSSn-B) in the channel memory (124).

When the n-th switch Sn in the decoupling unit 130 is closed, the first external power supply n-channel connection line VSSn-A in the first channel memory 122 is connected to the second channel And is operatively coupled to a second external power supply channel connection line (VSSn-B) in the memory (124).

As a result, the decoupling unit 130 connected between the channel memories 122 and 124 performs a decoupling operation according to a decoupling driving signal applied through the line L10. In response to the signal indicating that the decoupling driving signal is a switch-open signal, the decoupling unit 130 outputs the first and second external power channel connection lines (e.g., VSS1 -A, VSS1-B) are operatively separated from each other.

The decoupling unit 130 responds to the signal indicating that the decoupling driving signal indicates a switch close, and outputs the first and second external power channel connection lines (first and second external power channel connection lines) Yes VSS1-A, VSS1-B) are operatively connected to each other.

2, in order for the external power sources VSSA and VSSB, which are independently applied to the first and second channel memories 122 and 124, to be used in the corresponding channels, the switching controller 140 controls the channel power And applies the decoupling driving signal to the decoupling unit 130 in response to the control signal CONS. The channel power control signal CONS may be provided to the multi-channel memory device 100 as a mode register set (MRS) signal after power-up of the device.

As shown in FIG. 2, one or more power sources of an external power source (eg, VSS) may be formed depending on whether the decoupling unit 130 is operated or not.

Fig. 3 is a block diagram of the apparatus of the second embodiment according to Fig.

Referring to FIG. 1, a multi-channel memory device 100 includes a multi-channel memory 120 and a switching controller 141.

The multi-channel memory 120 basically includes a first channel memory 122 and a second channel memory 124 that are independently accessed within the same chip. That is, the multi-channel memory 120 may include at least two channel memories. Each channel memory may be implemented as a DRAM or an MRAM. Internal power networks are formed in the first and second channel memories 122 and 124, respectively. As in Fig. 1, each channel memory receives addresses, data, and commands channel-independent.

When the multi-channel memory 120 includes two channel memories, a decoupling unit 130 is provided between the channel memories. The decoupling unit 130 responds to a decoupling driving signal applied through the line L12 to connect the first and second internal power supply lines (e.g., VIP1-A, VIP2-B) are operatively separated from each other.

The internal power supply networks of the first and second channel memories 122 and 124 may be formed as one unit over the entirety of the multi-channel memory device 100 according to the activation of the decoupling unit 130, It is possible.

In order to allow the first and second internal power sources, which are independently applied to the first and second channel memories 122 and 124, to be used in corresponding channels, the switching control unit 141 outputs a channel power control signal CONP And applies the decoupling driving signal to the decoupling unit 130 in response to the decoupling signal.

3, the first and second internal power generation units 151 and 152 may be installed in the multi-channel memory 120, as shown in FIG.

That is, the first and second internal power generation units 151 and 152 apply the first and second internal power supplies independent of each other to the first and second channel memories 122 and 124, respectively. For example, the first internal power supply (VIP1) is supplied to the first power supply network (PN1) through the first channel power supply line (PO1). The second internal power supply (VIP2) is supplied to the second power supply network (PN2) through the second channel power supply line (PO2). Here, the voltage levels of the first internal power supply (VIP1) and the second internal power supply (VIP2) may be the same. When the first internal power supply generation unit 151 is a high voltage pump circuit, the external power supply voltage VEXT is received by the pad PA1 to perform charge pumping. The charge pumped voltage may be provided to the first power supply network PN1 of the first channel memory 122 as a high power supply voltage VPP.

Further, when the second internal power supply generating unit 152 is a high voltage pump circuit, the external power supply voltage VEXT is received by the pad PA2 to perform charge pumping. The charge pumped voltage may be provided to the second power supply network PN2 of the second channel memory 124 as a high power supply voltage VPP.

In the multi-channel memory 120 of FIG. 3 composed of two channels, the connection configuration of the internal power supply network is exemplarily shown. In the first channel memory 122, the first internal power supply channel connection lines include first through n-th channel connection lines VIP1-A, VIP2-A, ..., VIPn-A. Here, n is a natural number of 2 or more. The first to n-th channel connection lines VIP1-A, VIP2-A, ..., VIPn-A receive the first internal voltage VIP-A through the first channel power supply line PO1 . The first internal voltage VIP-A is supplied to the first power-supply voltage VOUT and the second power-supply voltage VINT that are higher than the internal power-supply voltage VINT, ). ≪ / RTI > The first internal voltage VIP-A is a voltage that is lower than the internal power-supply voltage VINT, the half-level voltages VBL and VP of the internal power-supply voltage VINT, VBB2) higher than the second substrate power supply voltage VBB2.

In the second channel memory 124, the second internal power supply channel connection lines include first through n-th channel connection lines VIP1-B, VIP2-B, ..., VIPn-B. Similarly, the first to n-th channel connection lines VIP1-B, VIP2-B, ..., VIPn-B are connected to the second internal power supply line PO2 via the second internal voltage VIP- . Here, the second internal voltage VIP-A is a voltage that is higher than the internal power-supply voltage VINT, the high power-supply voltage VPP higher than the internal power-supply voltage VINT, ). ≪ / RTI > The second internal voltage VIP-B may be a voltage lower than the internal power supply voltage VINT, a half level voltage VBL or VP of the internal power supply voltage VINT, VBB2) higher than the second substrate power supply voltage VBB2.

When the first switch S1 in the decoupling unit 130 is opened, the first internal power supply first channel connection line VIP1-A in the first channel memory 122 is connected to the second channel memory 124 and the second external power supply first channel connection line (VIP1-B). In this case, the two power supply networks PN1 and PN2 may be formed channel-independent.

When the first switch S1 in the decoupling unit 130 is closed, the first internal power supply first channel connection line VIP1-A in the first channel memory 122 is connected to the second channel And is operatively coupled to a second internal power first channel connection line (VIP1-B) in the memory (124). In this case, the first and second internal power supply networks PN1 and PN2 form a single power supply network in the multi-channel memory 120 as a whole.

Similarly, when the n-th switch Sn in the decoupling unit 130 is opened, the first internal power supply n-channel connecting line VIPn-A in the first channel memory 122 is connected to the second internal power supply n-channel connecting line Is operatively separated from the second internal power supply n-channel connection line (VIPn-B) in the channel memory (124).

When the n-th switch Sn in the decoupling unit 130 is closed, the first internal power supply n-channel connection line VIPn-A in the first channel memory 122 is connected to the second channel And is operatively coupled to a second internal power supply n-channel connection line (VIPn-B) in the memory 124.

As a result, the decoupling unit 130 connected between the channel memories 122 and 124 performs a decoupling operation according to a decoupling driving signal applied through the line L12. In response to the signal indicating that the decoupling driving signal is a switch-open signal, the decoupling unit 130 receives the first and second internal power channel connection lines (e.g., VIP1 and VIP2) disposed in the first and second channel memories 122 and 124, -A, and VIP1-B) are operatively separated from each other.

In response to the signal indicating that the decoupling driving signal indicates a switch close, the decoupling unit 130 outputs the first and second internal power supply lines (first and second internal power supply lines) VIP1-A, VIP1-B) are operatively connected to each other.

3, the switching controller 140 controls the internal power supplies (VIP-A and VIP-B), which are independently applied to the first and second channel memories 122 and 124, to be used in corresponding channels And applies the decoupling driving signal to the decoupling unit 130 in response to the channel power control signal CONP. The channel power control signal CONP may be provided to the multi-channel memory device 100 as a mode register set (MRS) signal after power-up of the device.

As shown in FIG. 3, the power source network of the internal power source (e.g., VIP) may be formed by one or a number of channels depending on the decoupling operation of the decoupling unit 130.

FIG. 4 is a block diagram of the apparatus of the third embodiment according to FIG. 1. FIG.

Referring to FIG. 4, in the multi-channel memory 120 including the first and second channel memories 122 and 124, a connection configuration related to a power source network of external power sources is exemplarily shown. In the first channel memory 122, the first external power channel connection lines include first through n-th channel connection lines VEP1-A, VEP2-A, ..., VEPn-A. Here, n is a natural number of 2 or more. The first through n-th channel connection lines VEP1-A, VEP2-A, ..., VEPn-A receive an external power supply VEP through external power supply pads P1, P2, . A part or all of the first to n-th channel connection lines VEP1-A, VEP2-A, ..., VEPn-A forms a power source network PN10 of the first external power source.

In the second channel memory 124, the second external power channel connection lines include first through n-th channel connection lines VEP1-B, VEP2-B, ..., VEPn-B. Here, n is a natural number of 2 or more. The first through n-th channel connection lines VEP1-B, VEP2-B, ..., VEPn-B receive an external power supply VEP through external power supply pads P10, P20 and P30 . Some or all of the first to n-th channel connection lines VEP1-B, VEP2-B, ..., VEPn-B form a power source network PN10 of the first external power source.

The external power supply pads P1, P2 and P3 of the first channel and the external power supply pads P10, P20 and P30 of the second channel are installed for each channel. At the PCB level, As shown in FIG.

When the first switch S1 in the decoupling unit 130 is opened, the first external power supply first channel connection line VEP1-A in the first channel memory 122 is connected to the second channel memory 124 are operatively separated from the second external power supply first channel connection line (VEP1-B). In this case, the two power supply networks PN10 and PN20 may be formed channel-independent.

When the first switch S1 in the decoupling unit 130 is closed, the first external power supply first channel connection line VEP1-A in the first channel memory 122 is connected to the second channel And is operatively coupled to a second external power first channel connection line (VEP1-B) in the memory (124). In this case, one power source network may be formed in the multi-channel memory 120 as a whole. That is, the two power supply networks PN10 and PN20 are operatively connected to each other to form a common power supply network.

Similarly, when the n-th switch Sn in the decoupling unit 130 is in the open state, the first external power supply n-channel connection line VEPn-A in the first channel memory 122 is connected to the second Is operatively separated from the second external power supply channel connection line (VEPn-B) in the channel memory (124).

In the meantime, when the n-th switch Sn in the decoupling unit 130 is closed, the first external power supply n-channel connection line VEPn-A in the first channel memory 122 is connected to the second channel And is operatively coupled to a second external power supply channel connection line (VEPn-B) in the memory (124).

As a result, the decoupling unit 130 connected between the channel memories 122 and 124 performs a decoupling operation according to a decoupling driving signal applied through the line L13. In response to the signal indicating that the decoupling driving signal is a switch-open signal, the decoupling unit 130 outputs the first and second external power channel connection lines (e.g., VEP1 and VEP2) arranged in the first and second channel memories 122 and 124, -A, VEP1-B) are operatively separated from each other.

The decoupling unit 130 responds to the signal indicating that the decoupling driving signal indicates a switch close, and outputs the first and second external power channel connection lines (first and second external power channel connection lines) Yes VEP1-A, VEP1-B) are operatively connected to each other.

4, in order for the external power sources VEPA and VEPB applied to the first and second channel memories 122 and 124 to be used in corresponding channels, the switching controller 142 controls the channel power And applies the decoupling driving signal to the decoupling unit 130 in response to the control signal CONE. The channel power control signal CONE may be provided to the multi-channel memory device 100 as a mode register set (MRS) signal after power-up of the device.

As shown in FIG. 4, the power source network of the external power source (eg, VEP) may be formed by one or a set number of channels depending on whether the decoupling unit 130 performs a decoupling operation.

The external power supply VEP of FIG. 4 includes a ground voltage VSS and includes an external power supply voltage VEXT, an external voltage VDD, an input / output external voltage VDDQ, an input / output portion ground voltage VSSQ, And an external voltage VDDCA.

Since the power supply network can be independently configured for each channel, independent operation is assured for each channel and interference between power supply noise between channels is eliminated or minimized. It is also possible to implement one power supply network over the entire channel as required.

FIG. 5 is an exemplary view of a decoupling unit in FIG. 1. FIG.

Referring to FIG. 5, the decoupling unit 130 may be implemented with an RC filter S1.

The RC filter S1 may be operated in response to a signal SQ applied as the decoupling driving signal. The RC filter S1 may selectively perform the role of the integrator depending on whether the signal SQ is in a state or not.

When the RC filter S1 is enabled, the first power supply line LIL and the second power supply line LIR are operatively connected to each other. On the other hand, when the RC filter S1 is disabled, the first power supply line LIL and the second power supply line LIR are operatively separated from each other. Here, the first power supply line LIL and the second power supply line LIR correspond to the first and second external power supply lines (e.g., VSS1-A and VSS1-B) in the case of FIG.

FIG. 6 is another embodiment of the decoupling unit in FIG. 1. FIG.

Referring to FIG. 6, the decoupling unit 130 may be implemented as a transmission gate TG.

The transmission gate TG may be operated in response to a signal SQ applied as the decoupling driving signal. The transmission gate TG may selectively perform a transmission function of the power according to the logic state of the signal SQ.

As the signal SQ is applied to the high level, the first power supply line LIL and the second power supply line LIR are operatively connected to each other when the transmission gate TG is enabled. Meanwhile, when the signal SQ is applied to the high level, the first power supply line LIL and the second power supply line LIR are operatively separated from each other when the transmission gate TG is disabled. The first power supply line LIL and the second power supply line LIR correspond to the first and second internal power supply lines VIP1-A and VIP1-B, respectively.

The capacitors C1 and C2 may be connected to the first power supply line LIL and the second power supply line LIR, respectively, in order to perform the noise filtering function. In Fig. 6, the inverter INV1 is an element for inverting the logic level of the signal SQ to drive the fMOS transistor of the transmission gate TG.

Fig. 7 is an equivalent circuit diagram of Fig. 5 or Fig.

Referring to FIG. 7, a configuration is shown in which a resistor R1 and first and second capacitors C1 and C2 are connected between the first power supply line LIL and the second power supply line LIR.

The resistor R1 functions as a variable resistor and can correspond to the transmission gate TG of Fig.

When the transmission gate TG is enabled, the resistor R1 is in a low resistance state and the first power supply line LIL and the second power supply line LIR are operatively connected to each other. Meanwhile, when the transmission gate TG is disabled, the resistor R1 is in a high resistance state, and the first power supply line LIL and the second power supply line LIR are operatively separated from each other. The resistor R1 and the first capacitor C1 form an RC filter to perform a power supply noise filtering operation. In addition, the resistor R1 and the second capacitor C2 form another RC filter to perform a power supply noise filtering operation.

8 is a circuit block diagram of the channel memory of FIG.

Referring to the drawings, the first channel memory 122 and the second channel memory 124 may have the circuit block configuration of FIG.

8, an arbitrary channel memory 122 includes a memory cell array 11, a column gate 12, a sense amplifier circuit 13, an I / O buffer 14, an address buffer 15, a row decoder 16, a column decoder 17, and a control circuit 18, and a power switching circuit 19.

The memory cell array 11 may consist of DRAM memory cells consisting of one access transistor and one storage capacitor. The memory cells may be arranged to form a matrix structure of rows and columns.

The control circuit 18 receives an applied control signal and an address, and generates an internal control signal for controlling the set operation modes.

The power switching circuit 19 connects or disconnects the power supply networks of the channel memory 122 in response to the internal control signal.

The address buffer 15 receives the applied address and performs buffering. In response to the internal control signal, the address buffer 15 provides a row address for selecting a row of the memory cell array to the row decoder 16, and supplies the column address for selecting the column of the memory cell array to the column decoder 17, .

The row decoder 16 decodes the row address in response to the internal control signal. When the result of the row address decoding is applied to the memory cell array 11, a selected one of a plurality of word lines connected to the memory cells is driven.

The column decoder 17 decodes the column address in response to the internal control signal.

The column gate 12 performs column gating according to the decoded column address. As a result of the column gating, selected bit lines connected to the memory cells are driven.

The sense amplifier circuit 13 detects the potential appearing on the bit line of the selected memory cell and senses the data stored in the selected memory cell.

The I / O buffer 14 buffers input and output data. In the read operation mode, the I / O buffer 14 buffers the data read out from the sense amplifier circuit 13 and outputs it to the I / O terminal (I / O).

9A to 9D are diagrams showing applications of the present invention applied to a memory system having various interfaces.

Referring to FIG. 9A, the memory system includes a controller 1000 and a memory device 2000. The controller 1000 includes a control unit 1100 and an input and output circuit 1200. The memory device 2000 includes a DRAM core 2110 including a sensing and latch circuit 2110 and an input and output circuit 2200. [ The input / output circuit of the controller 1000 transmits a command, a control signal, an address and a data strobe DQS to the memory device 2000 and the data DQ is an interface (Interface). Here, the DRAM Core 2110 may be implemented as a multi-channel memory device as shown in FIG. Accordingly, the implementation of the external power supply network or the internal power supply network can be formed channel-independent or channel-shared.

9B, the input / output circuit of the controller 1000 transmits an interface for transmitting a chip select signal CS and an address in one packet and data DQ for transmitting and receiving, .

9C, the input / output circuit of the controller 1000 transmits the chip select signal CS, the address and the write data wData in one packet, and the read data rData receives And an interface.

9D, the input / output circuit of the controller 1000 includes an interface for transmitting and receiving a command, an address and data DQ, and receiving a chip selection signal CS.

10 is a diagram showing an application example of the present invention applied to a memory system stacked through a TSV (TSV).

Referring to FIG. 10, the interface chip 3010 is located on the lowest layer, and the memory chips 3100, 3200, 3300, and 3400 are located thereon. The memory chips include the sensing and storing circuits 3601, 3602, 3603, and 3604 of the present invention. The chip and the chip are connected through a micro pump (uBump) 3500 and the chip itself is a through silicon via (TSV) Lt; / RTI > For example, the number of stacked chips may be one or more.

In the case of FIG. 10, the memory chips 3100, 3200, 3300, and 3400 may be implemented as multi-channel memory devices as shown in FIG.

11 is a diagram showing an application example of the present invention applied to an electronic system.

11, a DRAM 3500 including a data read circuit 3550, a central processing unit (CPU) 3150, and a user interface 3210 are connected via a system bus 3250. [

When the electronic system is a portable electronic device, a separate interface can be connected to an external communication device. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, or the like.

The chips of the DRAM 3500 or the central processing unit (CPU) 3150 may be mounted using various types of packages, either individually or together. For example, the chip can be used as a package in package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC) ), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package Can be packaged as a package.

On the other hand, in Fig. 11, the bus 3250 may further employ a flash memory. However, various types of nonvolatile storage may be used without limitation.

The non-volatile storage may store data information having various data types such as text, graphics, software codes, and the like.

12 is a block diagram illustrating an application of the present invention applied to a computing device.

Referring to FIG. 12, a computing device may include a memory system 4500 having a DRAM 4520 and a memory controller 4510. The computing device may include an information processing device, a computer, and the like. In one example, a computing device may include a memory system 4500 and a modem (MODEM 4400), a CPU 4100, a RAM 4200, and a user interface 4300, each of which is electrically coupled to the system bus 4250. The memory system 4500 may store data processed by the CPU 4100 or externally input data.

Computing devices can also be applied to solid state disks, camera image sensors, and other application chipsets. In one example, the memory system 4500 can be configured with an SSD, in which case the computing device can store large amounts of data reliably and reliably in the memory system 4500.

The DRAM 4520 constituting the memory system 4500 can be implemented as a multi-channel memory device as in Fig. 1, so that the performance of a computing device can be improved.

The memory controller 4510 may apply commands, addresses, data, or other control signals to the DRAM 4520 in a channel independent manner.

The CPU 4100 functions as a host and controls all operations of the computing device.

The host interface between the CPU 4100 and the memory controller 4510 includes various protocols for exchanging data between the host and the memory controller 4500. Illustratively, the memory controller 4510 may be implemented using a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- , At least one of various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, And may be configured to communicate with the outside.

The device shown in FIG. 12 may be a computer, a UMPC (Ultra Mobile PC), a digital picture player, a digital video recorder, a digital video player, One of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or Or one of various components of an electronic device, such as one of various components that make up a computing system.

13 is a block diagram illustrating an application of the present invention applied to a smartphone.

Referring to FIG. 13, a main block diagram of a mobile phone such as a smart phone incorporating a DRAM is shown. The smartphone includes an antenna 501 (ATN), an analog front end block 503 (AFE), an analog-digital modulation circuit 505 (ADC1, 519: ADC2), a digital-analog modulation circuit 507 (DAC1, 517: DAC2) A baseband block 509 (BBD), a speaker 521 (SPK), a liquid crystal monitor 523 (LCD), a microphone 525 (MIK), and an input key 527 (KEY). Although not shown in the drawing, the analog front end block 503 may be an antenna switch, a band pass filter, various amplifiers, a power amplifier, a phase-locked loop (PLL), a voltage controlled oscillator (VCO), an orthogonal demodulator, And is a circuit block configured to transmit and receive radio waves. The baseband block 509 may also include a signal processing circuit 511 (SGC), a baseband processor 513 (BP), and a DRAM 515.

The operation of the smartphone according to Fig. 13 will be described. When receiving an image including voice and character information, the radio wave input from the antenna is input to the analog-digital modulation circuit 505 (ADC1) via the analog front end block 503 (AFE) - Digitally converted. The output signal of the ADC1 505 is inputted to the signal processing circuit 511 (SGC) in the baseband block 509 and subjected to voice and image processing. The audio signal is supplied from the digital-analog conversion circuit 517 (DAC2) (521), and the image signal is transmitted to the liquid crystal monitor 523, respectively.

When a voice signal is transmitted, the signal input from the microphone 525 is input to the signal processing circuit 511 through the analog-to-digital conversion circuit 519 (ADC2), and voice processing is performed. The output of the SGC 511 is transmitted from the digital-to-analog conversion circuit 507 (DAC1) to the antenna 501 via the analog front end block 503. When transmitting the character information, the signal input from the input key 527 is transmitted to the antenna 501 through the baseband block 509, the digital-analog conversion circuit 507, and the AFE 503 in order .

In FIG. 13, the DRAM 515 may be implemented as a multi-channel memory device as shown in FIG. In such a case, the DRAM 515 may be accessed by the baseband processor 513 via the first channel, as well as by an application processor not shown via the second channel. As a result, one memory chip can be shared by two processors.

Although the DRAM 515 is mounted in Fig. 13, the MRAM may be mounted instead of the DRAM in a different case.

Volatile semiconductor memory devices, such as SRAMs or DRAMs, lose data stored when power is interrupted.

In contrast, a non-volatile semiconductor memory device, such as a magnetic random access memory (MRAM), retains stored data even after power supply interruption. Therefore, when data loss is not desired due to a power failure or a power-off, the nonvolatile semiconductor memory device is preferably used for storing data.

In addition to the merits of FIG. 1 in the case of STT-MRAM (Spin Transfer Torque Magneto Resistive Random Access Memory) constituting a multi-channel memory device, the merits of MRAM can be added.

The STT-MRAM cell may include an MTJ (Magnetic Tunnel Junction) element and a selection transistor. The MTJ element may basically include a fixed layer, a free layer, and a tunnel layer formed therebetween. The magnetization direction of the pinned layer is fixed and the magnetization direction of the free layer may be the same as or opposite to the magnetization direction of the pinned layer depending on conditions.

14 is a block diagram showing an application example of the present invention applied to a mobile device.

14, a mobile device such as a notebook or portable electronic device includes a microprocessing unit 1100 (MPU), a display 1400, an interface unit 1300, a DRAM 2000, and a solid state drive 3000 .

The MPU 1100, the DRAM 2000, and the SSD 3000 may be manufactured or packaged into one chip as the case may be. As a result, the DRAM 2000 and the flash memory 3000 may be embedded in the mobile device.

When the mobile device is a portable communication device, the interface unit 1300 may be connected to a modem and a transceiver that perform communication data transmission / reception and data modulation / demodulation functions.

The MPU 1100 controls all operations of the mobile device according to a preset program.

The DRAM 2000 is connected to the MPU 1100 through a system bus and can function as a buffer memory or a main memory of the MPU 1100.

The DRAM 2000 may be a multi-channel memory device as shown in FIG.

The flash memory 3000 may be a NOR type or NAND type flash memory.

The display 1400 may have a touch screen as a liquid crystal having a backlight or an element such as a liquid crystal or an OLED having an LED light source. The display 1400 functions as an output device for displaying images such as characters, numbers, and pictures in color.

Although the mobile device has been described as a mobile communication device, it may function as a smart card by adding or subtracting components when necessary.

The mobile device may be connected to an external communication device via a separate interface. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, or the like.

Although it is not shown in the drawing, the mobile device may be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Do.

Although the flash memory is employed in Fig. 14, various types of nonvolatile storage may be used.

The non-volatile storage may store data information having various data types such as text, graphics, software codes, and the like.

15 is a block diagram showing an application example of the present invention applied to an optical I / O schema.

Referring to FIG. 15, a memory system 30 employing a high-speed optic I / 0 includes a chipset 40 and memory modules 50 and 60 as a controller mounted on a PCB substrate 31. The memory modules 50 and 60 are inserted into the slots 35_1 and 35_2 provided on the PCB substrate 31, respectively. The memory module 50 includes a connector 57, channel DRAM memories 55_1-55_n, an optical I / O input section 51, and an optical I / O output section 53. [

The optical I / O input unit 51 may include a photo-electric conversion element, for example, a photodiode, for converting an applied optical signal into an electrical signal. Therefore, the electric signal output from the photo-electric conversion element is received by the memory module 50. The optical I / O output unit 53 may include an electro-optical conversion element, for example, a laser diode, for converting an electric signal output from the memory module 50 into an optical signal. If necessary, the optical I / O output unit 53 may further include an optical modulator for modulating a signal output from the light source.

The optical cable 33 is responsible for optical communication between the optical I / O input unit 51 of the memory module 50 and the optical transmission unit 41_1 of the chipset 40. The optical communication may have a bandwidth of several tens of Gigabits per second or more. The memory module 50 may receive signals or data from the signal lines 37 and 39 of the chipset 40 through the connector 57 and transmit the signals or data through the optical cable 33 Speed data communication with the chipset 40. On the other hand, the resistors Rtm provided in the unshown lines 37 and 39 are termination resistors.

In the case of the memory system 30 adopting the optical I / O structure as shown in FIG. 15, the channel DRAM memories 55_1-55_n according to the concept of the present invention can be mounted in one chip.

Therefore, the chipset 40 can perform data read and data write operations independently for each channel through the channel DRAM memories 55_1-55_n. In this case, as shown in FIG. 1, the power supply network can be configured to be channel independent. Thus, the power noise of one channel does not affect adjacent channels, so the performance of the memory system 30 is improved or stabilized.

In FIG. 15, the chipset 40 may have an integrated access detection unit 210. The centralized access detecting unit 210 generates an intensive access detection signal when the number of times of application of the frequently applied address exceeds a predetermined threshold value.

The chipset 40 may prevent or mitigate corruption of data held in memory cells of neighboring memory regions adjacent to a specific memory region when the lumped-access detection signal is generated.

For example, when a specific word line, a specific bit line, or a specific memory block of a volatile semiconductor memory such as a DRAM is intensively accessed, deterioration of memory cell data may be caused. That is, the memory cells of neighboring word lines adjacent to a specific word line, adjacent bit lines adjacent to a specific bit line, or memory cells of an adjacent memory block adjacent to a specific memory block can lose cell data due to centralized access. It is necessary to eliminate or avoid such address concentration and to prevent or alleviate cell data loss.

When the channel DRAM memories 55_1 to 55_n of the memory modules 50 and 60 are accessed by memory page unit, column unit, or bank unit, the centralized access detecting unit 210 monitors access concentration.

When the memory system of Fig. 15 is referred to as an SSD, the channel DRAM memories 55_1-55_n may be used as a user data buffer.

16 is a block diagram showing an application example of the present invention applied to a portable multimedia device.

16, the portable multimedia device 500 includes an AP 510, a memory device 520, a storage device 530, a communication module 540, a camera module 550, a display module 560, A module 570, and a power module 580.

The AP 510 may perform a data processing function.

In FIG. 16, the memory device 520 may configure the power supply network as channel independent as shown in FIG. Thus, the power noise of one channel does not affect adjacent channels, so that the performance of the portable multimedia device is improved or stabilized. In addition, one power supply network may be formed in the memory device 520 when necessary. Therefore, the performance of the portable multimedia device becomes powerful.

The communication module 540 connected to the AP 510 may function as a modem that performs communication data transmission / reception and data modulation / demodulation functions. .

The storage device 530 may be implemented as a NOR type or NAND type flash memory for storing a large amount of information.

The display module 560 may be implemented as a liquid crystal having a backlight, a liquid crystal having an LED light source, or an element such as an OLED. The display module 560 functions as an output device for displaying images such as characters, numbers, and pictures in color.

The touch panel module 570 may provide touch input to the AP 510 alone or on the display module 560.

Although the portable multimedia device has been described as a mobile communication device, it can function as a smart card by adding and subtracting components when necessary.

The portable multimedia device may be connected to an external communication device through a separate interface. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, or the like.

The power module 580 performs power management of the portable multimedia device. As a result, the power saving of the portable multimedia device is achieved when the PMIC scheme is applied in the device.

The camera module 550 includes a camera image processor (CIS) and is connected to the AP 510.

It is apparent to those skilled in the art that another application chipset or mobile DRAM may be further provided in the portable multimedia device although not shown in the drawing.

17 is a block diagram showing an application example of the present invention applied to a personal computer. 17, a computing device 700 includes a processor 720, a chipset 722, a data network 725, a bridge 735, a display 740, a non-volatile storage 760, a DRAM 770, A keyboard 736, a microphone 737, a touch portion 738, and a pointing device 739. [

In FIG. 17, the DRAM 770 can configure the power supply network in a channel-independent manner as shown in FIG. Thus, the power noise of one channel does not affect adjacent channels, so that the performance of the personal computer is improved or stabilized.

The chipset 722 may apply commands, addresses, data, or other control signals to the DRAM 770.

The processor 720 functions as a host and controls all operations of the computing device 700.

The host interface between the processor 720 and the chipset 722 includes various protocols for performing data communication.

The non-volatile storage 760 may include, for example, an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM, a spin transfer torque MRAM, A phase change RAM (PRAM), a resistive RAM (RRAM or ReRAM), a Nanotube RRAM, a Polymer RAM (Random Access Memory), or the like, which is also called RAM (CBRAM), FeRAM (Ferroelectric RAM) (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory .

The personal computer shown in FIG. 17 may be a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, a tablet computer, , A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage that constitutes a data center, Device, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or various components constituting a computing system Or one of various components of an electronic device, such as one of the < RTI ID = 0.0 >

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention.

For example, although the first and second channel memories have been described, the circuit configuration of the drawings may be changed or changed without departing from the technical idea of the present invention when the matters are different, will be. Although the present invention has been described with reference to a semiconductor memory including a DRAM, the present invention can be applied to other semiconductor memory devices.

Description of the Related Art [0002]
100: Multi-channel memory device
120: Multi-channel memory
130: decoupling unit
140:

Claims (10)

A first channel memory and a second channel memory that are accessed independently from each other in the same chip;
A decoupling unit operatively separating the first and second external power channel connection lines of the first and second channel memories in response to a decoupling driving signal; And
And a switching controller for applying the decoupling driving signal to the decoupling unit in response to a channel power control signal so that external power sources independently applied to the first and second channel memories are used in corresponding channels Channel memory device.
2. The multi-channel memory device of claim 1, wherein the first and second channel memories comprise DRAM cells or MRAM cells.
The multi-channel memory device of claim 1, wherein the first and second external power supply lines are connected to each other when the external power supplies are applied.
2. The multi-channel memory device of claim 1, wherein the first and second external power channel connection lines are separated from each other when the external power sources are applied.
The multi-channel memory device according to claim 1, wherein the decoupling unit short-circuits the DC component of the external power supply and opens the AC component of the external power supply in the decoupling operation.
2. The multi-channel memory device of claim 1, wherein the decoupling section is an RC filter or a transmission gate.
A first channel memory and a second channel memory that are accessed independently from each other in the same chip;
First and second internal power generators for applying first and second internal power supplies independent of each other to the corresponding first and second channel memories;
A decoupling unit operatively separating the first and second internal power channel connection lines of the first and second channel memories in response to a decoupling driving signal; And
And a switching controller for applying the decoupling driving signal to the decoupling unit in response to a channel power control signal so that the first and second internal power supplies are used in corresponding channels.
The method of claim 7, wherein each of the first and second internal power generation units includes a multi-channel memory that generates at least one of an internal power supply voltage, a high power supply voltage higher than the internal power supply voltage, Device.
[7] The method of claim 7, wherein when the first and second internal power supply lines are connected to each other, one power supply network is formed in the first and second channel memories, Wherein the first and second channel memories have independent power supply networks when the lines are separated from each other.
A power supply network control method in a multi-channel memory device having a first channel memory and a second channel memory that are independently accessed in the same chip, the method comprising:
First and second internal power supplies or external power supplies independent of each other are applied to the corresponding first and second channel memories;
Wherein the first and second internal power supply networks are connected to the first and second internal power supply networks and the first and second internal power supply networks, respectively, when the decoupling request signal is generated.

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