KR20150016798A - Semicondctor devices and methods for fabricating the same - Google Patents

Semicondctor devices and methods for fabricating the same Download PDF

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Publication number
KR20150016798A
KR20150016798A KR1020130092691A KR20130092691A KR20150016798A KR 20150016798 A KR20150016798 A KR 20150016798A KR 1020130092691 A KR1020130092691 A KR 1020130092691A KR 20130092691 A KR20130092691 A KR 20130092691A KR 20150016798 A KR20150016798 A KR 20150016798A
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KR
South Korea
Prior art keywords
test
barrier film
substrate
forming
cell
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Application number
KR1020130092691A
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Korean (ko)
Inventor
지상욱
문형렬
박영렬
이인겸
조성동
Original Assignee
삼성전자주식회사
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Priority to KR1020130092691A priority Critical patent/KR20150016798A/en
Publication of KR20150016798A publication Critical patent/KR20150016798A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Abstract

A method for manufacturing a semiconductor device according to the embodiment of the present invention includes the steps of: providing a substrate which includes a plurality of cell regions which are separated by a scribe lane; forming a groove which faces from a first surface of the substrate to a second surface which faces the first surface in the scribe lane; successively forming a first insulation layer, a first barrier layer, and a second insulation layer in the groove; forming first and second test holes which pass through the second insulation layer and expose the first barrier layer in the groove; successively forming a metal layer and the second barrier layer in the first and second test holes; exposing the first insulation layer by etching the metal layer and the first and second barrier layers; and forming a first test through electrode and a second test through electrode in the first and second test holes, respectively. According to the method for manufacturing the semiconductor device according to the present invention, a through silicon via is electrically tested without performing a thinning process and a backside process on the second surface of the substrate.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a penetrating electrode and a method of manufacturing the same.

The trend in the electronics industry today is to manufacture lightweight, compact, high speed, multifunctional, and high performance products at low cost. To achieve this goal, a multi-chip stacked package technology or a system in package technology is used.

A package, which is a multi-chip stacked package or system, can perform functions of a plurality of unit semiconductor devices in one semiconductor package. A package, which is a multi-chip stacked package or system, may be somewhat thicker than a conventional single-chip package, but is substantially similar in size to a single-chip package in plan view and, therefore, is highly functional, such as a mobile phone, a notebook computer, a memory card, It is mainly used for products requiring compactness or mobility. A multi-chip stacked package technology or a package technology that is a system, uses a through silicon via (TSV) technology. The penetrating electrode may affect the performance of the semiconductor device.

The present invention provides a silicon penetrating electrode capable of improving the reliability of a semiconductor device and a manufacturing method thereof.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: providing a substrate including a plurality of cell regions separated by a scribe lane; Forming a groove in the scribe lane from a first surface of the substrate to a second surface opposite the first surface; Sequentially forming a first insulating film, a first barrier film, and a second insulating film in the groove; Forming first and second test holes through the second insulating film in the groove and exposing the first barrier film; Sequentially forming a second barrier film and a metal layer in the first and second test holes; Then, the metal layer, the first and second barrier films are etched to expose the first insulating film, and first test through electrodes and second test through electrodes are formed in the first test holes and the second test holes, respectively.

The method of fabricating the semiconductor device may further include forming first and second test pads on the first and second test penetrating electrodes, respectively.

In the manufacturing method of the semiconductor device, the first and second test pads may be electrically connected to the first and second test penetration electrodes through the first barrier film.

The method of manufacturing the semiconductor device further comprises forming a cell hole in the cell region from the first surface of the substrate to the second surface opposite to the first surface at the same time of forming the groove; The first insulating film and the first barrier film are formed in the cell hole; The second barrier film and the metal layer are formed on the first barrier film; And forming a silicon through electrode in the cell hole by the etching process.

The manufacturing method of the semiconductor device may further include forming a cell pad on the silicon through electrode.

Wherein the first and second barrier layers are formed of a material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride or titanium / And may be one or two or more laminated structures selected.

In the method of manufacturing the semiconductor device, the first insulating film may be silicon oxide, and the second insulating film may be silicon nitride.

A semiconductor device according to an embodiment of the present invention includes: a cell hole from a first surface of a substrate to a second surface opposite to the first surface; A first insulating film and a first barrier film sequentially provided in the cell hole; And a second barrier film and a conductive pattern sequentially provided in the first barrier film.

According to the method of manufacturing a semiconductor device according to an embodiment of the present invention, it is possible to perform electrical testing of a silicon through electrode without performing a thinning process and a backside process on a second surface of the substrate, There is an advantage that the reliability of the penetrating electrode can be secured.

1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of the area A shown in FIG. 1. FIG.
3 to 7 are cross-sectional views illustrating a method of manufacturing a silicon penetrating electrode according to an embodiment of the present invention.
8 is a plan view showing a package module according to an embodiment of the present invention.
9 is a view showing a memory card according to an embodiment of the present invention.
10 is a block diagram illustrating an electronic system according to an embodiment of the present invention.
11 is a diagram showing an example in which the electronic system of Fig. 11 is applied to a mobile phone.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

In the following, a semiconductor device and a manufacturing method thereof are used as an example for explaining features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. The invention may also be embodied or applied in other embodiments. In addition, the detailed description may be modified or changed in accordance with the viewpoint and use without departing from the scope, technical thought and other objects of the present invention.

In the description of the embodiment, when it is described as being formed on " on / under "of each layer, the upper (upper) Or formed indirectly through another layer. When an element or layer is referred to as being "connected" or "adjacent" to another element or layer, it may be directly connected to, coupled to, or adjacent to another element or layer, Or that there may be elements or layers sandwiched therebetween.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical idea of the present invention.

1 is a plan view showing a semiconductor device according to an embodiment of the present invention. Cell regions are provided on the substrate. A plurality of cell regions are arranged on the substrate in the horizontal and vertical directions. A scribe lane for dicing the substrate is disposed between each cell region.

2 is an enlarged view of the area A shown in FIG. A cell pad 161 is provided on the cell region. Although one pad is shown in the figure, two or more pads may be provided, depending on the embodiment. Then, first and second test pads 162 and 163 may be provided in the scribe lanes between the cell areas. The first and second test pads 162 and 163 may be disposed along the scribe lane direction. Further, although two test pads are shown in Fig. 2, more than two test pads may be provided according to an embodiment.

FIGS. 3 to 7 are views showing a method of manufacturing the semiconductor device of the semiconductor device shown in FIG.

Fig. 3 (a) is an exemplary view of a section taken along a line I-I 'of Fig. 2, and Fig. 3 (b) is an exemplary view of a section taken along a line II-II' of Fig. Referring to Figs. 3 (a) and 3 (b), a substrate 100 having a first surface and a second surface opposed to the first surface is provided. The substrate 100 may be, for example, a silicon substrate doped with a P-type impurity.

An oxide (not shown) and a hard mask (not shown) are deposited on the substrate 100, and then a mask pattern (not shown) is formed. The hard mask, the oxide, and the substrate 100 are etched using the mask pattern to form the grooves 110 and the cell holes 111. The groove 110 and the cell hole 111 are formed in the scribe lane and the cell region, respectively. The grooves 110 and the cell holes 111 may be formed using a dry etching method, a drilling method, a Bosch etching method, or a Steady State etching method. The grooves 110 and the cell holes 111 may extend to a depth not penetrating the substrate 100. [ The depths of the grooves 110 and the cell holes 111 can be changed by a design rule or device characteristics. After the grooves 110 and the cell holes 111 are formed, the mask pattern can be removed through an ashing and a strip process.

The first insulating film 122 may be formed in the grooves 110 and the cell holes 111. [ The first insulating layer 122 may be formed by depositing an insulating material such as a silicon oxide layer. The first insulating film 122 may be formed by, for example, an atomic layer deposition method or a chemical vapor deposition method.

A first barrier film 124 may be formed on the first insulating film 122. [ The first barrier film 124 may be formed along the inner surfaces of the grooves 110 and the cell holes 111 and may extend on the first side of the substrate 100. The first barrier layer 124 may be one or more stacked structures selected from among titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or double films of titanium / titanium nitride have. The first barrier film 124 may be formed by a sputtering method.

The second insulating film 126 may be formed on the first barrier film 124. [ The second insulating film 126 may be formed along the inner surface of the first barrier film 124 and may extend on the first surface of the substrate 100. The second insulating layer may be formed by depositing an insulating material such as a silicon nitride layer. The second insulating film 126 may be formed by, for example, an atomic layer deposition method or a chemical vapor deposition method.

The insulating layer 130 may be provided on the grooves 110 and the second insulating layer 124 in the cell holes 111 to fill the grooves 110 and the inside of the cell holes 111. [ The insulating layer 130 may extend over the first side of the substrate 100. The insulating layer 130 may be an insulating material such as silicon oxide or silicon nitride.

Referring to FIGS. 4A and 4B, a first test hole 112 and a second test hole 113 are formed in the groove 110. A mask pattern (not shown) is formed on the insulating layer 130. The insulating layer 130 and the second insulating layer 126 are etched using the mask pattern to expose the first barrier layer 124 in the cell hole 111. At the same time, the first test hole 112 and the second test hole 113 are formed by etching the insulating layer 130 and the second insulating film 126 in the groove 110 by using the mask pattern. At this time, the process of etching the cell holes 111 and the process of etching the first test holes 112 and the second test holes 113 can be performed at the same time. Although the first test hole 112 and the second test hole 113 are illustrated as being formed in the groove 110, three or more holes may be formed. The first test hole 112 and the second test hole 113 may expose the first barrier layer 124 through the insulating layer 130 and the second insulating layer 126. The thickness of the first barrier film 124 may be thinned by over-etching the cell holes 111 and the first and second test holes 112 and 113.

The cell holes 111 and the first and second test holes 112 and 113 may be formed using a dry etching method, a drilling method, a Bosch etching method, or a Steady State etching method.

Referring to Figs. 5A and 5B, a second barrier film 142 is formed. 5A, a second barrier film 142 is formed along the inner surfaces of the first test holes 112 and the second test holes 113 and extends toward the first surface of the substrate 100 . Referring to FIG. 5 (b), a second barrier film 142 may be formed on the first barrier film 124 and extend on the first side of the substrate 100.

The second barrier layer 142 may be one or more of a stacked structure selected from titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or a double film of titanium / titanium nitride have. The second barrier film 142 may be formed by a sputtering method.

A metal layer 144 may be provided on the second barrier layer 142 to fill the cell holes 111, the first test holes 112 and the second test holes 113. The metal layer 144 may extend on the first side of the substrate 110. The metal layer 144 may be formed using an electrolytic plating method, an electroless plating method, or a selective deposition method. In the electrolytic plating method, a seed film (not shown) is formed on the inner surfaces of the cell holes 111, the first test holes 112 and the second test holes 113 where the metal layer 144 is formed, And plating the material. The seed film may be a copper film formed by a sputtering method. The metal layer 144 may comprise silver, gold, copper, tungsten, or indium. In one embodiment, the electroplating method can be performed spoken bearing the substrate to electrolytic solution containing CuSO 4, H 2 SO 4, and Cl.

6A and 6B, a step of planarizing the first surface of the substrate 100 may be performed. In the planarization process, the second barrier layer 142 and the metal layer 144 may be etched to expose the first insulation layer 122. Thus, the cell TSV 140a, the first test TSV 140b, and the second test TSV 140c are formed in the cell hole 111, the first test hole 112, and the second test holes 113, respectively . The cell TSV 140a includes a first cell barrier pattern 124a, a second cell barrier pattern 142a and a first conductive pattern 144a, and the first test TSV 140b includes a second groove barrier pattern 142b And a second conductive pattern 144b and the second test TSV 140c may include a third groove barrier pattern 142c and a third conductive pattern 144c. The exposed first insulating layer 122 may have the same height as the first through third conductive patterns 144a, 144b, and 144c. For example, the etching process can be performed by chemical mechanical polishing (CMP).

After the planarization process is performed, an IMD (Intermetallic Dielectric) layer 152 may be formed. The IMD layer 152 may be a low dielectric constant material.

An insulating layer 154 may be formed on the IMD layer 152. The insulating layer 154 may be an insulating material such as silicon oxide or silicon nitride.

Referring to FIGS. 7A and 7B, a mask pattern (not shown) is formed on the insulating layer 154. The insulating layer 154 and the IMD layer 152 may be etched using the mask pattern to expose the first to third conductive patterns 144a, 144b, and 144c.

The cell pad 161, the first test pad 162 and the second test pad 163 may be respectively formed on the first to third conductive patterns 144a, 144b and 144c exposed by etching . The cell pad 161, the first test pad 162, and the second test pad 163 may include silver, gold, copper, tungsten, or indium. The first test pad 162 and the second test pad 163 are electrically connected to the second through third conductive patterns 144b and 144c, the second through third groove barrier patterns 142b and 142c, Pattern 124 may be electrically connected.

Although not shown in the drawings, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes etching a second surface of a substrate 100 to expose a lower surface of first through third conductive patterns 144a, 144b, and 144c And a lower pad (not shown) connected to the lower surface of the first to third conductive patterns 144a, 144b and 144c on the second surface of the substrate 100. [

According to the method for fabricating a semiconductor device according to the embodiment of the present invention, electrical testing of a silicon through electrode can be performed without going through a thinning process and a backside process on the second surface of the substrate 100 . 7A and 7B, the first test pad 162 is electrically connected to the first test TSV 140b, the second test pad 163 is electrically connected to the second test TSV 140c, Respectively. Thus, an electrical test can be performed through the first test pad 162 and the second test pad 163 of the scribe lane to monitor the electrical test of the cell TSV 140a in the cell region, thereby reducing the number of processes There is an advantage that the reliability of the silicon penetrating electrode can be secured.

8 is a plan view showing a package module 300 according to embodiments of the present invention. 8, the package module 300 includes a module substrate 302 having external connection terminals 308, a semiconductor chip 304 mounted on the module substrate 302, and a semiconductor chip 304 mounted on the module substrate 302, Package 306 may be included. The semiconductor chip 304 and / or the semiconductor package 306 may include a semiconductor device according to embodiments of the present invention. The package module 300 may be connected to an external electronic device through an external connection terminal 308. [

9 is a schematic diagram illustrating a memory card 400 in accordance with embodiments of the present invention. Referring to FIG. 9, the card 400 may include a controller 420 and a memory 430 in a housing 420. The controller 420 and the memory 430 may exchange electrical signals. For example, in accordance with a command of the controller 420, the memory 430 and the controller 420 can exchange data. Accordingly, the memory card 400 can store data in the memory 430 or output data from the memory 430 to the outside.

The controller 420 and / or the memory 430 may include at least one of a semiconductor device or a semiconductor package according to embodiments of the present invention. The memory card 400 may be used as a data storage medium of various portable devices. For example, the memory card 400 may include a multi media card (MMC) or a secure digital (SD) card.

10 is a block diagram illustrating an electronic system 500 in accordance with embodiments of the present invention. Referring to FIG. 10, the electronic system 500 may include at least one semiconductor device or semiconductor package according to embodiments of the present invention. The electronic system 500 may include a mobile device, a computer, or the like. For example, the electronic system 500 may include a memory system 512, a processor 514, a RAM 516, and a user interface 518, Communication can be performed. The processor 514 may be responsible for executing the program and controlling the electronic system 500. The RAM 516 may be used as an operating memory of the processor 514. For example, processor 514 and RAM 516 may each comprise a semiconductor device or semiconductor package according to an embodiment of the present invention. Or the processor 514 and the RAM 516 may be included in one package. The user interface 518 may be used to input or output data to the electronic system 500. The memory system 512 may store code for operation of the processor 514, data processed by the processor 514, or externally input data. The memory system 512 may include a controller and memory and may be configured substantially the same as the memory card 400 of FIG.

The electronic system (500 in FIG. 10) can be applied to an electronic control device of various electronic devices. 11 shows an example in which an electronic system (500 of Fig. 10) is applied to a mobile phone 600. Fig. Besides, the electronic system (500 in FIG. 10) can be applied to a portable notebook, an MP3 player, a navigation, a solid state disk (SSD), an automobile or household appliances.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

Claims (8)

Providing a substrate comprising a plurality of cell regions separated by a scribe lane;
Forming a groove in the scribe lane from a first surface of the substrate to a second surface opposite the first surface;
Sequentially forming a first insulating film, a first barrier film, and a second insulating film in the groove;
Forming first and second test holes through the second insulating film in the groove and exposing the first barrier film;
Sequentially forming a second barrier film and a metal layer in the first and second test holes; And
Forming a first test penetrating electrode and a second test penetrating electrode in the first and second test holes by etching the metal layer, the first and second barrier films to expose the first insulating film, Way. The method according to claim 1,
And forming first and second test pads on the first and second test penetration electrodes, respectively. 3. The method of claim 2,
Wherein the first and second test pads are electrically connected to the first and second test penetrating electrodes through the first barrier film. The method according to claim 1,
A cell hole is formed in the cell region from the first surface of the substrate to the second surface opposite to the first surface at the same time as the groove is formed;
The first insulating film and the first barrier film are formed in the cell hole;
The second barrier film and the metal layer are formed in the first barrier film; And
And a silicon penetrating electrode is formed in the cell hole by the etching process. 5. The method of claim 4,
And forming a cell pad on the silicon penetrating electrode. The method according to claim 1,
Wherein the first and second barrier layers are at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride or a double film of titanium / titanium nitride A method of manufacturing a semiconductor device. The method according to claim 1,
Wherein the first insulating film is silicon oxide and the second insulating film is silicon nitride. A cell hole from a first surface of the substrate to a second surface opposite to the first surface;
A first insulating film and a first barrier film sequentially provided in the cell hole; And
And a second barrier film and a conductive pattern sequentially provided in the first barrier film.
KR1020130092691A 2013-08-05 2013-08-05 Semicondctor devices and methods for fabricating the same KR20150016798A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170065419A (en) * 2015-12-03 2017-06-13 삼성전자주식회사 Semiconductor device and method for manufacturing the semiconductor device
CN111199930A (en) * 2018-11-20 2020-05-26 南亚科技股份有限公司 Semiconductor device and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170065419A (en) * 2015-12-03 2017-06-13 삼성전자주식회사 Semiconductor device and method for manufacturing the semiconductor device
CN111199930A (en) * 2018-11-20 2020-05-26 南亚科技股份有限公司 Semiconductor device and method for manufacturing the same
US11121062B2 (en) 2018-11-20 2021-09-14 Nanya Technology Corporation Semiconductor device and method for manufacturing the same

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