KR20150010472A - Power Rectifying Device - Google Patents

Power Rectifying Device Download PDF

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Publication number
KR20150010472A
KR20150010472A KR20130085554A KR20130085554A KR20150010472A KR 20150010472 A KR20150010472 A KR 20150010472A KR 20130085554 A KR20130085554 A KR 20130085554A KR 20130085554 A KR20130085554 A KR 20130085554A KR 20150010472 A KR20150010472 A KR 20150010472A
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KR
South Korea
Prior art keywords
gate
shape
substrate
channel layer
gate patterns
Prior art date
Application number
KR20130085554A
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Korean (ko)
Inventor
박건식
나경일
원종일
Original Assignee
한국전자통신연구원
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Priority to KR20130085554A priority Critical patent/KR20150010472A/en
Publication of KR20150010472A publication Critical patent/KR20150010472A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention discloses a power rectifying device. A power rectifying device according to the present invention includes a substrate, a source layer on the substrate, a channel layer on the source layer, gate patterns formed on the channel layer and separated from each other, gate insulating layers interposed between the gate patterns and the channel layer, and a drain formed in the channel layer interposed between the gate patterns. The gate patterns may be formed on a cell area of the substrate in one of a shape of a cross formed by combining lines having a wide line width and lines having a narrow line width with each other, a T-shape, a circular shape, a rectangular shape and an octagon shape and may be disposed to surround a peripheral region of the substrate in a ring shape.

Description

[0001] Power rectifying device [0002]

The present invention relates to a semiconductor device, and more particularly, to a power rectifying device for rectifying power.

Power rectifiers for high-voltage and high-power semiconductors are widely used as power supply and power converter, and p-n junction diodes and Schottky diode devices are mainly used. The pn junction diode has a low leakage current and good reliability even at high temperature. However, due to the large forward voltage or turn-on voltage (~ 0.7V) and current conduction characteristic due to minority carrier, reverse recovery time and other switching speeds are slow. On the other hand, the Schottky diode has advantages such as a reverse recovery time because it has a low forward voltage and a conduction characteristic by a majority carrier by using a suitable metal electrode, but the leakage current in the off- Further, there is a problem of lowering the reliability at the contact portion between the metal and the semiconductor at high temperature, so additional measures for suppressing the heat generation are needed.

RK Williams et al. In US Pat. No. 5,818,084 concurrently connect drains, gates, and bodies in a metal oxide semiconductor field effect transistor (MOSFET) structure as shown in FIGS. 1A and 1B, And a MOS type rectifier structure using a source as a cathode is proposed. Since the prior patent has lower turn-on voltage and more carrier conduction characteristics than a conventional MOS connection diode (forming an anode by connecting a drain and a gate to form a cathode by connecting a source and a body), the reverse recovery time is set to be a pn diode Faster, and has good characteristics of leakage current and high-temperature reliability.

However, since the power rectifying device of FIG. 1A forms a channel with the p-body by the lateral diffusion process, it is difficult to precisely control the channel length and the threshold voltage of the MOSFET. The trench-type large power rectifying device of FIG. 1B also forms a p-body by a deep diffusion process, so that it is difficult to precisely control the channel length and threshold voltage of the MOSFET, and the process is complicated.

APD Semiconductor, Inc. has proposed a method of fabricating a MOSFET having a short channel length (~ 0.2 μm or less) and various methods for easily controlling the threshold voltage in the power rectifier. In US Pat. No. 6,186,408, US Pat. No. 6,331,455 and US Pat. No. 6,420,225, a method of forming a short-length channel and p-body using a spacer is proposed. US Pat. No. 6,448,160 employs isotropic etching of photoresist to form a short- US 6,624,030, US 6,765,264 and US 6,979,861 proposed methods using an undercut having a slope by isotropic etching of an oxide film.

Also, Diodes Fabtech Inc. U.S. Patent No. 7,847,315 proposed in US Pat. No. 7,847,315 and US Patent Application No. 2009/0261427 proposed by PFC DEVICE Co. use an undercut method having an inclination by isotropic etching of oxide film as in US 6,624,030 of APD Semiconductor Inc.

The proposed patents include patterning for forming the guard ring 271, patterning for defining the field region 24, defining the gate electrode 23 as shown in FIG. 2A (US 2009/0261427 FIG. And at least four or more patterning steps including patterning for defining the metal electrode 25 are required.

A guard ring 271 with a deep junction depth in this structure is commonly used to withstand high reverse voltages in power devices. On the other hand, at an operating voltage of 100 V or less, the reverse voltage can be sustained only by the region junction of the body 272 without forming the guard ring 271 region. However, if the guard ring 271 having a deep junction depth is not advanced There is a problem that a breakdown occurs because the reverse voltage can not withstand the boundary portion (arrow mark) between the active region and the field region shown by an arrow in FIG. 2A.

Also, the proposed patents have a rectangular shape as shown in FIG. 2B in the gate shape of the power rectifier cell. When the cell width is increased by decreasing the gate width W, the forward voltage of the rectifying element It becomes a factor to increase the descent.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power rectifying device having a low forward voltage characteristic, a high switching speed, and a good leakage current characteristic.

According to an aspect of the present invention, there is provided a power rectifying device including: a substrate; A source layer on the substrate; A channel layer on the source layer; Gate patterns individually separated on the channel layer; Gate insulating films between the gate patterns and the channel layer; And a drain formed in the channel layer between the gate patterns. Here, the gate patterns may be formed in any one of a cross shape, a tessell shape, a circle shape, a rectangular shape, and an octagon shape in which a wide width and a narrow width are combined on a cell region of the substrate And may be arranged in a ring shape surrounding the peripheral region of the substrate.

As described above, according to an exemplary embodiment of the present invention, the power rectifying element includes various shapes of gates in which a wide line width and a narrow line width are combined in a cell. The coexistence of the wide and narrow linewidths of the gate reduces the JFET resistance and increases the cell density to reduce the forward voltage drop (VF). In addition, by overlaying the gate over the edge of the active region and the field region or placing the gate above the field region, the reverse voltage can be tolerated without a guard ring having a deep junction depth, thereby simplifying the process.

Therefore, the power rectification device according to the embodiment of the present invention has a forward voltage characteristic, a fast switching speed, and an excellent leakage current characteristic.

Figs. 1A and 1B are cross-sectional views showing a general rectifying device for large power.
2A is a cross-sectional view of a conventional power rectifying device having a guard ring.
2B is a plan view of a conventional power rectifying device having a rectangular gate.
3A is a plan view showing gates in a cell of a power rectifying element according to an embodiment of the present invention.
FIG. 3B is a sectional view taken along the line AB in FIG. 3A.
Figs. 3C to 3I are plan views showing power-regulating elements of various gate shapes according to the present invention.
4A and 4B are cross-sectional views showing a general MOS type power rectifying device.
4C to 4F are cross-sectional views showing the power rectifying device of the present invention.
5A to 5I are cross-sectional views sequentially illustrating a method of manufacturing a power rectifying device according to an embodiment of the present invention.
Figs. 5J and 5K are plan views of a power rectifying element formed according to the manufacturing method of Figs. 5A to 5K.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in different forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is to be understood that the phrase "comprises" and / or "comprising" used in the specification exclude the presence or addition of one or more other elements, steps, operations and / or elements, I never do that. In addition, since they are in accordance with the preferred embodiment, the reference numerals presented in the order of description are not necessarily limited to the order. The following embodiments are examples using an N-type substrate, and conversely, a P-type substrate may be used. In this case, all types of dopants may be opposite to each other.

3A is a plan view showing gates in a cell of a power rectifying element according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken on line A-B of FIG. 3A.

Referring to FIGS. 3A and 3B, the gate of the power rectifier according to the embodiment of the present invention has a structure in which a narrow line width a and a wide line width b are combined in a cell.

In order to increase the cell density in the power rectifier, it is advantageous that the gate line width is narrow. However, when the line width is narrow, there is a disadvantage that the forward current density is decreased due to the increase in resistance by the JFET resistance (R JFET ). In order to solve this problem, it is possible not only to increase the cell density but also to reduce the decrease of the forward current due to the JFET resistance by allowing the narrow gate line width and the wide gate line to coexist in the cell region.

Figs. 3C to 3I illustrate other embodiments of gate shapes of various shapes in which the narrow line width a and the wide line width b repeatedly coexist as described above. In each gate shape, a represents a narrow line width and b represents a wide line width.

3C shows a cross-shaped gate shape. 3A is a structure in which the convex corner portions in the structure of FIG. 3C are cut at an arbitrary angle (for example, 45 degrees), and the concave corner portions are added at an arbitrary angle (for example, 45 degrees).

FIG. 3D shows a structure in which cross-shaped gate shapes are arranged in a line and repeated.

FIG. 3E shows a structure in which convex corner portions in the structure of FIG. 3D are cut at an arbitrary angle (for example, 45 degrees). The concave corner portion is a structure attached at an arbitrary angle (for example, 45 degrees).

FIG. 3F shows a structure in which a tier-like gate shape is repeated.

FIG. 3G shows a structure in which convex corner portions in the structure of FIG. 3F are cut at an arbitrary angle (for example, 45 degrees). The concave corner portion is a structure attached at an arbitrary angle (for example, 45 degrees).

FIG. 3h shows a structure in which gates having a circular shape and a rectangular shape are repeated, and respective gates are connected to each other.

FIG. 3I shows a structure in which gates of an octagonal shape and a rectangular shape are repeated, and respective gates are connected to each other. The portion where the gate is not formed (drain portion) also has an octagonal shape.

3J shows that a portion where a gate is not formed (a drain portion) has a circular shape, and a gate is connected to a region except for an anode portion of a circular shape.

The above are embodiments for explaining the present invention for a gate shape repeatedly including a region having a narrow gate width and a region having a wide gate width. In addition, the gate shape is a (memory shape), c H (hitchhiker), and tool shape, their convex corners can be cut out, and the concave corners can include various shapes such as an attached structure.

In addition, the shape of the drain shown in FIG. 3H to FIG. 3J may have various structures such as a square, a hexagon, etc. in addition to a circular or octagonal shape.

Another aspect of the invention relates to edge termination of power rectifiers. The following embodiments are examples using an N-type substrate, and conversely, a P-type substrate may be used. In this case, all types of dopants are opposite to each other.

FIG. 4A shows a cross-sectional structure of a general N-channel MOS type power rectifier device. The N-Epi (102) wafer grown on the N + substrate 101 is used as the starting material. After the field oxide film 104 is grown, a patterning process for forming the P-guard ring 103 is performed, boron is ion-implanted, and a high-temperature heat treatment is performed to form a P-guard ring 103 having a deep junction depth. Next, the active region 113 in which the cell is to be formed is defined, and the gate insulating film 105 and the gate polysilicon 106 are successively grown and then patterned to form a gate pattern. Next, ion implantation and heat treatment of the P-body 1 (108) and the P-body 2 (107) are performed at the portion where the channel and the body are to be formed. In addition, ion implantation and heat treatment for forming N + drain 110 may be additionally performed. Finally, a metal electrode is deposited on the upper portion and etched to form an anode 111 electrically connected to the gate-drain-body, and a metal electrode is deposited on the backside of the substrate to form a cathode 112.

At least four lithography processes of P-Guardring, Active, Gate and Metal are required to fabricate the above-mentioned general type of MOS type power rectifiers, and Lithography for forming N + drain is needed if necessary. .

In the above structure, the P-Guardring 103 is a process necessary to withstand the reverse withstand voltage of the power rectifier. That is, in a state where a high voltage (+) is applied to the cathode, the edge portion of the power rectifier is most vulnerable to breakdown. To compensate for this, the P-Guardring 103 of the deep junction is formed to improve the reverse breakdown characteristic .

However, at a low operating voltage of 100 V or less, the guard ring 103 is not formed and the body region junction 107 can withstand the reverse voltage. However, the boundary between the active region and the field region Color arrows) can not withstand the reverse voltage and breakdown occurs.

In order to overcome such a problem and simplify the process, the present invention proposes a device structure in which a gate material overlaps on a boundary between an active and a field to thereby withstand a reverse withstand voltage without a P-guard ring.

That is, as shown in FIG. 4C, when the reverse voltage is applied, the depletion region 114 expands to the field region by locating the gate electrode 106 over the boundary portion between the active region 113 and the field region 104 And can withstand high reverse voltage without breakdown. It is important to select a proper distance (a) between the gate 106 and the field oxide film 104 located at the boundary portion in the above structure, and a has a value of 0 to 50 탆 according to the concentration of the N-Epi layer 102 .

On the other hand, FIG. 4D shows a cross-sectional structure in the case where the N + drain is not formed in the structure of FIG. 4C.

The outermost gate may be located only in the upper portion of the field region, not overlapping the active region 113 and the field region 104, as shown in FIG. 4E. The gate located above the field region 104 allows the depletion region to extend out of the cell upon application of a reverse voltage to dissipate the voltage to withstand a higher reverse voltage. The outermost gate located above the field region may be composed of a plurality of gates separated by a certain distance. FIG. 4F shows a cross-sectional structure of a structure of FIG. 4E in which N + drain is not formed.

On the other hand, the outermost gate has a gate electrode 106 overlaid on the boundary portion between the active region 113 and the field region 104 described in FIGS. 4C and 4D, and a gate electrode 106 overlying the field region described in FIGS. 4E and 4F. Or a combination of a plurality of gates.

A method of manufacturing a power rectifying device according to an embodiment of the present invention will be described.

5A to 5I are cross-sectional views sequentially illustrating a method of manufacturing a power rectifying device according to an embodiment of the present invention. Figs. 5J and 5K are plan views of a power rectifying element formed according to the manufacturing method of Figs. 5A to 5K.

5A, a field oxide 104 is grown to a thickness of 100 to 1000 nm on an N-epitaxial layer 102 formed on an N + substrate 101, and then a P- The guardring region 103 is defined and the oxide film is etched. Then, boron ions are implanted and diffused into a heat treatment process to form a deep-depth junction. The P-guard ring forming process can be skipped in a power device fabrication process of 100 V or less.

In the following drawings, the case where the P-guardring process is skipped will be described.

Referring to FIG. 5B, an active region 113 is defined by using a mask and the oxide film is etched.

Referring to FIG. 5C, a gate dielectric 105, a gate material 106, and an oxide film 109 are continuously formed. The gate insulating film 105 may be a silicon oxide film, and the gate material 106 may be polysilicon.

Referring to FIG. 5D, the oxide film 109 is etched after the photoresist 115 in the portion where the gate electrode portion is to be formed is patterned by a photolithography process.

Referring to FIG. 5E, the oxide film 109 is etched by an isotropic etching (for example, a wet etching) process so that an undercut of the oxide film is formed in a region where a channel is to be formed.

Referring to FIG. 5F, the gate material 106 is etched and boron ion implantation is performed to form a P-body 2 (107) at a deep depth. On the other hand, the ion implantation process for forming the P-body 2 may be performed before the gate material 106 is etched or before the isotropic oxide film etch of FIGS.

Referring to FIG. 5G, boron or BF 2 is ion-implanted to form P-body 1 108 at a portion where a channel is to be formed after removal of the photoresistor 115, and a heat treatment process for activating the dopant is performed.

Referring to FIG. 5H, the gate insulating film 105 and the oxide film 109 are etched. At this time, the oxide film 109 may not be completely removed.

5I, a metal is formed on the upper part of the element to form the anode 111, and a metal is formed on the lower part of the substrate to form the cathode 112. [ Meanwhile, ion implantation and heat treatment such as phosphorus or arsenic ion implantation for N + drain formation can be performed as illustrated in FIGS. 4C and 4E before metal formation.

FIGS. 5J and 5K show an embodiment of the power device according to the present invention, wherein FIG. 5J corresponds to a case where a P-guard ring is present and FIG. 5K corresponds to a case where there is no P-guard ring.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

101: N + substrate 102: N-Epi
103: P-Guardring 104: field area
105: gate insulating film 106: gate polysilicon
107: P-body2 108: P-body1
109: oxide film 110: N + Drain
111: Anode 112: Cathode
113: active region 114: depletion region
115: Photoresist

Claims (1)

Board;
A source layer on the substrate;
A channel layer on the source layer;
Gate patterns individually separated on the channel layer;
Gate insulating films between the gate patterns and the channel layer; And
And a drain formed in the channel layer between the gate patterns,
The gate patterns may have any one of a cross shape, a teardrop shape, a circular shape, a rectangular shape, and an octagon shape in which a wide width and a narrow width are combined on a cell region of the substrate And arranged in a ring shape surrounding the substrate peripheral region.
KR20130085554A 2013-07-19 2013-07-19 Power Rectifying Device KR20150010472A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11452705B2 (en) 2017-06-12 2022-09-27 Icure Bnp Co., Ltd. Oral drug delivery composition containing oxaliplatin and method for preparing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11452705B2 (en) 2017-06-12 2022-09-27 Icure Bnp Co., Ltd. Oral drug delivery composition containing oxaliplatin and method for preparing same

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