KR20150009823A - Method of predicting computer processor performance and method of adjusting frequency using the method - Google Patents

Abstract

According to an embodiment of the present invention, a method for predicting a change in the performance of a computer processor according to dynamic voltage and frequency scaling (DVFS) comprises the steps of: calculating a stop state time (T_stall(f)) at the processor operating speed (f); and calculating the total run time (T_total(f)) based on the calculated stop state time, wherein the stop state time (T_stall(f)) is a duration when the calculation operation of the processor is stopped until a response comes back from the main memory of a computer.

Description

TECHNICAL FIELD The present invention relates to a method for predicting a performance change of a computer processor according to dynamic voltage and frequency scaling (DVFS) and a method for adjusting the speed of a processor using the same,

The present invention relates to a method for predicting a processor performance change and a method for controlling a speed of a processor, and more particularly, to a method for predicting a performance change of a processor by dynamically estimating a load execution time according to a current processor operation speed, To a method for predicting the performance change of a computer processor according to dynamic voltage and frequency scaling (DVFS), and a method for controlling the speed of processor operation using the same.

Dynamic Voltage & Frequency Scaling (DVFS) is a technology that dynamically adjusts the speed of a computer processor. Generally, the lower operating speed of a processor can be driven at a lower voltage. Lowering the voltage helps reduce power consumption, so that the voltage can be adjusted to be lowered simultaneously when the operating speed is lowered. As such, DVFS is used to reduce power consumption under given conditions by adjusting the processor voltage and operating frequency (operating speed).

The relationship between the operating frequency of the processor and the power consumption can be represented as shown in FIG. FIG. 1 is a graph showing a relationship between execution time, power consumption, and power consumption according to the operation speed of the processor. Referring to FIG. 1 (a), when the DVFS level becomes high (that is, The processing speed is increased and the execution time is reduced, but the power W to be used is increased. Conversely, if the DVFS step is lowered (ie, the operating frequency is lowered), the power used is reduced but the execution time is increased.

Generally, the power consumption (Wh) of the processor is a product of the power (W) and the time (h), and is defined as follows.

Since the power of the processor and the execution time of the processor according to the operating frequency are the same as those of the graph of FIG. 1 (a), the power consumption of the processor according to the operating frequency is expressed by the graph of FIG. That is, as the frequency increases, the power consumption gradually decreases, and the power consumption increases again from a certain frequency.

However, this pattern of power consumption depends on the nature of the workload (e.g., program) being executed by the processor. In the case of memory intensive workload, the bandwidth of the memory controller becomes a bottleneck, so even though lowering the DVFS level of the processor, execution time is longer than processor intensive workload It does not. The power increases proportionally to the DVFS phase, but the variation in the runtime is not always proportional to the change in DVFS, as it is affected by the characteristics of the workload.

Therefore, there is a need for a method that can dynamically predict the execution time of the workload according to the operating speed of the current processor and thereby reduce the power consumption.

According to an embodiment of the present invention, there is provided a method of dynamically checking the state of a main memory bandwidth and predicting a load execution time according to the DVFS step.

According to an embodiment of the present invention, there is provided a method of predicting a DVFS step-by-step power consumption amount from a predicted load execution time and thereby adjusting a processor operation speed to have a minimum power consumption amount.

According to an embodiment of the present invention, there is provided a method of predicting the performance change of a computer processor according to dynamic voltage and frequency scaling (DVFS), comprising: calculating a stop state time T _stall (f) at a processor operation speed f step; And calculating a total execution time (T _total (f)) based on the stop state time, wherein the stop state time (T _stall (f) And a time for stopping the calculation operation of the processor.

According to one embodiment of the present invention, in the operation timing of the computer processor, the method according to the dynamic voltage and frequency scaling (DVFS), the total running time (T _total (f)) of the processor by the processor performance impact prediction method Calculating; Calculating a power consumption amount of the processor according to the operation speed (f) based on the total execution time (T _total (f)); And estimating an operation speed having a minimum power consumption amount from the calculated power consumption amount.

According to an embodiment of the present invention, a computer-readable recording medium having recorded thereon a program for causing the computer to execute the method may be provided.

According to an embodiment of the present invention, it is possible to dynamically check the state of the main memory bandwidth and estimate the execution time of the load according to the DVFS step.

According to an embodiment of the present invention, there is an advantage in that it is possible to predict the DVFS step-by-step power consumption amount from the execution time of the predicted load, thereby adjusting the processor operation speed to have the minimum power consumption amount.

1 is a graph showing a relationship between execution time, power consumption, and power consumption according to the operating speed of a computer processor,
FIG. 2 is a flowchart illustrating a method of predicting a performance change of a computer processor according to an embodiment of the present invention and a method of adjusting a processor operation speed according to an embodiment of the present invention.
3 is a diagram for explaining a processor execution operation,
FIG. 4 is a graph for explaining the response time change of the main memory device according to the traffic of the main memory device and the operation speed of the processor,
FIG. 5 is a flowchart for explaining a method of obtaining a stop state time (T _stall (f)) according to an embodiment,
FIG. 6 is a view for explaining the flow chart of FIG. 5,
FIG. 7 is a diagram for explaining a pseudo code corresponding to the flowchart of FIG. 5,
FIG. 8 is a diagram illustrating a result of a performance change prediction test when the processor operation speed is adjusted according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content.

Where the terms first, second, etc. are used herein to describe components, these components should not be limited by such terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The singular forms herein include plural forms unless the context clearly dictates otherwise. The terms "comprise" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

Herein, the operation speed of the processor is referred to as "operation speed "," operation frequency ", or "frequency"

Hereinafter, the present invention will be described in detail with reference to the drawings. Various specific details are set forth in the following description of specific embodiments in order to provide a more detailed description of the invention and to aid in understanding the invention. However, it will be appreciated by those skilled in the art that the present invention may be understood by those skilled in the art without departing from such specific details. It should also be mentioned in advance that it is common knowledge in the description of the invention that the parts which are not largely related to the invention do not describe to prevent confusion in explaining the invention.

In one embodiment of the present invention, a method for dynamically checking the state of main memory bandwidth and predicting the execution time of a workload according to the DVFS step is provided. The present invention also provides a method for predicting the power consumption of the DVFS step by step from the execution time of the predicted work load, thereby adjusting the operation speed of the processor to have the minimum power consumption.

For example, FIG. 2 illustrates an exemplary flow chart for performing a performance change prediction and a processor operation speed adjustment method according to DVFS in a computer system.

2, for predicting the performance change of a computer processor according to dynamic voltage and frequency scaling (DVFS), calculating a total execution time of the processor (S110) and calculating a power consumption of the processor according to the processor operation speed Step S120 may be included.

First, in step S110, the total execution time T _total (f) of the processor for executing a predetermined work load (program) is calculated. As will be described later with reference to FIG. 2, the total execution time (T _total (f)) can be calculated by calculating the calculation state time and the stop state time of the processor, respectively.

Then, in step S120, based on the calculated total execution time T _total (f), the power consumption amount of the processor according to the operating speed of the processor is calculated. That is, the values corresponding to the execution time graph are calculated in FIG. 1 (a) through step S110, and the power according to the operating frequency can be determined through measurement. Therefore, The power consumption according to the operating frequency can be calculated.

The present invention may also include a method of adjusting the operation speed of the computer processor according to the DVFS based on the power consumption calculated in the step S120. For this, step S130 of estimating an operation speed having a minimum power consumption from the power consumption calculated in step S120, and operating the processor with the operation speed predicted with the minimum power consumption (S140) As shown in FIG.

Hereinafter, a method of calculating the total execution time T _total (f) according to an embodiment will be described with reference to FIG. 3 to FIG.

1. Total Run Time T _total (f)

In order to predict the performance change of the processor according to the present invention, the total execution time (T _total (f)) required for the processor to perform a specific work load at an arbitrary operation speed (f) must be obtained.

3 is a diagram for explaining a processor execution operation, and shows an execution model of a general processor.

Referring to FIG. 3, the execution time of a workload can be divided into two alternating states, "compute" and "stall." The processor remains in the "calculated" state while processing the prepared instructions. The processor in the computational state requests the necessary data from the main memory (memory) while processing the instruction, and changes from the computational state to the stopped state when all the prepared instructions are exhausted. The processor in the stopped state waits until a response is returned from the main memory. When a response is returned from main memory, the processor immediately begins processing the next instruction and changes to the calculated state. Accordingly, it can be seen that the processor repeats the calculation state and the stop state repeatedly, as shown in Fig.

Based on this processor operation, the total execution time (T _total (f)) of the processor in an embodiment of the present invention is expressed as:

Where T _comp (f) is the computation state time at the operation speed (f), and T _stall (f) is the time required for the processor to execute the given work load. Is the time to stop the processor's computation until a response is returned from the processor.

In order to know the total execution time T _total (f) according to the operation speed f of the processor, the calculation state time T _comp (f) according to the operation speed f and the stop state time T _stall (f), respectively.

2. Calculation state time T _comp (f)

The number of cycles the processor spent in the computation state to process an instruction does not change even if the processor's operating speed, f, changes. Therefore, the calculation state time according to the operation speed (f) can be expressed by Equation (3).

Where C _comp is the number of cycles required to compute a given workload, which is easily derived when the workload is specified regardless of the operating speed (f).

3. Stopped state  time T _stall (f)

The pause state time is the amount of time that the processor stops counting until a response is returned from the computer's main memory. The pause state time is proportional to the memory latency (hereinafter also referred to as "main memory response time").

However, since the main memory response time varies depending on the traffic of the main memory and the operation speed (f) of the processor, it should be considered. In this regard, FIG. 4 is a graph for explaining the response time change of the main storage device according to the traffic of the main memory device and the operation speed f of the processor. In the Intel Xeon E5-2670 processor, It shows the change of the main memory response time according to the device traffic.

As can be seen from the figure, while the main memory traffic value of the X axis increases to a certain point, the response time of the main memory of the Y axis does not substantially change, but the response time increases sharply beyond this point. Also, it can be seen that the response time of the main memory is increased when the operation speed (f) of the processor is slowed down.

Since the stop state time T _stall (f) is proportional to the main memory response time and the main memory response time is a function of the main memory traffic Rf and the operation speed f of the processor, And the stop state time T _stall (f) as shown in Fig.

Where T _stall (f ₀₎ is the stop state period at the reference operation rate _{(f 0), Latency (f} , Rf) is the main memory unit in a main storage device response time operating speed (f) and the operating speed (f) a function of traffic _{(Rf), Latency (f 0} , R 0) is the response time from the reference operation rate (f _0). Based on the operation speed of the time (f ₀₎ may be any operating speed of a known value, for example, it can be set to, based on the current operating speed of the operating speed (f _0).

In this case, since the latency (f, Rf) is a function of each operation speed f and the main memory traffic Rf, it is expressed as shown in the graph of FIG. 4, It is assumed that the measured value is a known value. That is, it is presumed in FIG. 4 that the value (response time) of the Y-axis coordinate with respect to the value of the X-axis coordinate (main memory device traffic Rf) is stored in advance for each operation speed f. To this end, in one embodiment, this value may be obtained by mathematical modeling, or alternatively, a response speed value according to main memory traffic Rf at each operating speed f may be measured and stored in advance have. When the latter method is used, the response time of the main memory device is directly measured with respect to the operation speed which can be taken and the interval value of the main memory device traffic, and a characteristic function is created. The interpolation method is applied to the non- The graph value as shown in FIG. 4 can be calculated. However, this is an exemplary method, and it is needless to say that the main memory response time for each operation speed f and the traffic Rf can be obtained by using another method.

Meanwhile, in order to calculate the stopping state time (T _stall (f)) in Equation (4), the main memory traffic Rf according to the operation speed f must be known, and this traffic value is also changed according to the operation speed f Function.

In an embodiment of the present invention, the main memory traffic Rf is defined as a value obtained by dividing the total amount of data sent and received by the total execution time. Accordingly, the main memory traffic Rf at an arbitrary operation speed f is Can be expressed as Equation 5. " (5) "

Where N _data represents the total amount of data exchanged between the main memory and the processor when a given workload is executed. For example, N _data includes all kinds of data transfer to and from the main memory, and includes data loading, writeback, and prefetch as shown in FIG. 3, Does not change with the operation speed (f) of the processor.

Referring back to Equation 4, the reference operation speed (for example, the current operation speed) f ₀ , the main memory traffic R _{0 at} this time, and the time T _stall (f ₀ ) It can be easily measured with a counter.

However, in order to obtain the stop state time (T _stall (f)) according to the arbitrary operation speed (f) in Equation (4), it is necessary to know the main memory traffic Rf according to an arbitrary operation speed f, In order to obtain this traffic Rf, it is necessary to know the stop state time (T _stall (f)). That is, it can be seen that the stop state time (T _stall (f)) is a kind of recursive function.

In one embodiment of the present invention, a Nested Interval Theorem can be used to calculate the stop state time (T _stall (f)) from Equations (4) and (5). However, it is a matter of course that the narrowing-down theorem is one of various methods for solving such a recursive function problem, and the present invention is not limited to this method. Hereinafter, an exemplary method for obtaining the stop state time (T _stall (f)) by the reduced interval theorem will be described with reference to FIG. 5 and FIG.

FIG. 5 is a flowchart for explaining a method of determining a stop state time (T _stall (f)) by a reduction interval correction according to an embodiment, and FIG. 6 is a diagram for explaining the method of FIG.

The key to the reduction algorithm is to reduce the range in which variables can exist by repeating calculations. In the illustrated embodiment, the value of the main memory traffic Rf is determined by the iterative calculation, and the value of the traffic Rf is substituted into the equation 4 to finally obtain the stop state time T _stall (f).

In order to set the number of iterative calculations, k = 1 is set in step S210. Where k is an integer for counting the number of repetitions. Thereafter, in step S220, a range [R _left , R _right ] that the main memory traffic Rf can have is set. As an initial value of this range, it can be assumed that R _left is 0 and R _right is infinity (see Fig. 6 (a)).

Next, in step S230, R _input , which is an initial estimated value of the main memory traffic Rf, is selected. This initial value can be any value. In one embodiment, it is possible to select R _input = R ₀ x T _comp (f) / T _comp (f ₀ ) as the initial value, assuming that the response time of the main memory is constant.

Next, this initial value (R _input ) is substituted into Equation 4 to calculate T _stall (f), and the calculated T _stall (f) is substituted into Equation 5 to calculate R _output , which is a new traffic (Rf) estimation value Steps S240, S250 and Fig. 6 (b)).

Thereafter, in step S260, the R _input used as the _input of Equation 4 and the R _output obtained by substituting the Equation 5 are compared in the previous steps S240 and S250, and these two values are equal to or different from each other (D), if it is within the predetermined range (D), the R _output is substituted into the equation (4) in step S270 to determine the final stop state time (T _stall .

However, if it is determined in step S260 that R _input and R _output If the difference between the values exceeds the predetermined range (D), the calculation step (S240, S250) is repeated.

To this end, it is first checked in step S280 whether the number of repetitions has reached a predetermined number N (N is an integer of 2 or more). If the number of repetitions has not yet reached the predetermined number N, the process proceeds to step S300, And resets the range [R _left , R _right ] in which the device traffic Rf may exist. Preferably, the R _input and the R _output obtained in the previous step are reset to the upper and lower limits of the range [R _left , R _right ], respectively. That is, a smaller value among R _input and R _output is set as R _left, and a larger value is set as R _right (refer to FIG. 6 (c)). Next, in step S310, the R _input , which is a predicted value of the traffic Rf, is also selected again. In one embodiment, the intermediate value of the newly set range [R _left , R _right ] may be selected as a new predicted value (R _input ) in step S300.

Thereafter, the process returns to steps S240 and S250, and a new R _output is obtained by using the equations 4 and 5 (refer to FIG. 6 (d)). In step S260, the newly obtained R _input is compared with the R _output It is determined whether the routine is repeated or terminated. If the routine is repeated again, the upper and lower values of the current R _input and R _output are reset to the lower limit (R _left ) and the upper limit (R _right ), respectively, as shown in FIG. 6 (e).

Since the R _input is determined as the average value of R _left and R _right whenever the calculation is repeated, the range that the main memory traffic (Rf) can have is always monotonically decreased, (Rf) converges finally to a single value. However, since it may take a long time to converge to a single value, it is determined whether the difference between the R _input and the R _output is within a specific range D in step S260. If the range is within the range D, _Output value is used to calculate the stop state time (T _stall (f)).

The operation according to the flowchart of FIG. 5 described above can be expressed by the pseudo code as shown in FIG. FIG. 7 illustrates the flow chart of FIG. 5 in an exemplary pseudocode.

Referring to FIG. 7, the fourth row of the pseudo code corresponds to step S220 of FIG. 5 and sets a range [ _R.sub.left , _R.sub.right ] that the main memory traffic Rf can have. The fifth line of the pseudo code corresponds to step S230 and selects R _input which is an initial estimated value of the main memory traffic Rf.

The seventh and eighth rows of the pseudo code respectively correspond to the calculation steps (S240 and S250), the ninth row corresponds to the R _input and the R _output Corresponding to the step S260 of comparing the values.

R [the _left , R _right ] in which the main memory traffic Rf can exist in the 12th and 13th rows of the pseudo code, and the 14th row of the pseudo code resets the range [R _left , R _right ] And the intermediate value is selected as a new predicted value (R _input ). Also, in this pseudo-code, the number of iterations of the calculation is limited to a maximum of 10, and the error range of Rf is set to 5%.

4. Total Run Time T _total (f)

The performance of the processor is limited not only by the main memory latency but also by the maximum bandwidth of the main memory depending on the operation speed f of the processor. When the bandwidth of the main memory is saturated, the total execution time (T _total (f)) can not be faster than the time (T _memory (f)) for exchanging data with the main _memory . In one embodiment, the minimum time required to transmit data may be expressed as: < EMI ID = 6.0 >

Here, Bandwidth (f) is a function indicating the maximum bandwidth of the main memory when the operation speed is f (hereinafter also referred to as "maximum bandwidth function"). It can be assumed that the value of this maximum bandwidth function is stored in advance as a known value. Similar to the response time function Latency (f, Rf) described with reference to equation (4), the maximum bandwidth function can also be found by mathematical modeling and, alternatively, at each operating speed f, The value can be measured and stored in advance.

Finally, when considering the lower limit value of the total execution time (T _total (f)) of Equation 6, the total execution time for processing the work load when the operation speed of the processor is f can be expressed by Equation (7).

5. Prediction of operating speed with minimum power consumption

As described above, if the total execution time (T _total (f)) is calculated, the performance change of the processor can be predicted based on this, and the optimal DVFS step can be predicted in terms of energy consumption by workload. That is, as described with reference to Fig. 2, when the total execution time T _total (f) of the processor is calculated, then the total execution time T _total (f) and the operation speed f are calculated in step S120 It is possible to calculate the power consumption of the processor according to the operation speed f, so that it is possible to know a performance change according to each operation speed f.

At this time, the total execution time at each operation speed f is a value calculated by the above-described Expression 7, and the power according to the operation speed f can use a previously known measurement value. Generally, the power according to the operation speed (f) does not depend on the program but is a characteristic of the hardware, so it can be measured in advance regardless of the program being executed.

Also, according to an embodiment of the present invention, a processor can be executed in an optimal DVFS step using predicted values of processor performance changes. That is, the operation speed f having the minimum power consumption amount from the power consumption amount calculated by the operation speed calculated in the step S120 of FIG. 2 (step S130), and the operation speed having the smallest power consumption amount among the estimated power consumption amount (Step S140). The operating speed at this time is the optimal DVFS step for the processor to process the workload.

6. Experimental Results

The method of predicting the processor performance change according to the DVFS step according to the above embodiment is evaluated as shown in FIG. Experiments were conducted using two Intel Xeon E5-2670 8-core processors and 128GB of memory. All kinds of prefetchers on the processor were activated and hyper threading was disabled. The operating system used Ubuntu 12.04 with Linux kernel 3.2, and the virtualization environment used KVM.

The virtual machine was allocated a virtual processor and 2GB of memory, and each virtual machine was assigned to a dedicated core. In order to evaluate the DVFS performance change prediction method, a method according to an embodiment of the present invention is used to predict a point where the performance of each program is lowered by 3%, 5%, 10%, 20% And the actual performance measurements for each case are plotted. The operating speed of the processor is changeable from 1.2 GHz to 2.6 GHz. Execution time and processor operation speed were measured while simultaneously executing eight identical benchmark programs, and the results are shown in FIGS. 8 (a) and 8 (b).

Figure 8 (a) shows the performance degradation rate of each program for each of the total 29 programs compared to when the processor was set at the fastest rate. The rightmost graph (denoted as "g-mean") in FIG. 8 (a) represents the average value of each value for all 29 programs on the left hand side. And Figure 8 (b) shows the average operating speed of the processor for each case.

In the graph of FIG. 8 (a), the left side shows relatively memory-intensive programs and the right side shows relatively CPU-intensive programs. The performance degradation ratio is not significantly different, but the average operation speed is memory- Can be seen to be relatively low. However, FIG. 8 (a) and FIG. 8 (b) show that the overall performance of the processor is well predicted according to the operating speed of the processor.

Although the present invention has been described with reference to the preferred embodiments and drawings, the present invention is not limited to the above embodiments. Therefore, it is to be understood that various modifications and changes may be made by those skilled in the art to which the present invention pertains. The scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims (9)

A method for predicting a performance change of a computer processor according to dynamic voltage and frequency scaling (DVFS)
Calculating a stop state time (T _stall (f)) at the processor operating speed (f); And
And calculating a total execution time (T _total (f)) based on the stop state time,
Wherein the stop state time (T _stall (f)) is a time to stop the computing operation of the processor until a response is returned from the main memory of the computer. The method according to claim 1,
Characterized in that the total execution time (T _total (f)) is the sum of the calculated state time (T _comp (f)) taken to execute a given workload and the _stall state time (T _stall How to predict performance change. The method according to claim 1,
Wherein the stop state time (T _stall (f)) is determined based on a response time (Latency) and main memory traffic (Rf) according to the operation speed (f) The method of claim 3,
The stop state time (T _stall (f)) is defined by the following first equation,

Here, T _stall (f ₀₎ is the stop state period at the reference operation rate _{(f 0), Latency (f} , Rf) is a main memory traffic on the operating speed (f) and the operating speed (f) (Rf) And the latency (f ₀ , R ₀ ) represents the response time at the reference operation speed (f ₀ ). 5. The method of claim 4,
The traffic Rf of the main memory is defined by the following second formula,

Where N _data represents the total amount of data exchanged between the main memory and the processor during execution of a given workload. 6. The method of claim 5, wherein the stop state time (T _stall (f)) is calculated from the first and second expressions using Nested Interval Theorem. A method for adjusting the operating speed of a computer processor according to dynamic voltage and frequency scaling (DVFS)
Calculating a total execution time (T _total (f)) of the processor by the processor performance change prediction method according to claim 1;
Calculating a power consumption amount of the processor according to the operation speed (f) based on the total execution time (T _total (f)); And
And estimating an operation speed having a minimum power consumption amount from the calculated power consumption amount. 8. The method of claim 7,
Further comprising: operating the processor at the predicted operating speed with a minimum power consumption. A computer-readable recording medium having recorded thereon a program for causing a computer to execute the method according to any one of claims 1 to 8.

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