KR20150009328A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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KR20150009328A
KR20150009328A KR1020130083688A KR20130083688A KR20150009328A KR 20150009328 A KR20150009328 A KR 20150009328A KR 1020130083688 A KR1020130083688 A KR 1020130083688A KR 20130083688 A KR20130083688 A KR 20130083688A KR 20150009328 A KR20150009328 A KR 20150009328A
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South Korea
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emitter
region
well region
type
metal
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KR1020130083688A
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Korean (ko)
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서동수
엄기주
장창수
송인혁
박재훈
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삼성전기주식회사
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Publication of KR20150009328A publication Critical patent/KR20150009328A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention relates to a power semiconductor device which includes a first conductivity type drift layer; a well region formed by injecting a second conductivity type impurity to the upper part of the drift layer; an emitter region which is formed by injecting the first conductivity type impurity to the upper part of the well region and has a separated shape from the drift layer; a gate which is formed in parts of the upper surface of the well region and is formed to cover the boundary of the wall region and the drift layer from the boundary of the well region and the emitter region; a first emitter metal which is formed on the upper surface of the emitter region and is in ohmic contact with the emitter region; and a second emitter metal which is formed on the upper surface of the well region and is in ohmic contact with the well region.

Description

[0001] Power semiconductor device [0002]

The present invention relates to a power semiconductor device having a low contact resistance in an emitter region.

Generally, a power semiconductor device is widely used as a control device of a motor or various kinds of switching devices such as an inverter.

Specifically, a power semiconductor device means a semiconductor device used in a power device, and is a core of a power device optimized for power conversion and control.

And is characterized in that it has a higher internal voltage, a higher current, and a higher frequency of hydration than a general semiconductor device.

Typical types of power semiconductor devices include metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

The IGBT and the MOSFET have basically npn type structure. That is, since the diode is in the form of npn and two rectifying directions are opposite to each other, the current does not flow.

However, when a positive voltage is applied to a gate formed in a form insulated from the p-type semiconductor region by using an oxide, electrons present in the p-type semiconductor region are attracted, and thus, the p- A conductive channel is formed at the contact portion.

Through the conductive channel, a current flows between the emitter and the collector or between the source and the drain.

In particular, an IGBT refers to a transistor having a bipolar transistor by forming a gate using a MOS (Metal Oxide Semiconductor) and forming a p-type collector layer on the rear surface.

IGBTs feature low forward loss and fast switching speeds and are applied to fields that were not possible with conventional thyristors, bipolar transistors, and MOSFETs (Metal Oxide Semiconductor Field Emitting Transistors). This trend is expanding.

When the IGBT is turned on, a voltage higher than the cathode is applied to the anode, and when a voltage higher than the threshold voltage of the device is applied to the gate electrode, The polarity of the surface of the p-type body region located at the lower end of the p-type body region is reversed and an n-channel is formed.

The electron current injected into the drift region through the channel is injected from the high concentration p-type collector layer located under the IGBT element in the same manner as the base current of the bipolar transistor. Inducing current injection.

Concentration implantation of such a small number of carriers causes conductivity modulation in which the conductivity in the drift region increases by several tens to hundreds of times.

Unlike a MOSFET, the resistance component in the drift region becomes very small due to the conductivity modulation, so that it can be applied at a very high voltage.

The current flowing to the cathode is divided into the electron current (ie) flowing through the channel and the hole current (ih) flowing through the junction of the p-type body and the n-type drift region.

That is, in the case of an electron current, the current flows through the channel to the emitter metal contacting the n-type emitter layer, and in the case of the hole current, flows to the emitter metal in contact with the p-type well layer.

However, since p-type and n-type semiconductors have different metals that can make ohmic contacts, in the conventional case, since the contact is formed by one metal, at least one of the p-type semiconductor and the n- Can be a resistance component.

For example, when a contact is formed by forming titanium (Ti) / titanium nitride (TiN) as a barrier metal and then stacking aluminum (Al), titanium (Ti) the contact resistance is obtained for the n-type semiconductor region, but the contact resistance is relatively high for the p-type semiconductor region.

As described above, in the case of having a high contact resistance, the performance of the device can be deteriorated. Thus, a method for reducing the contact resistance is needed.

Patent Document 1 described in the following prior art document is an invention related to a semiconductor device.

The invention described in Patent Document 1 is an invention in which an increase in on-voltage is suppressed to improve the latch-up capacity of an IGBT. Specifically, the invention disclosed in Patent Document 1 is characterized in that the n-type emitter region is electrically connected to the metal film through an intervening layer which operates as a resistor, thereby preventing latch-up. That is, the present invention differs from the present invention in that resistance is lowered by forming different metals in the n-type emitter region and the p-type well region.

Korean Patent Laid-Open Publication No. 1990-0019261

The present invention seeks to provide a tangential power semiconductor device in which the emitter metal and the emitter layer have low contact resistance.

A power semiconductor device according to an embodiment of the present invention includes a drift layer of a first conductivity type; A well region of a second conductivity type formed on the drift layer; A first conductivity type emitter region formed on the well region and separated from the drift layer by the well region; A gate formed to cover a boundary between the drift layer and the well region from a boundary between the emitter region and the well region; A first emitter metal formed on an upper surface of the emitter region and ohmically contacting the emitter region; And a second emitter metal formed on the upper surface of the well region and ohmically in contact with the well region.

In one embodiment, when the first conductivity type is n-type, the first emitter metal may be titanium (Ti).

In one embodiment, when the second conductivity type is p-type, the second emitter metal may be aluminum (Al).

In one embodiment, the second emitter metal may cover the first emitter metal.

A power semiconductor device according to another embodiment of the present invention includes a drift layer of a first conductivity type; A well region of a second conductivity type formed on the drift layer; A first conductivity type emitter region formed on the well region and separated from the drift layer by the well region; A gate formed to penetrate from the well region to a portion of the drift layer, the gate having the emitter regions located on both sides thereof; A first emitter metal formed on an upper surface of the emitter region and ohmically contacting the emitter region; And a second emitter metal formed on the upper surface of the well region and ohmically in contact with the well region.

In another embodiment, when the first conductivity type is n-type, the first emitter metal may be titanium (Ti).

In another embodiment, when the second conductivity type is p-type, the second emitter metal may be aluminum (Al).

In another embodiment, the second emitter metal may cover the first emitter metal.

The power semiconductor device according to the present invention is characterized in that the first emitter metal formed on the upper surface of the n-type emitter region and the second emitter metal formed on the upper surface of the p-type well region are formed differently from each other, So that the first or second emitter metal can make an ohmic contact.

Therefore, the on resistance loss of the power semiconductor device can be greatly reduced.

1 is a schematic perspective view of a power semiconductor device according to an embodiment of the present invention.
2 is a schematic plan view of a power semiconductor device according to an embodiment of the present invention.
3 is a schematic cross-sectional view of a power semiconductor device according to an embodiment of the present invention.
4 is a schematic perspective view of a power semiconductor device according to another embodiment of the present invention.
5 is a schematic plan view of a power semiconductor device according to another embodiment of the present invention.
6 is a schematic cross-sectional view of a power semiconductor device according to another embodiment of the present invention.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the invention. It is also to be understood that the technical terms used herein are to be interpreted in a sense generally understood by a person skilled in the art to which the present invention belongs, Should not be construed to mean, or be interpreted in an excessively reduced sense. Further, when a technical term used herein is an erroneous technical term that does not accurately express the spirit of the present invention, it should be understood that technical terms that can be understood by a person skilled in the art are replaced. In addition, the general terms used in the present invention should be interpreted according to a predefined or prior context, and should not be construed as being excessively reduced.

Also, the singular forms "as used herein include plural referents unless the context clearly dictates otherwise. In the present application, the term "comprising" or "comprising" or the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

Furthermore, terms including ordinals such as first, second, etc. used in this specification can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or similar elements throughout the several views, and redundant description thereof will be omitted.

In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It is to be noted that the accompanying drawings are only for the purpose of facilitating understanding of the present invention, and should not be construed as limiting the scope of the present invention with reference to the accompanying drawings.

In the drawing, the x direction is defined as the width direction, the y direction is defined as the longitudinal direction, and the z direction is defined as the height direction.

The power switch can be implemented by any one of power MOSFET, IGBT, thyristor and the like. Most of the novel techniques disclosed herein are described on the basis of IGBTs. However, the various embodiments of the present invention disclosed herein are not limited to IGBTs but may be applied to other types of power switch technologies, including, for example, power MOSFETs and various types of thyristors in addition to diodes. Moreover, various embodiments of the present invention are described as including specific p-type and n-type regions. However, it goes without saying that the conductivity types of the various regions disclosed herein can be equally applied to the opposite device.

The n-type and p-type used herein may be defined as a first conductive type or a second conductive type. On the other hand, the first conductive type and the second conductive type mean different conductive types.

In general, '+' means a state doped at a high concentration, and '-' means a state doped at a low concentration.

The ohmic contact used here is defined as such that when the work function of the metal in contact with the semiconductor region having the n-type conductivity is? M and the work function of silicon is? Si,? M < Quot; means that the metal and the semiconductor region having the n-type conductivity are in contact with each other.

When the work function of the metal in contact with the semiconductor region having the p-type conductivity is represented by? M and the work function of silicon is represented by? Si, when? M>? Si is satisfied, the metal and the p- Quot; semiconductor region &quot;

FIG. 1 is a schematic perspective view of a power semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are a plan view and a cross-sectional view of the power semiconductor device shown in FIG. 1, respectively.

Referring to FIGS. 1 and 2, a power semiconductor device according to an embodiment of the present invention includes a drift layer 10 of a first conductivity type; A well region 20 formed by implanting an impurity of a second conductivity type in an upper portion of the drift layer 10; An emitter region 30 formed by implanting an impurity of a first conductivity type into the upper portion of the well region 20 and having a shape separated from the drift layer; The drift layer 10 and the well region 20 are formed so as to cover the boundary between the emitter region 30 and the well region 20 from the boundary between the drift layer 10 and the well region 20, A gate 40; A first emitter metal (50a) formed on an upper surface of the emitter region (30) and ohmically contacting the emitter region (30); And a second emitter metal (50b) formed on the upper surface of the well region (20) and ohmically contacting the well region (20).

The ideal breakdown voltage of the power semiconductor device is basically determined by the thickness of the drift layer 10 and the concentration of impurities.

In order to improve the internal pressure, it is necessary to increase the thickness and to reduce the concentration of the impurities. In this case, the Vce (sat) of the power semiconductor device increases.

In addition, since the processing for maintaining the internal pressure by the raw material is required to alleviate the electric field concentration at the chip edge, the power semiconductor device according to an embodiment of the present invention may include an electric field limiting ring (not shown).

The drift layer 10 may be formed by doping an n-type impurity at a low concentration to secure an internal pressure.

The well region 20 may be formed by implanting a p-type impurity into the drift layer 10.

The well region 20 may be formed to be long in the longitudinal direction on the drift layer and may have a stripe structure in the width direction.

An n-type impurity may be implanted into the well region 20 at a high concentration to form the emitter region 30.

The emitter region 30 may be formed in the well region 20 at a predetermined interval in the width direction and the longitudinal direction.

The drift layer 10, the well region 20, and the emitter region 30 have n-type, p-type, and n-type conductivity types, respectively.

That is, the diode is connected in the order of the n-type and the p-type, and the diode is connected in the order of the p-type and the n-type, and the current does not flow when the gate 40 voltage is not applied .

A gate 40 may be formed on the upper surface of the well region 20.

The gate 40 may have a structure in which a gate insulating layer 41 is formed in a portion in contact with the upper surface of the well region 20 and polysilicon 42 is formed in an upper portion of the gate insulating layer 41 have.

The gate 40 may be formed on the upper surface of the power semiconductor device in the longitudinal direction and may be formed to cover a portion of the drift layer 10 and a portion of the emitter region 30, Can be formed on the upper surface.

That is, the power semiconductor device according to an embodiment of the present invention may have a planar gate structure.

The power semiconductor device is operated by forming a conductive channel in the well region 20 when a voltage is applied to the gate 40 because the gate 40 takes the structure of a metal oxide semiconductor (MOS) .

That is, when a voltage higher than the threshold voltage of the device is applied to the gate electrode electrically connected to polysilicon or metal in the gate 40, the polarity is reversed on the surface of the well region 20 at the lower end of the electrode, This causes the transistor to operate.

Referring to FIG. 3, when a positive voltage is applied to the gate 40, a channel is formed in the well region 20 so that an electron current (ie, a current) flows through the channel, the emitter region 30, (50a). &Lt; / RTI &gt;

On the other hand, the hole current ih flows from the well region 20 to the second emitter metal 50a without going through the emitter region 30.

At this time, depending on the material of the first or second emitter metal 50a or 50b, the emitter region 30, the first emitter metal 50a, the well region 20, 2 emitter metal 50b is changed, the resistance value is changed.

That is, a first emitter metal 50a having a low barrier voltage by Ohmic contact with the emitter region 30 is formed on the upper surface of the emitter region 30, And on the upper surface of the well region 20, a second emitter metal 50a having a low barrier voltage can be formed by ohmic contact with the first emitter metal layer 50 to reduce the on voltage loss of the power semiconductor device.

Table 1 below shows the barrier voltages of titanium and aluminum according to the conductivity type of the semiconductor.

Titanium (Ti) Aluminum (Al) n-type semiconductor -0.1 eV 0.2 eV p-type semiconductor 1.22 eV 0.92 eV

As shown in Table 1, for the n-type semiconductor, titanium (Ti) has a barrier voltage of -0.1 eV, while aluminum has a barrier voltage of 0.2 eV.

That is, in the case of the emitter region 30 using the n-type semiconductor, by forming the first emitter metal 50a using titanium (Ti), a lower barrier voltage can be obtained than in the case of using aluminum (Al) have.

Therefore, the first emitter metal 50a can be formed on the upper surface of the emitter region 30 using titanium (Ti), thereby minimizing the loss of the electron current (ie).

On the other hand, in the case of the well region 30 using the p-type semiconductor, by forming the second emitter metal 50b using aluminum (Al), a lower barrier voltage can be obtained than in the case of using titanium (Ti) have.

Therefore, the second emitter metal 50b may be formed on the upper surface of the well region 20 by using aluminum (Al) to minimize the loss of the hole current ih.

The second emitter metal 50b may be formed to cover the first emitter metal 50a.

That is, after the well region 20, the emitter region 30, and the gate are formed, the first emitter metal 50a is formed by sputtering, CVD (Chemical Vapor Deposition) The remaining portion except the portion corresponding to the emitter region 30 may be removed by etching or the like.

Thereafter, the second emitter metal 50b is formed by sputtering, CVD or the like so that the second emitter metal 50b is covered with the first emitter metal 50a .

The power semiconductor device of the present invention may further include a collector layer 60 under the drift layer 10. When the collector layer 60 has a second conductivity type, If it has a type, it can operate as a MOSFET.

A colractor metal 70 may be formed on the lower portion of the collector layer 60.

A high-concentration field stop layer 11 of the first conductivity type may be formed between the collector layer 60 and the drift layer 10.

The field stop layer 11 improves the breakdown voltage of the power semiconductor device and reduces the thickness of the drift layer 10, contributing to miniaturization of the device.

FIG. 4 is a schematic perspective view of a power semiconductor device according to another embodiment of the present invention, and FIGS. 5 and 6 are a plan view and a sectional view of the power semiconductor device shown in FIG. 1, respectively.

Referring to FIGS. 4 and 5, a power semiconductor device according to another embodiment of the present invention includes a drift layer 10 of a first conductivity type; A well region 20 formed by implanting an impurity of a second conductivity type in an upper portion of the drift layer 10; An emitter region 30 formed by implanting an impurity of a first conductivity type into the upper portion of the well region 20 and having a shape separated from the drift layer 10; A gate (40) formed to penetrate from the well region (20) to a portion of the drift layer (10) and on which the emitter region (30) is located; A first emitter metal (50a) formed on an upper surface of the emitter region (30) and ohmically contacting the emitter region (30); And a second emitter metal (50b) formed on the upper surface of the well region (20) and ohmically contacting the well region (20).

The ideal breakdown voltage of the power semiconductor device is basically determined by the thickness of the drift layer 10 and the concentration of impurities.

In order to improve the internal pressure, it is necessary to increase the thickness and to reduce the concentration of the impurities. In this case, the Vce (sat) of the power semiconductor device increases.

In addition, since the processing for maintaining the internal pressure by the raw material is required to alleviate the electric field concentration at the chip edge, the power semiconductor device according to an embodiment of the present invention may include an electric field limiting ring (not shown).

The drift layer 10 may be formed by doping an n-type impurity at a low concentration to secure an internal pressure.

The well region 20 may be formed by implanting a p-type impurity into the drift layer 10.

An n-type impurity may be implanted into the well region 20 at a high concentration to form the emitter region 30.

The drift layer 10, the well region 20, and the emitter region 30 have n-type, p-type, and n-type conductivity types, respectively.

That is, the diode is connected in the order of the n-type and the p-type and the diode is connected in the order of the p-type and the n-type, so that the current does not flow.

The gate 40 may be formed by etching from the well region 20 to a portion of the drift layer 10.

The gate 40 may be formed to have a structure in which the emitter region 30 is located on both sides.

The gate 40 may have a structure in which the gate insulating layer 41 is formed in the etched portion and the polysilicon 42 is filled in the gate insulating layer 41.

The gate 40 may be formed to extend in the y direction on the power semiconductor device.

That is, the power semiconductor device according to another embodiment of the present invention may have a structure having a trench gate.

In the power semiconductor device, when the gate 40 has a structure of a metal oxide semiconductor (MOS) structure and a voltage is applied to the gate 40, a conductive channel is formed in the well region 20 to operate .

That is, when a voltage higher than the threshold voltage of the device is applied to the gate electrode electrically connected to polysilicon or metal in the gate 40, the polarity is reversed on the surface of the well region 20 at the lower end of the electrode, This causes the transistor to operate.

Referring to FIG. 6, when a positive voltage is applied to the gate 40, a channel is formed in the well region 20 adjacent to the gate 40, so that an electron current (ie, ), It flows to the first emitter metal 50a.

On the other hand, the hole current ih flows from the well region 20 to the second emitter metal 50a without going through the emitter region 30.

At this time, depending on the material of the first or second emitter metal 50a or 50b, the emitter region 30, the first emitter metal 50a, the well region 20, 2 emitter metal 50b is changed, the resistance value is changed.

That is, a first emitter metal 50a having a low barrier voltage by Ohmic contact with the emitter region 30 is formed on the upper surface of the emitter region 30, And on the upper surface of the well region 20, a second emitter metal 50a having a low barrier voltage can be formed by ohmic contact with the first emitter metal layer 50 to reduce the on voltage loss of the power semiconductor device.

As shown in Table 1, for the n-type semiconductor, titanium (Ti) has a barrier voltage of -0.1 eV, while aluminum has a barrier voltage of 0.2 eV.

That is, in the case of the emitter region 30 using the n-type semiconductor, by forming the first emitter metal 50a using titanium (Ti), a lower barrier voltage can be obtained than in the case of using aluminum (Al) have.

Therefore, the first emitter metal 50a can be formed on the upper surface of the emitter region 30 using titanium (Ti), thereby minimizing the loss of the electron current (ie).

Conversely, by forming the second emitter metal 50b using the aluminum (Al) in the well region 30 using the p-type semiconductor, a lower barrier voltage can be obtained than in the case of using titanium (Ti) have.

Therefore, the second emitter metal 50b may be formed on the upper surface of the well region 20 by using aluminum (Al) to minimize the loss of the hole current ih.

The second emitter metal 50b may be formed to cover the first emitter metal 50a.

That is, after the well region 20, the emitter region 30, and the gate are formed, the first emitter metal 50a is formed by a method such as sputtering or CVD (Chemical Vapor Deposition) The remaining portion except the portion corresponding to the emitter region 30 may be removed by etching or the like.

Thereafter, the second emitter metal 50b is formed by sputtering, CVD or the like so that the second emitter metal 50b is covered with the first emitter metal 50a .

The power semiconductor device of the present invention may further include a collector layer 60 under the drift layer 10. When the collector layer 60 has a second conductivity type, If it has a type, it can operate as a MOSFET.

A colractor metal 70 may be formed on the lower portion of the collector layer 60.

A high-concentration field stop layer 11 of the first conductivity type may be formed between the collector layer 60 and the drift layer 10.

The field stop layer 11 improves the breakdown voltage of the power semiconductor device and reduces the thickness of the drift layer 10, contributing to miniaturization of the device.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken as a limitation upon the scope of the invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

10: drift layer
11: Field stop layer
20: well region
30: Emitter area
40: Gate
41: gate oxide
42: Polysilicon
50a: first emitter metal 50b: second emitter metal
60: Collector layer
70: Colacator metal

Claims (8)

A drift layer of a first conductivity type;
A well region of a second conductivity type formed on the drift layer;
A first conductivity type emitter region formed on the well region and separated from the drift layer by the well region;
A gate formed to cover a boundary between the drift layer and the well region from a boundary between the emitter region and the well region;
A first emitter metal formed on an upper surface of the emitter region and ohmically contacting the emitter region; And
And a second emitter metal formed on an upper surface of the well region and ohmically in contact with the well region. The method according to claim 1,
When the first conductivity type is n-type,
Wherein the first emitter metal is titanium (Ti). The method according to claim 1,
When the second conductivity type is p-type,
And the second emitter metal is aluminum (Al). The method according to claim 1,
And the second emitter metal covers the first emitter metal. A drift layer of a first conductivity type;
A well region of a second conductivity type formed on the drift layer;
A first conductivity type emitter region formed on the well region and separated from the drift layer by the well region;
A gate formed to penetrate from the well region to a portion of the drift layer, the gate having the emitter regions located on both sides thereof;
A first emitter metal formed on an upper surface of the emitter region and ohmically contacting the emitter region; And
And a second emitter metal formed on an upper surface of the well region and ohmically in contact with the well region. 6. The method of claim 5,
When the first conductivity type is n-type,
Wherein the first emitter metal is titanium (Ti). 6. The method of claim 5,
When the second conductivity type is p-type,
And the second emitter metal is aluminum (Al). 6. The method of claim 5,
And the second emitter metal covers the first emitter metal.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160121354A (en) 2015-04-09 2016-10-19 삼성전기주식회사 Semiconductor Device And Manufacturing Method Of The Same

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KR20160121354A (en) 2015-04-09 2016-10-19 삼성전기주식회사 Semiconductor Device And Manufacturing Method Of The Same

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