KR20150009170A - Shift register - Google Patents

Abstract

The present invention relates to a shift register to output the scan pulse of complex wave. A-stages which receive at least one among A-clock pulses and output at least one A-carry pulse and at least one A-scan pulse; and at least one B-stage which receives at least one among at least first to A-carry pulse among the A-stages, an enable signal from the outside, and B-clock pulses and output at least one B-scan pulse.

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly, to a shift register capable of stably outputting a scan pulse of a complex waveform in an organic light emitting diode display.

In the organic light emitting diode display device, there is a deviation of a driving current applied to each pixel, and a large number of transistors are integrated inside the pixel to prevent the deviation.

This display device has a shift register for sequentially generating a large number of control signals for driving these transistors.

Conventional shift registers employ a multiplexer structure to output scan pulses of two composite waveforms having different widths and timings.

However, this structure generates a scan pulse of the above-described complex waveform by switching a fixed constant voltage provided from the outside, and in order to stably output the scan pulse, there is a problem that the size of the output transistor switching the scan pulse is enormous there was. Further, there is an additional problem that the size of the display device must be increased.

The present invention has been conceived to solve the problems as described above, and it is an object of the present invention to provide a method of bootstrapping a set node by using a clock pulse and a floating structure to stably provide a plurality of composite waveforms And it is an object of the present invention to provide a shift register capable of outputting scan pulses (A-scan pulse and B-scan pulse), thereby making the size of the scan output switching elements relatively small.

According to an aspect of the present invention, there is provided a shift register including a plurality of A-stages for receiving at least one of a plurality of A-clock pulses and outputting at least one A-carry pulse and at least one A- field; And supplying at least one of an A-carry pulse from at least one of the A-stages, an external enable signal, and a plurality of B-clock pulses to output at least one B- Stage.

The plurality of A-stages sequentially outputs a plurality of A-scan pulses and a plurality of A-carry pulses for every A-output period of each frame period; Stage B-scan pulse is outputted in a B-output period of a specific frame period. The A-stages include A-carry output terminals and at least one A-scan output terminal ; The at least one B-stage comprises at least one B-scan output terminal; Each of the A-stages outputs an A-carry pulse through its A-carry output terminal and an A-scan pulse through an A-scan output terminal; The A-scan output terminal and the B-scan output terminal are the same or different.

The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; And a B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node.

The n-th B-stage is controlled in accordance with an A-carry pulse from an n-th A-stage and is used for discharging the voltage between the B-set node and an enable line, And a reset switching element connected between the power supply lines.

The n-th B-stage is controlled according to a control signal from the outside, and is connected between the B-set node and the enable line or between the B-set node and a discharge power supply line for transmitting a discharge voltage source And a reset switching element.

The n-th B-stage is controlled in accordance with the A-scan pulse from the n-th A-stage, and between the B-set node and the enable line or the B- A first reset switching element connected between the first discharge power supply line; Connected between the B-set node and the enable line, or between the B-set node and a second discharging power supply line for transmitting a second discharging voltage source, And a reset switching element.

Stage, the n-th B-stage further comprises a B-capacitor connected between the B-set node and the B-scan output terminal.

The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A switching element; A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B-set node.

The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; A reset switching element connected between the B-set node and an enable line, or between a B-set node and a discharge power supply line for transmitting a discharge voltage source, the reset switching element being controlled according to a control signal from the outside; A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B-set node.

The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage between the B-set node and the enable line, or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A first reset switching element connected to the second node; A second reset connected between the B-set node and an enable line, or between a second discharge power supply line for transmitting a second discharge voltage source to the B-set node, A switching element; A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B-set node.

The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number) and the enable line for transmitting the enable signal and the B1- A connected set switching element; stage, and between the B1-set node and the enable line, or between the B1-set node and the first discharge power supply line for transmitting the first discharge voltage source A first B1-reset switching element connected thereto; A B1-scan output switching element connected between the B1-clock transmission line for transmitting the B1-clock pulse and the B1-scan output terminal, the B1-scan output switching element being controlled according to the voltage of the B1-set node; A B-control switching element controlled in accordance with the voltage of the B1-set node and connected between the B1-set node and the B2-set node; stage between the B2-set node and the enable line, or between the B2-set node and the second discharge power supply line for transferring the second discharge voltage A first B2-reset switching element connected thereto; And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B2-set node.

A second B1-reset switching element controlled in accordance with a control signal from the outside, and connected between the B1-set node and an enable line, or between the B1-set node and a first discharge power supply line; And at least one of the second B2-reset switching elements connected between the B2-set node and the enable line, or between the B2-set node and the second discharge power supply line, And one or more of them.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A switching element; A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-carry output terminal and the B-scan output terminal.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; A reset switching element connected between the B-set node and an enable line, or between a B-set node and a discharge power supply line for transmitting a discharge voltage source, the reset switching element being controlled according to a control signal from the outside; A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-carry output terminal and the B-scan output terminal.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage, and is connected between the B-set node and the enable line, or between the B-set node and the discharge power supply line for transferring the discharge voltage source to the first A reset switching element; A second reset switching element connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, the second reset switching element being controlled according to a control signal from the outside; A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-carry output terminal and the B-scan output terminal.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A switching element; A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-clock transmission line and the B-carry output terminal.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; A reset switching element connected between the B-set node and an enable line, or between a B-set node and a discharge power supply line for transmitting a discharge voltage source, the reset switching element being controlled according to a control signal from the outside; A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-clock transmission line and the B-carry output terminal.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage, and is connected between the B-set node and the enable line, or between the B-set node and the discharge power supply line for transferring the discharge voltage source to the first A reset switching element; A second reset switching element connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, the second reset switching element being controlled according to a control signal from the outside; A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-clock transmission line and the B-carry output terminal.

The n-th B-stage is controlled in accordance with the voltage of the B-reset node, and further includes a B-carry discharge switching element connected between the B-carry output terminal and a discharge power supply line for transmitting a discharge voltage ; The B-reset node is characterized in that any one of the A-clock pulse, the A-carry pulse, the start pulse, and the voltage of the A-stage reset node is applied.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage between the B-set node and the enable line or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A connected reset switching element; A B-carry output switching element connected between the B1-clock transmission line and the B-carry output terminal for transmitting the B1-clock pulse, the B-carry output switching element being controlled according to the voltage of the B-set node; A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; A B2-scan output switching element controlled in accordance with the voltage of the B-set node and connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal; And a B-carry discharge switching element connected between the B-carry output terminal and a second discharge power supply line for transmitting a second discharge voltage, the B-carry discharge switching element being controlled according to the voltage of the B-reset node; The B-reset node is characterized in that any one of the A-clock pulse, the A-carry pulse, the start pulse, and the voltage of the A-stage reset node is applied.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; A reset switching element connected between the B-set node and the enable line or between the B-set node and a first discharge power supply line for transmitting a first discharge voltage source, ; A B-carry output switching element connected between the B1-clock transmission line and the B-carry output terminal for transmitting the B1-clock pulse, the B-carry output switching element being controlled according to the voltage of the B-set node; A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; A B2-scan output switching element controlled in accordance with the voltage of the B-set node and connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal; And a B-carry discharge switching element connected between the B-carry output terminal and a second discharge power supply line for transmitting a second discharge voltage, the B-carry discharge switching element being controlled according to the voltage of the B-reset node; The B-reset node is characterized in that any one of the A-clock pulse, the A-carry pulse, the start pulse, and the voltage of the A-stage reset node is applied.

Wherein the at least one B-stage further comprises at least one B-carry output terminal; The B-stage further outputs a B-carry pulse via a B-carry output terminal; The number of A-stages and the number of B-stages are the same; Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal; The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The n-th B-stage (n is a natural number) is controlled in accordance with the A-carry pulse from the (n + x) th A-stage (x is a natural number), and the enable line and the B- A connected set switching element; stage between the B-set node and the enable line or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A connected first reset switching element; A second reset connected between the B-set node and an enable line, or between a second discharge power supply line for transmitting a second discharge voltage source to the B-set node, A switching element; A B-carry output switching element connected between the B1-clock transmission line and the B-carry output terminal for transmitting the B1-clock pulse, the B-carry output switching element being controlled according to the voltage of the B-set node; A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; A B2-scan output switching element controlled in accordance with the voltage of the B-set node and connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal; And a B-carry discharge switching element connected between the B-carry output terminal and a third discharge power supply line for transmitting a third discharge voltage, the B-carry discharge switching element being controlled according to the voltage of the B-reset node; The B-reset node is characterized in that any one of the A-clock pulse, the A-carry pulse, the start pulse, and the voltage of the A-stage reset node is applied.

The n-th B-stage is controlled according to a B-clock pulse or an F-clock pulse, and further comprises a first B-control switching element connected between the B-set node and a B-scan output terminal; And the F-clock pulse is equal to or different from the A-clock pulse.

The n-th B-stage includes: a capacitor to which a B-clock pulse or a G-clock pulse is supplied to one terminal; A first B-control switching element controlled in accordance with a voltage of the B-set node, the first B-control switching element being connected between the other terminal of the capacitor and a discharge power supply line for transmitting a discharge voltage; And a second B-control switching element connected between the B-set node and the B-scan output terminal, the second B-control switching element being controlled according to a voltage applied to the other terminal of the capacitor; And a rising edge of the B-clock pulse is included in the pulse width of the G-clock pulse.

The n-th A-stage (n is a natural number) is determined according to at least one of the A-carry pulse from the npth A-stage and the A-carry pulse from the n + And a node control section for controlling the voltage of the set node or the voltage of the A1-set node and the A-reset node.

The number of A-stages and the number of B-stages are the same; Wherein the at least one A-scan output terminal comprises an A1-scan output terminal and an A2-scan output terminal; The plurality of A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses; the nth A-stage is controlled according to the voltage of the A-set node, and the A-carry output switching element connected between the A1-clock transmission line transmitting the A1-clock pulse and the A-carry output terminal; An A1-scan output switching device controlled in accordance with the voltage of the A-set node and connected between the A1-clock transmission line and the A1-scan output terminal; An A2-scan output switching element connected between the A2-clock transmission line and the A2-scan output terminal for transmitting the A2-clock pulse, the A2-scan output switching element being controlled according to the voltage of the A-set node; And an A-carry discharge switching element connected between the A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to the voltage of the A-reset node.

The number of A-stages and the number of B-stages are the same; Wherein the at least one A-scan output terminal comprises an A1-scan output terminal and an A2-scan output terminal; The plurality of A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses; the nth A-stage is controlled according to the voltage of the A1-set node, and the A-carry output switching element connected between the A1-clock transmission line transmitting the A1-clock pulse and the A-carry output terminal; An A1-scan output switching element controlled in accordance with the voltage of the A1-set node and connected between the A1-clock transmission line and the A1-scan output terminal; An A-control switching element controlled in accordance with the voltage of the A1-set node, the A-control switching element being connected between the A1-set node and the A2-set node; An A2-scan output switching element connected between the A2-clock transmission line and the A2-scan output terminal for transmitting the A2-clock pulse, the A2-scan output switching element being controlled according to the voltage of the A2-set node; And an A-carry discharge switching element connected between the A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to the voltage of the A-reset node .

The number of A-stages and the number of B-stages are the same; Wherein the at least one A-scan output terminal comprises an A1-scan output terminal and an A2-scan output terminal; The plurality of A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses; the nth A-stage is controlled according to the voltage of the A1-set node, and the A-carry output switching element connected between the A1-clock transmission line transmitting the A1-clock pulse and the A-carry output terminal; An A1-scan output switching element controlled in accordance with the voltage of the A1-set node and connected between the A1-clock transmission line and the A1-scan output terminal; An A-control switching element controlled in accordance with the voltage of the A-carry output terminal and connected between the A-carry output terminal and the A2-set node; An A2-scan output switching element connected between the A2-clock transmission line and the A2-scan output terminal for transmitting the A2-clock pulse, the A2-scan output switching element being controlled according to the voltage of the A2-set node; And an A-carry discharge switching element connected between the A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to the voltage of the A-reset node .

The n-th A-stage is controlled according to the voltage of the A-reset node, and is connected between the A1-scan output terminal and the discharge power supply line. And at least one of A2-scan discharge switching elements controlled in accordance with the voltage of the A-reset node and connected between the A2-scan output terminal and the discharge power supply line.

The n-th A-stage is controlled according to any one of the A1-scan pulse and the A2-scan pulse. The first A-stage is connected between the A-reset node and a discharge power supply line for transmitting a discharge voltage. A control switching element; And at least one of a second A-control switching element controlled in accordance with a B-clock pulse and connected between the A1-set node and the A2-set node and the discharge power supply line .

The nth A-stage is controlled in accordance with a B-carry pulse from the B-stage and is connected between a power supply line for transmission of a discharge voltage to one of the A1-set node and the A2- A third A-control switching element; And a fourth A-control switching element controlled in accordance with a B-carry pulse from the B-stage and connected between the A-reset node and the discharge power supply line .

The nth A-stage node controller is controlled according to the A-carry pulse from the A-stage (n is a natural number smaller than n), and the charging power supply line for transmitting the charging voltage and the A- A first A-switching element connected between the charging power supply line and the A1-set node; (n + q) th (where q is a natural number) A-stage, and between the A-set node and a discharge power supply line for transmitting a discharge voltage, or between the A1- A second A-switching element connected between the dedicated power supply lines; And an A-inversion unit for controlling a voltage of the A-set node according to a voltage of the A-set node or the A1-set node.

Wherein the A-inverting portion is controlled in accordance with a high voltage from a high power line, the first A-inverting switching element being connected between the high power line and the A-reset node; And a second A-inversion switching element connected between the A-reset node and a low power line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1- do.

The A-inverting unit includes: a first A-inverting switching element connected between the high power line for transmitting a high voltage and the A-reset node, the first A-inverting switching element being controlled according to a control signal from the outside; And a second A-inversion switching element connected between the A-reset node and a low power line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1- do.

The A-inverting unit includes a first A-inverting switching element connected between a high power line for transmitting a high voltage and an A-common node, the first A-inverting switching element being controlled according to a control signal from the outside; A second A-inversion switching element connected between the A-common node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node; A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And a fourth A-inversion switching element connected between the A-reset node and the low power supply line, the fourth A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node.

Wherein the A-inverting section is controlled in accordance with a high voltage from a high power line, the first A-inverting switching element being connected between the high power line and the A-common node; A second A-inversion switching element connected between the A-common node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node; A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And a fourth A-inversion switching element connected between the A-reset node and the low power supply line, the fourth A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node.

Wherein the A-inverting section is controlled in accordance with a high voltage from a high power line, the first A-inverting switching element being connected between the high power line and the A-common node; A second A-inverting switching element connected between the A-common node and a low power line for transmitting a low voltage, the second A-inverting switching element being controlled according to the voltage of the A1-scan output terminal or the A2-scan output terminal; A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And a fourth A-inverting switching element controlled in accordance with the voltage of the A-set node or the A1-reset node and connected between the A-reset node and the low power line.

Wherein the A-inverting portion comprises: a first A-inverting switching element connected between the A-set node and a low power supply line for transmitting a low voltage, the first A-inverting switching element being controlled according to the voltage of the A- Set node and the A-set node and between the A-set node and the A-scan output terminal, or between the A-set node and the A- Connected between the A1-set node and the A1-scan output terminal, or between the A1-set node and the A2-scan output terminal, or between the A1-set node and the A- A-inverting switching device; And an A-capacitor connected between the A-reset transmission node and the A-clock transmission line for transmitting any one of the A-clock pulses.

The A-inverting unit is controlled according to any one of the A-clock pulses and includes a first A-inverting switching element connected between a high power line for transmitting a high voltage and an A-reset node; A second A-inversion switching element connected between the A-set node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node; And a third A-inverted switching element connected between the A-reset node and the low power supply line, the third A-inverted switching element being controlled according to another A-clock pulse.

The A-inverting unit is controlled according to any one of the A-clock pulses, and the first A-inverted switching unit connected between the A-clock transmission line and the A- device; A second A-inversion switching element connected between the A-set node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node; And a third A-inverted switching element connected between the A-reset node and the low power supply line, the third A-inverted switching element being controlled according to another A-clock pulse.

The A-inverting unit is controlled according to any one of the A-clock pulses, and includes a first A-inverting switching element connected between a high power line for transmitting a high voltage and the A-common node; A second A-inverting switching element connected between the A-common node and a low power supply line for transmitting a low voltage, the second A-inverting switching element being controlled according to another A-clock pulse; A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And a fourth A-inversion switching element connected between the A-reset node and the low power supply line, the fourth A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node.

The A-inverting portion is controlled according to an A-carry pulse from an n-pth A-stage, and a fifth A-inverting switching element connected between the A-reset node and the low power supply line; Stage node and between the A-set node and the discharge power supply line, or between the A-set node and the A1-scan output terminal of any one of the A-stages, or between the A- Between the set node and the A2-scan output terminal of any one of the A-stages, or between the A-set node and the carry output terminal of any one of the A-stages, or between the A1- Or between the A1-set node and the A1-scan output terminal of any one of the A-stages, or between the A1-set node and the A2-scan output terminal of any one of the A-stages or between the A1- A sixth A-inverting switching element connected between the carry output terminals of any one of the A-stages; The A-set node is controlled by the voltage of the A-reset node and between the A-set node and the A-clock transmission line transmitting any one A-clock pulse, or between the A- A seventh A-inverting switching element connected between the A-clock transmission line for transmitting the A-clock transmission line; Stage output terminal and the A-set node, or between the A2-scan output terminal of the npth A-stage and the A-set node, and the A- Or an 8th A-inverting switching element connected between the A1-scan output terminal and the A1-set node of the npth A-stage or between the A2- scan output terminal of the npth A-stage and the A1-set node; And at least one of ninth A-inversion switching elements controlled in accordance with a scan pulse from any one of the A-stages and connected between the A-reset node and the low power supply line .

The A-inverting unit may further include a tenth A-inverting switching element connected between the A-common node and the low power supply line, the tenth A-inverting switching unit being controlled according to a scan pulse from any one of the A-stages.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to an A-scan pulse from the A-scan output terminal of the n-th A-stage, and the A- And a third A-switching element connected between the two-room dedicated power supply line.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to an A-scan pulse from the A-scan output terminal of the n-th A-stage, and the A- A third A-switching element connected between two dedicated power lines; And a fourth A-switching element connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, the fourth A-switching element being controlled according to a B-clock pulse or an F-clock pulse .

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to a B-carry pulse from the B-carry output terminal of the n-th B-stage, A third A-switching element connected between two dedicated power lines; And a fourth A-switching element connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, the fourth A-switching element being controlled according to an F-clock pulse; And a B-carry pulse from the B-stage is generated based on a B-clock pulse.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to a B-carry pulse from the B-carry output terminal of the n-th B-stage, A third A-switching element connected between two dedicated power lines; And a fourth A-switching element connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, the fourth A-switching element being controlled according to an F-clock pulse; And a B-carry pulse from the B-stage is generated based on an F-clock pulse.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to a B-carry pulse from the B-carry output terminal of the n-th B-stage, A third A-switching element connected between two dedicated power lines; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, Further comprising a 4 A-switching element; And a B-carry pulse from the B-stage is generated based on an F-clock pulse.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to a B-carry pulse from the B-carry output terminal of the n-th B-stage, A third A-switching element connected between two dedicated power lines; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, Further comprising a 4 A-switching element; And a B-carry pulse from the B-stage is generated based on a B-scan pulse from the B-stage.

The nth A-stage further comprises a fifth A-switching element controlled in accordance with the voltage of the A-reset node and connected between the second power line and the B-carry output terminal .

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to an A-scan pulse from the A-scan output terminal of the n-th A-stage, and the A- A third A-switching element connected between two dedicated power lines; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, Further comprising a 4 A-switching element; The n-th B-stage is controlled in accordance with an F-clock pulse, and the first B-switching connected between the B-scan output terminal of the n-th B-stage and the B- Further comprising a device.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The nth A-stage node controller is controlled according to a B-clock pulse, and the third A-switching node connected between the A-reset node and a second discharge power supply line for transmitting a second discharge voltage device; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, Further comprising a 4 A-switching element; The n-th B-stage is controlled in accordance with an F-clock pulse, and the first B-switching connected between the B-scan output terminal of the n-th B-stage and the B- Further comprising a device.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to an A-scan pulse from the A-scan output terminal of the n-th A-stage, and the A- A third A-switching element connected between two dedicated power lines; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, Further comprising a 4 A-switching element; The n-th B-stage includes: a capacitor to which a B-clock pulse or a G-clock pulse is supplied to one terminal; A first B-control switching element controlled in accordance with a voltage of the B-set node, the first B-control switching element being connected between the other terminal of the capacitor and a discharge power supply line for transmitting a discharge voltage; And a second B-control switching element connected between the B-set node and the B-scan output terminal, the second B-control switching element being controlled according to a voltage applied to the other terminal of the capacitor; And a rising edge of the B-clock pulse is included in the pulse width of the G-clock pulse.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal, an A1-scan output terminal and an A2-scan output terminal; The nth B-stage includes a B1-set node, a B2-set node, a B1-scan output terminal and a B2-scan output terminal; The A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses; B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The A1-scan output terminal of the n-th A-stage is connected to the B1-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The A2-scan output terminal of the n-th A-stage is connected to the B2-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th stage A-stage node controller is controlled according to an A-scan pulse from the A-scan output terminal of the n-th A-stage, and the A- A third A-switching element connected between two dedicated power lines; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, 4-A switching device.

Stage comprises an A-set node, an A-reset node, an A-carry output terminal, an A1-scan output terminal and an A2-scan output terminal; stage, the n-th B-stage includes a B-set node, a B1-scan output terminal and a B2-scan output terminal; The A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses; B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses; The A1-scan output terminal of the n-th A-stage is connected to the B1-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The A2-scan output terminal of the n-th A-stage is connected to the B2-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th stage A-stage node controller is controlled according to an A-scan pulse from the A-scan output terminal of the n-th A-stage, and the A- A third A-switching element connected between two dedicated power lines; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, 4-A switching device.

Stage comprises an A-set node, an A1-reset node, an A2-reset node, an A-carry output terminal and an A-scan output terminal; The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage; The n-th A-stage node controller is controlled according to a B-carry pulse from the B-carry output terminal of the n-th B-stage, A third A1-switching element connected between the two-room dedicated power supply line; A third A2-switching device controlled in accordance with a B-carry pulse from the B-carry output terminal of the n-th B-stage and connected between the A2-reset node and a second discharge power supply line; And a B-carry pulse from the B-carry output terminal of the n-th B-stage, wherein the A-set node is connected to a first discharge power supply line for transmitting a first discharge voltage, Further comprising a 4 A-switching element; And a B-carry pulse from the B-stage is generated based on a B-scan pulse from the B-stage.

Wherein the at least one A-scan output terminal comprises an A1-scan output terminal; The plurality of A-clock pulses comprising a plurality of A1-clock pulses having a phase difference; the nth A-stage is controlled according to the voltage of the A-set node, and the A-carry output switching element connected between the A1-clock transmission line transmitting the A1-clock pulse and the A-carry output terminal; An A1-scan output switching device controlled in accordance with the voltage of the A-set node and connected between the A1-clock transmission line and the A1-scan output terminal; And an A-carry discharge switching element connected between the A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to the voltage of the A-reset node.

The shift register according to the present invention has the following effects.

First, according to the present invention, a stable non-constant voltage pulse and a floating structure are used to bootstrap the set node, so that a stable A-carry pulse and an A-scan pulse can be output even by using a relatively low voltage clock pulse .

Second, since the output voltage is stabilized by the bootstrapping, the output can be prevented from being attenuated by making the size of the scan output switching elements relatively small. Therefore, it is advantageous to minimize the occupied area of the display device and reduce its size.

Third, since the two A-scan pulses (A1-scan pulse and A2-scan pulse) are generated using the nodes included in one A-stage, only a few Pulses can be output.

1 is a view showing a shift register according to an embodiment of the present invention;
Figure 2 is an example of an A-clock pulse, an enable signal and a B-clock pulse, and an A-output pulse and a B-output pulse generated by them
FIG. 3 is a diagram showing a waveform except for the B-output pulse in FIG. 2; FIG.
Fig. 4 is a diagram showing a waveform except for the A- output pulse in Fig. 2
Fig. 5 is a block diagram of the B-stage of Fig. 1
6 is a diagram showing a circuit configuration of an n-th B-stage according to the first embodiment of the present invention
7 is a diagram showing the circuit configuration of the n-th B-stage according to the second embodiment of the present invention
8 is a diagram showing the circuit configuration of the n-th B-stage according to the third embodiment of the present invention
9 is a diagram showing a circuit configuration of an n-th B-stage according to a fourth embodiment of the present invention
10 is a diagram showing a circuit configuration of an n-th B-stage according to a fifth embodiment of the present invention
11 is a diagram showing a circuit configuration of an n-th B-stage according to a sixth embodiment of the present invention
12 is a diagram showing a circuit configuration of an n-th B-stage according to a seventh embodiment of the present invention
Figure 13 shows switching elements that may be added to the nth B-stage;
14 is a diagram showing a circuit configuration of an n-th B-stage according to an eighth embodiment of the present invention
15 is a diagram showing a circuit configuration of an n-th B-stage according to a ninth embodiment of the present invention
16 is a diagram showing a circuit configuration of an n-th B-stage according to a tenth embodiment of the present invention
17 is a diagram showing a circuit configuration of an n-th B-stage according to an eleventh embodiment of the present invention
18 is a diagram showing a circuit configuration of an n-th B-stage according to a twelfth embodiment of the present invention
19 is a diagram showing a circuit configuration of an n-th B-stage according to a thirteenth embodiment of the present invention
20 is a diagram showing a circuit configuration of an n-th B-stage according to a fourteenth embodiment of the present invention
21 is a diagram showing a circuit configuration of an n-th B-stage according to a fifteenth embodiment of the present invention
22 is a diagram showing a circuit configuration of an n-th B-stage according to a sixteenth embodiment of the present invention
23 is a diagram showing a circuit configuration of an n-th B-stage according to a seventeenth embodiment of the present invention
24 is a diagram showing a circuit configuration of an n-th B-stage according to an eighteenth embodiment of the present invention
25 is a diagram showing a circuit configuration of an n-th B-stage according to a nineteenth embodiment of the present invention
26 shows switching elements that may be added to the n-th B-stage;
27 is a diagram showing a circuit configuration of an n-th A-stage according to the first embodiment of the present invention
28 is a diagram showing a circuit configuration of the n-th A-stage according to the second embodiment of the present invention
29 is a diagram showing a circuit configuration of the n-th A-stage according to the third embodiment of the present invention
Figure 30 shows switching elements that may be added to the nth A-stage;
Figure 31 shows switching elements that may be added to the nth A-stage;
32 illustrates switching elements that may be added to the nth A-stage;
33 is a diagram showing a circuit configuration of a node control unit provided in the n-th A-stage
34 is a detailed configuration diagram of the A-inverted portion according to the first embodiment
35 is a detailed configuration diagram of the A-inverted portion according to the second embodiment
36 is a detailed configuration diagram of the A-inverted portion according to the third embodiment
37 is a detailed configuration diagram of the A-inverted portion according to the fourth embodiment
38 is a detailed configuration diagram of the A-inverted portion according to the fifth embodiment
39 is a detailed configuration diagram of the A-inverting section according to the sixth embodiment
40 is a detailed configuration diagram of the A-inverting portion according to the seventh embodiment
41 is a detailed configuration diagram of the A-inverted portion according to the eighth embodiment
42 is a detailed configuration diagram of the A-inverted portion according to the ninth embodiment
FIG. 43 is a view showing inverting switching elements that can be added to the A-inverting portion;
44 shows an inverting switching element which can be added to the A-inverting portion
45 is a diagram showing a first embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
46 is a diagram showing a second embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
47 is a view showing a third embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
48 is a diagram showing a fourth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
49 is a view showing a fifth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
50 is a view showing a sixth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
51 is a view showing a seventh embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
52 is a view showing an eighth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
53 is a view showing a ninth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
54 is a diagram showing a tenth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
55 is a view showing an eleventh embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage;
56 is a view showing still another embodiment of the n-th A-stage;

1 is a view illustrating a shift register according to an embodiment of the present invention.

The shift register according to the present invention includes a plurality of A-stages A-ST_n-2 to A-OUT_n + 2 sequentially outputting A-output pulses A-OUT_n- ST_n-2 to B-ST_n + 2) sequentially outputting B-output pulses (B-OUT_n-2 to B-OUT_n + 2) +2).

Here, the number of A-stages and the number of B-stages may be the same and may be different from each other. Here, the same number of A-stages and the same number of B-stages means that the number of B-stages is the same as the number of A-stages that supply outputs to signal lines (gate lines or scan lines). That is, the number of A-stages and the number of B-stages are the same except for dummy stages. The number of dummy stages may vary depending on the configuration of the A-stages and the configuration of the B-stages. In addition, the B-stage may correspond to at least one A-stage.

Further, if the number of stages is the same, a stage positioned at the same stage can be matched. For example, the n-th A-stage A-ST_n and the n-th B-stage B-ST_n are stages corresponding to each other. Stage and B-stage, and the corresponding stages are located at the same stage, but the present invention is applicable even when the number is different, in which case the A-stage in the latter stage corresponds to the corresponding A- Refers to the A stage located at the rear end of the stage, and the A-stage located at the same end means the corresponding A-stage.

Further, the output terminals of the corresponding stages can be connected to each other.

Stages located at the same stage are stages corresponding to each other. For example, the n-th A-stage A-ST_n and the n-th B-stage B-ST_n are stages corresponding to each other.

Each of the A-stages A-ST_n-2 through A-ST_n + 2 receives A-output pulses A-OUT_n-2 through A-OUT_n + 2 through its A- And B-stages (B-ST_n-2 through B-ST_n + 2) each generate B-output pulses B-OUT_n-2 through B- -OUT_n + 2).

One A-stage has one A-clock pulse (A-CLK) supplied to it, an A-output pulse from its A-stage at its previous stage, and one A-output pulse from its A- It is controlled by A-output pulse. That is, the n-th A-stage A-ST_n includes any one of the A-clock pulse CLKA, the A-output pulse from the np-th stage, and the A- -OUT_n + 2). Here, p and q are both natural numbers, and in particular p is a natural smaller than n. As an example, p can be 1 and q can be 2, an example of which is shown in FIG.

The A-stage generates an A-output pulse using an A-clock pulse, which can be divided into at least one A-scan pulse and at least one A-carry pulse. The A-scan pulse is a signal supplied to various signal lines including the gate line and the scan line of the display panel, and the A-carry pulse has a front stage A-stage positioned ahead of the A- A-stage. The A-carry pulse is also supplied to at least one B-stage to control the operation of that B-stage. Here, when the number of A-stages is greater than the number of B-stages, some A-carry pulses may not be supplied to the B-stage. Also, an A-carry pulse may be supplied to the B-stage to control the operation of the B-stage.

Thus, the A-scan pulse functions as a signal for driving the signal lines in the display panel, while the A-carry pulse functions as a signal for controlling the operation of the A-stage and B-stage.

The A-scan pulse and the A-carry pulse output from one A-stage may be generated by the same clock pulse, or may be generated by other clock pulses having different phases. When the A-scan pulse and the A-carry pulse are generated by the same clock pulse, these A-scan pulse and A-carry pulse are actually the same signal.

The A-output terminal (A-OT) is divided into an A-scan output terminal for outputting the A-scan pulse and an A-carry output terminal for outputting the A-carry pulse. The A-scan pulse generated from one A-stage is supplied to the corresponding signal line through its A-scan output terminal, and the A-carry pulse generated from the one A-stage passes through its A- Stage A-stage and the B-stage.

One A-stage performs the set operation in accordance with the A-carry pulse from the A-stage located in the preceding stage and outputs an A-output pulse as one of the A-clock pulses supplied after the set operation . Thereafter, after the output operation, the one A-stage performs a reset operation in accordance with the A-carry pulse from the A-stage located at a later stage.

On the other hand, one B-stage receives at least one of an A-carry pulse from at least one of the A-stages, an enable signal EN from the outside, and a plurality of B- - Generate output pulses.

Any one of the B-stages can be supplied with an A-carry pulse from the A-stage located at a later stage. That is, the n-th B-stage (B-ST_n) can receive the A-carry pulse from the (n + x) th A-stage. Here, x is a natural number. As an example, x may be 1.

On the other hand, as yet another embodiment, one B-stage may be supplied with an A-carry pulse from the A-stage in the back end as well as an A-carry pulse from the A-stage in the same stage as the B-stage . That is, the n-th B-stage (S-ST_n) may be supplied with an A-carry pulse from the (n + x) th A-stage and an A-carry pulse from the nth A-stage.

This B-stage generates a B-output pulse using a B-clock pulse, which can be divided into at least one B-scan pulse and at least one B-carry pulse. The B-scan pulse is a signal supplied to various signal lines including the gate line and the scan line of the display panel, and the B-carry pulse is a signal supplied to the A-stage at the same stage as the B-stage at which the B-scan pulse is outputted. This B-carry pulse may not be generated according to the circuit configuration of the B-stage.

Thus, the B-scan pulse functions as a signal for driving the signal lines in the display panel, while the B-carry pulse functions as a signal for controlling the operation of the A-stage.

The B-scan pulse and B-carry pulse output from one B-stage may be generated by the same clock pulse, or may be generated by other clock pulses having different phases. When the B-scan pulse and the B-carry pulse are generated by the same clock pulse, these B-scan pulse and B-carry pulse are actually the same signal.

The B-output terminal (B-OT) is divided into a B-scan output terminal for outputting a B-scan pulse and a B-carry output terminal for outputting a B-carry pulse. The B-scan pulse generated from one B-stage is supplied to the corresponding signal line through its B-scan output terminal, and the B-carry pulse generated from the one B- Stage A-stage.

One B-stage performs a set operation in accordance with an A-carry pulse (an A-carry pulse generated in the current frame period) from the A-stage located at a stage subsequent to the B-stage, And performs an output operation of outputting a clock pulse as a B-output pulse. Thereafter, after the output operation, the one B-stage performs the reset operation by the A-carry pulse (the A-carry pulse generated in the next frame period) from the A-stage described above. On the other hand, this B-stage may perform the reset operation in accordance with the A-carry pulse from the A-stage located at the same stage.

In the shift register including the A-stage and the B-stage thus configured, the A-stage and the B-stage corresponding to each other may be connected to the same signal line or may be separately connected to other signal lines. For example, the A-scan output terminal of the n-th A-stage A-ST_n and the B-scan output terminal of the n-th B-stage B-ST_n may be connected to the same n-th gate line. The A-scan output terminal of the n-th A-stage A-ST_n may be connected to the n-th gate line and the B-scan output terminal of the n-th B-stage B-ST_n may be connected to the n- .

A-clock pulse and B-clock pulse are pulse signals output with a constant period and amplitude.

On the other hand, the enable signal EN may be a pulse signal output with a regular period, or may be a pulse signal randomly output randomly.

The above-described output periods of the A-scan pulse and the B-scan pulse may be set differently. For example, when examining the A-scan pulse output from the (n-2) -th stage A-ST_n-2 and the B-scan pulse output from the (n-2) , The A-scan pulse is generated once for every frame, and the B-scan pulse (B-SC) is generated once for several frames.

As a more specific example, if the total number of gate lines of the display panel to be driven is 10, and the shift register for driving the 10 gate lines includes a total of 10 A-stages and 10 B-stages, (A-ST_n-2) and (n-2) th B-stages are the first stages for driving the first gate line, the time during which one gate line is driven is one horizontal period, Assume that one frame period is when all 10 gate lines are driven once.

Under this assumption, the first A-stage drives the first gate line every first horizontal period of each frame period by outputting an A-scan pulse for each first horizontal period of the 1 to 10 frame period. In addition, the first B-stage outputs a B-scan pulse immediately after the tenth horizontal period of the first frame period. That is, the generation position of the B-scan pulse can be generated at any time from the generation of the last A-scan pulse in the current frame period to the start of the next frame period. For example, the period may be a blank period of every frame period.

If the enable signal EN is output in the form of a pulse having a constant period, the B-scan pulse is output again through the first B-stage in the eleventh frame period. That is, under the above conditions, the first A-stage outputs an A-scan pulse once every frame period, and the first B-stage outputs a B-scan pulse (B-SC ). The remaining A-stages and B-stages also output A-scan pulses for each horizontal period in each frame period, and also output A-scan pulses in the ending period of the frame period (next period of the last horizontal period in each frame period) - Outputs a scan pulse. As described above, the term " next period of the last horizontal period " here means any specific period belonging to the period between the generation of the last A-scan pulse in the current frame period to the start of the next frame period.

2 shows one example of the A-clock pulse, the enable signal EN and the B-clock pulse, and the A-output pulse and the B-output pulse generated by them, and Fig. 3 2 except for the B-output pulse, and FIG. 4 is a diagram showing a waveform except for the A- output pulse in FIG.

As shown in FIG. 2, the A-clock pulse is composed of four clock pulses (A-CLK_1 to A-CLK_4) and the B-clock pulse is composed of one clock pulse (B-CLK) .

On the other hand, the enable signal EN is outputted in accordance with any one of the A-output pulses. For example, the enable signal EN outputted in the first frame period (T_F located at the leftmost position in Fig. 2) is synchronized with the (n + 2) th A-output pulse A-OUT_n-2. Specifically, a falling edge of the (n + 2) th A-output pulse A-OUT_n-2 is located within the high pulse width of the enable signal EN.

The output position of the enable signal EN may vary in each frame period. For example, as shown in Fig. 2, the enable signal EN output in the second frame period (T_F located in the middle) differs from the first frame period described above in that the (n + 3) (Not shown). The enable signal EN outputted in the third frame period (T_F located at the rightmost position) is supplied to the (n + 4) th A-output pulse (not shown) unlike the first and second frame periods described above It is synchronized.

The A-clock pulse may consist of first to fourth A-clock pulses (A-CLK_1 to A-CLK_4) having different phase differences and overlapping part of their pulse widths between adjacent ones. FIG. 2 shows an example in which the widths of adjacent A-clock pulses are overlapped by 1/2, which is only one example, and the size of the overlapping can be changed as much as possible. On the other hand, these A-clock pulses may be output without being overlapped with each other.

The A-clock pulse is used as the A-output pulse (A-OUT_n-1 to A-OUT_n + 2), i.e., the A-scan pulse and the A-carry pulse. For example, when a four-phase A-clock pulse (A-CLK_1 to A-CLK_4) is used as shown in FIG. 2, the A- stage of 4i + 1 th (i is a natural number including 0) (A-CLK_1) and outputs a 4i + 1 th A-scan pulse and a 4i + 1 th A1-carry pulse, and the 4i + 2 th A- (A-CLK_3), and outputs the 4i + 3th A-scan pulse and the (4i + 3) -th A- Stage A-stage receives the fourth A-clock pulse (A-CLK_4) and outputs the 4i + 4th A-scan pulse and the 4i + 4th A- And outputs 4i + 4th A-carry pulse.

The B-clock pulse (B-CLK) is used as the B-output pulse, i.e., the B-scan pulse and the B-carry pulse. This B-clock pulse (B-CLK) is output every period (each frame period, the next period of the last horizontal period; hereinafter referred to as B-output period T_B) of each frame period as described above. Accordingly, the B-carry pulse and the B-scan pulse are also output every B-output period T_B.

In FIG. 2, three frame periods are shown. At the end of each frame period, there is a blank period (BK) in which various signals necessary for the next frame period are set. However, a data signal necessary for displaying an image is not included in the various signals described above. That is, this data signal is not generated in this blank period BK.

The above-described B-output period T_B is included in this blank period BK. That is, the B-clock pulse (B-CLK), the B-scan pulse and the B-carry pulse described above are generated during the blank period BK.

On the other hand, the A-clock pulses A-CLK_1 to A-CLK_4 have a smaller pulse width than the B-clock pulses B-CLK.

The A-scan pulses included in the A-output pulses A-OUT_n-1 to A-OUT_n + 2 are generated based on the A-clock pulses A-CLK_1 to A-CLK_4 described above, As described above, adjacent ones have a form in which a part of the pulse width thereof overlaps. At this time, the A-scan pulses are sequentially output one frame at a time during one frame period.

The B-scan pulses included in the B-output pulses B-OUT_n to B-OUT_n + 2 are generated based on the B-clock pulse B-CLK described above, Is output in the same form and timing as the pulse (B-CLK). At this time, since the B-scan pulse is outputted once per one frame period, its output position changes according to the frame period. For example, a B-scan pulse (e.g., B-OUT_n) is output from the n-th B-stage (B-ST_n) during the first leftmost frame period, (B-OUT_n + 1) is output from the (n + 1) th B-stage (B-ST_n + 1) and the B-scan pulse During the third frame period, a B-scan pulse (for example, B-OUT_n + 2) is output from the (n + 2) th B-stage (B-ST_n + 2).

As the output position of the B-scan pulse changes in each frame period, the distance between the A-scan pulse and the B-scan pulse corresponding to each other in one frame period is gradually reduced as shown in FIG.

2, a period during which the first to fourth A-clock pulses A-CLK_1 to A-CLK_4 are output in one frame period is defined as an A-output period T_A, When the remaining period is defined as the B-output period T_B as described above, the first to fourth A-clock pulses A-CLK_1 to A-1 during the B-output period T_B of the one frame period T_F And -CLK_4 may all remain in a low state. Of course, during the B-output period T_B, the first to fourth A1-clock pulses A1-CLK_1 to A1-CLK_4 may be output as they are in the A-output period T_A.

5 is a block diagram of the B-stage of FIG.

One B-stage (for example, B-ST_n) includes a node controller B-NC and a B-scan output switching element B-SCO, as shown in FIG.

The node control unit B-NC controls the voltage state of the B-set node B-Q according to the enable signal EN and the A-carry pulse A-CR from the A-stage.

The B-scan output switching element (B-SCO) is controlled according to the voltage of the B-set node (BQ), and the B-clock transmission line and the B-scan output terminal B-SOT). The B-scan output switching element B-SCO is turned on or off according to the voltage of the B-set node BQ and outputs the B-clock pulse B-CLK on the B- Terminal (B-SOT). The B-clock pulse B-CLK output through the B-scan output terminal B-SOT of the n-th B-stage B-ST_n becomes the B-scan pulse B-SC_n.

Hereinafter, the specific configuration of the B-stage will be described with reference to the drawings.

6 is a diagram showing the circuit configuration of the n-th B-stage according to the first embodiment of the present invention.

The nth B-stage B-ST_n according to the first embodiment includes the set switching element STr, the reset switching element RTr, and the B-scan output switching element B- SCO).

Here, the B-scan output switching element (B-SCO) in the first embodiment is the same as that in the above-described FIG. 5, and therefore, the description related to FIG. 5 is referred to.

The set switching element STr provided in the n-th B-stage B-ST_n is controlled in accordance with the A-carry pulse A-CR_n + 2 from the (n + And is connected to the enable line for transmitting the enable signal EN and the B-set node BQ. The set switching element STr is turned on or off according to the (n + 2) th A-carry pulse A-CR_n + 2, and the turn- ).

the reset switching element RTr provided in the n-th B-stage B-ST_n is controlled in accordance with the A-carry pulse A-CR_n from the n-th A-stage A-ST_n, And is connected between a node BQ and a discharge power supply line for transmitting a discharge voltage source VSS. The reset switching element RTr is turned on or off according to the n-th A-carry pulse A-CR_n and supplies the turn-on discharge voltage VSS to the B-set node BQ do.

Here, the reset switching element RTr may be supplied with the enable signal EN from the enable line instead of the above-described discharge voltage VSS.

7 is a diagram showing the circuit configuration of the n-th B-stage according to the second embodiment of the present invention.

The nth B-stage B-ST_n according to the second embodiment includes a set switching element STr, a reset switching element RTr and a B-scan output switching element B- SCO).

Here, the B-scan output switching element (B-SCO) in the second embodiment is the same as that in the above-described FIG. 5, and therefore, the description related to FIG. 5 is referred to.

Since the set switching element STr in the second embodiment is the same as that in Fig. 6 described above, the description related to Fig. 6 will be referred to.

The reset switching element RTr provided in the n-th B-stage B-ST_n is controlled in accordance with a control signal ECS from the outside, and transmits the B-set node BQ and the discharge voltage source VSS And is connected between the discharge power supply lines. The reset switching element RTr is turned on or off according to the n-th A-carry pulse A-CR_n and supplies the turn-on discharge voltage VSS to the B-set node BQ do.

Here, the reset switching element RTr may be supplied with the enable signal EN from the enable line instead of the above-described discharge voltage VSS.

8 is a diagram showing the circuit configuration of the n-th B-stage according to the third embodiment of the present invention.

The n-th B-stage B-ST_n according to the third embodiment includes a set switching element STr, a first reset switching element RTr1, a second reset switching element RTr2) and a B-scan output switching element (B-SCO).

Here, the B-scan output switching element (B-SCO) in the third embodiment is the same as that in the above-described FIG. 5, and therefore, the description related to FIG. 5 is referred to.

The set switching element STr in the third embodiment is the same as that in FIG. 6 described above, and therefore, the description related to FIG. 6 is referred to.

The first reset switching element RTr1 in the third embodiment is the same as the reset switching element RTr in FIG. 6 described above, and therefore, the description related to FIG. 6 is referred to.

The second reset switching element RTr2 in the third embodiment is the same as the reset switching element RTr in Fig. 7 described above, and therefore, the description related to Fig. 6 is referred to.

9 is a diagram showing the circuit configuration of the n-th B-stage according to the fourth embodiment of the present invention.

9, the nth B-stage B-ST_n according to the fourth embodiment includes a set switching element STr, a reset switching element RTr, a B1-scan output switching element B1- SCO) and a B2-scan output switching element (B2-SCO).

Here, the set switching element STr and the reset switching element TRr in the fourth embodiment are the same as those in the above-described FIG. 6, respectively, and therefore, the description related to those in FIG. 6 is referred to.

The B1-scan output switching device B1-SCO included in the n-th B-stage B-ST_n is controlled in accordance with the voltage of the B-set node BQ and transmits the B1-clock pulse B1- Clock transmission line and the B1-scan output terminal (B1-SOT). This B1-scan output switching element B1-SCO is turned on or off according to the voltage of the B-set node BQ and turns on B1-clock pulse B1-CLK on the B1- To the terminal (B1-SOT). The B1-clock pulse B1-CLK outputted through the B1-scan output terminal B1-SOT of the n-th B-stage B-ST_n becomes the B1-scan pulse B1-SC_n.

The B2-scan output switching element B2-SCO included in the n-th B-stage B-ST_n is controlled according to the voltage of the B-set node BQ and transmits the B2- Clock transmission line and a B2-scan output terminal (B2-SOT). This B2-scan output switching element B2-SCO is turned on or off according to the voltage of the B-set node BQ and the B2-clock pulse B2-CLK on the turn- Terminal (B2-SOT). The B2-clock pulse B2-CLK output through the B2-scan output terminal B2-SOT of the n-th B-stage B-ST_n becomes the B2-scan pulse B2-SC_n.

Here, the B1-clock pulse B1-CLK may be the same clock pulse as the B-clock pulse B-CLK described above. And the B2-clock pulse B2-CLK may be the same clock pulse as this B1-clock pulse B1-CLK. The B2-clock pulse B2-CLK may be in phase with the B1-clock pulse B1-CLK, or may be a clock pulse having a different pulse width or a different amplitude.

10 is a diagram showing the circuit configuration of the n-th B-stage according to the fifth embodiment of the present invention.

The nth B-stage B-ST_n according to the fifth embodiment includes the set switching element STr, the reset switching element RTr, the B1-scan output switching element B1- SCO) and a B2-scan output switching element (B2-SCO).

Here, the set switching element STr in the fifth embodiment is the same as that in FIG. 6 described above, and therefore, the description related to FIG. 6 will be referred to.

The reset switching elements TRr in the fifth embodiment are the same as those in the above-described FIG. 7, respectively, and therefore, the description related to FIG. 7 will be referred to.

The B1-scan output switching element B1-SCO and the B2-scan output switching element B2-SCO in the fifth embodiment are the same as those in Fig. 9 described above, 9.

The B1-clock pulse B1-CLK and the B2-clock pulse B2-CLK in the fifth embodiment are respectively the same as those in Fig. 9 described above. .

11 is a diagram showing a circuit configuration of an n-th B-stage according to the sixth embodiment of the present invention.

The n-th B-stage B-ST_n according to the sixth embodiment includes a set switching element STr, a first reset switching element RTr1, a second reset switching element Scan output switching elements B1-SCO and B2-scan output switching elements B2-SCO.

Here, the set switching element STr in the sixth embodiment is the same as that in FIG. 6 described above, and therefore, the description related to FIG. 6 will be referred to.

Since the first reset switching element TRr1 in the sixth embodiment is the same as the reset switching element RTr in FIG. 6 described above, the description related to FIG. 6 will be referred to for the description.

Since the second reset switching element TRr2 in the sixth embodiment is the same as the reset switching element RTr in Fig. 7 described above, the description related to Fig. 7 is referred to.

The B1-scan output switching element B1-SCO and the B2-scan output switching element B2-SCO in the sixth embodiment are the same as those in FIG. 9 described above, 9.

The B1-clock pulse B1-CLK and the B2-clock pulse B2-CLK in the sixth embodiment are respectively the same as those in Fig. 9 described above. .

12 is a diagram showing a circuit configuration of an n-th B-stage according to a seventh embodiment of the present invention.

The nth B-stage B-ST_n according to the seventh embodiment includes a set switching element STr, a first B1-reset switching element B1-RTr1, a B1- Output switching element B1-SCO, a B-control switching element B-Ctr and a B2-scan output switching element B2-SCO.

Here, the B1-clock pulse B1-CLK and the B2-clock pulse B2-CLK in the seventh embodiment are respectively the same as those in Fig. 9 described above, .

The set switching element STr provided in the n-th B-stage B-ST_n is controlled in accordance with the A-carry pulse A-CR_n + 2 from the (n + And is connected to the enable line for transmitting the enable signal EN and the B1-set node B1-Q. The set switching element STr is turned on or off according to the (n + 2) th A-carry pulse A-CR_n + 2 and is turned on by the enable signal B1- (EN).

The first B1-reset switching element B1-RTr1 provided in the n-th B-stage B-ST_n is controlled according to the A-carry pulse A-CR_n from the n-th A-stage A- And is connected between the B1-set node (B1-Q) and the first discharge power supply line for transmitting the first discharge-specific voltage source (VSS1). The first B1-reset switching element B1-RTr1 is turned on or off according to the n-th A-carry pulse A-CR_n and the first discharge voltage VSS1 at turn- - Set node (B1-Q).

Here, the first B1-reset switching element B1-RTr1 may be supplied with the enable signal EN from the enable line instead of the first discharge voltage VSS1 described above.

The B1-scan output switching device B1-SCO included in the n-th B-stage B-ST_n is controlled according to the voltage of the B1-set node B1-Q and the B1- And the B1-scan output terminal (B1-SOT). This B1-scan output switching element B1-SCO is turned on or off according to the voltage of the B1-set node B1-Q and turns on B1-clock pulse B1-CLK at B1- To the scan output terminal (B1-SOT). The B1-clock pulse B1-CLK outputted through the B1-scan output terminal B1-SOT of the n-th B-stage B-ST_n becomes the B1-scan pulse B1-SC_n.

The B-control switching element B-Ctr provided in the n-th B-stage B-ST_n is controlled according to the voltage of the B1-set node B1-Q, And is connected between the B2-set nodes (B2-Q). The B-control switching element B-Ctr is turned on or off according to the voltage of the B1-set node B1-Q and is turned on when the B1-set node B1- And electrically connects the nodes (B2-Q).

The first B2-reset switching element B2-RTr1 provided in the n-th B-stage B-ST_n is controlled according to the A-carry pulse A-CR_n from the n-th A-stage A- And is connected between the B2-set node (B2-Q) and the second discharging power supply line for transmitting the second discharging voltage source (VSS2). The first B2-reset switching element B2-RTr1 turns on or off according to the n-th A-carry pulse A-CR_n and turns on the second discharge voltage VSS2 at the turn- - to the set node (B2-Q).

Here, the first B2-reset switching element B2-RTr1 may be supplied with the enable signal EN from the enable line instead of the second discharge voltage VSS2 described above.

The B2-scan output switching element B2-SCO provided in the n-th B-stage B-ST_n is controlled according to the voltage of the B2-set node B2-Q and the B2- And a B2-SCL output terminal (B2-SOT). This B2-scan output switching element B2-SCO is turned on or off according to the voltage of the B2-set node B2-Q and turns on the B2-clock pulse B2- To the scan output terminal (B2-SOT). The B2-clock pulse B2-CLK output through the B2-scan output terminal B2-SOT of the n-th B-stage B-ST_n becomes the B2-scan pulse B2-SC_n.

13 shows the switching elements that can be added to the n-th B-stage. The n-th stage shown in Fig. 12 includes the second B1-reset switching element B1-RTr2 shown in Fig. 13, And a B2-reset switching element (B2-RTr2).

As shown in Fig. 13A, the second B1-reset switching element B1-RTr2 provided in the n-th B-stage B-ST_n is controlled in accordance with a control signal ECS from the outside And is connected between the B1-set node B1-Q and the first discharge power supply line for transmitting the first discharge voltage VSS1. The second B1-reset switching element B1-RTr2 is turned on or off according to a control signal ECS from the outside, and the first discharging voltage VSS1 at turn- (B1-Q).

As shown in FIG. 13B, the second B2-reset switching element B2-RTr2 provided in the n-th B-stage B-ST_n is controlled in accordance with a control signal ECS from the outside And is connected between the B2-set node (B2-Q) and the second discharging power supply line for transmitting the second discharging voltage VSS2. The second B2-reset switching element B2-RTr2 is turned on or off according to a control signal ECS from the outside, and the second discharging voltage VSS2 at the turn- (B2-Q).

FIG. 14 is a diagram showing a circuit configuration of an n-th B-stage according to an eighth embodiment of the present invention.

The n-th B-stage B-ST_n according to the eighth embodiment includes the set switching element STr, the reset switching element RTr, the B-scan output switching element B- SCO) and a B-carry output switching element (B-CRO).

Since the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the eighth embodiment are the same as those in Fig. 6 described above, respectively, Refer to FIG. 6 for a description.

the B-carry output switching element B-CRO provided in the n-th B-stage B-ST_n is controlled according to the voltage of the B-set node BQ, B-scan output terminal (B-SOT). The B-carry output switching element B-CRO is turned on or off according to the voltage of the B-set node BQ, and the B-scan output terminal B- - The scan pulse (B-SC_n) is supplied to the B-carry output terminal (B-COT). The B-scan pulse B-SC_n output via the B-carry output terminal B-COT of the n-th B-stage B-ST_n becomes the B-scan pulse B-SC_n.

15 is a diagram showing a circuit configuration of an n-th B-stage according to a ninth embodiment of the present invention.

The nth B-stage B-ST_n according to the ninth embodiment includes a set switching element STr, a reset switching element RTr, a B-scan output switching element B- SCO) and a B-carry output switching element (B-CRO).

The set switching element STr and the B-scan output switching element B-SCO in the ninth embodiment are the same as those in the above-described FIG. 6, respectively. do.

Note that the reset switching element RTr in the ninth embodiment is the same as that in Fig. 7 described above, and therefore the description thereof will be referred to the contents of Fig.

The B-carry output switching element (B-CRO) in the ninth embodiment is the same as that in Fig. 14 described above, and therefore, the description thereof will be given with reference to Fig.

16 is a diagram showing a circuit configuration of an n-th B-stage according to a tenth embodiment of the present invention.

The nth B-stage (B-ST_n) according to the tenth embodiment includes a set switching element STr, a first reset switching element RTr1, a second reset switching element Scan output switching element B-SCO, and a B-carry output switching element B-CRO.

The set switching element STr and the B-scan output switching element B-SCO in the tenth embodiment are the same as those in the above-described FIG. 6, respectively. do.

The first reset switching element RTr1 in the tenth embodiment is the same as the reset switching element RTr in Fig. 6 described above, and therefore, the description thereof is given with reference to Fig.

The second reset switching element RTr2 in the tenth embodiment is the same as the reset switching element RTr in Fig. 7 described above, and therefore, the description thereof will be made with reference to Fig.

The B-carry output switching element (B-CRO) in the tenth embodiment is the same as that in the above-described Fig. 14, and therefore, the description of Fig. 14 is referred to.

17 is a diagram showing a circuit configuration of an n-th B-stage according to an eleventh embodiment of the present invention.

The nth B-stage B-ST_n according to the eleventh embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B- CRO) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the eleventh embodiment are the same as those in Fig. 6 described above, respectively, Refer to FIG. 6 for a description.

the B-carry output switching element B-CRO included in the n-th B-stage B-ST_n is controlled according to the voltage of the B-set node BQ and transmits the B- And a B-clock transmission line and a B-carry output terminal (B-COT). The B-carry output switching element B-CRO is turned on or off according to the voltage of the B-set node BQ and the B-carry pulse B-CLK on the turn- Terminal (B-COT). The B-clock pulse B-CLK output through the B-carry output terminal B-COT of the n-th B-stage B-ST_n becomes the B-carry pulse B-CR_n.

FIG. 18 is a diagram showing a circuit configuration of an n-th B-stage according to a twelfth embodiment of the present invention.

The n-th B-stage B-ST_n according to the twelfth embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B- CRO) and a B-scan output switching element (B-SCO).

The set switching element STr and the B-scan output switching element B-SCO in the twelfth embodiment are the same as those in the above-described FIG. 6, respectively. do.

The reset switching element RTr in the twelfth embodiment is the same as that in Fig. 7 described above, and therefore, the description of Fig. 7 is referred to.

The B-carry output switching element (B-CRO) in the twelfth embodiment is the same as that in the above-described FIG. 17, and therefore, the description of FIG. 17 is referred to.

19 is a diagram showing the circuit configuration of the n-th B-stage according to the thirteenth embodiment of the present invention.

The nth B-stage (B-ST_n) according to the thirteenth embodiment includes a set switching element STr, a first reset switching element RTr1, a second reset switching element (B-CRO), and a B-scan output switching element (B-SCO).

The set switching element STr and the B-scan output switching element B-SCO in the thirteenth embodiment are the same as those in the above-described FIG. 6, respectively. do.

The first reset switching element RTr1 in the thirteenth embodiment is the same as the reset switching element RTr in FIG. 6 described above, and therefore, the description of FIG. 6 is referred to.

The second reset switching element RTr2 in the thirteenth embodiment is the same as the reset switching element RTr in FIG. 7 described above, and therefore, the description thereof will be given with reference to FIG.

The B-carry output switching element (B-CRO) in the thirteenth embodiment is the same as that in the above-described FIG. 17, and the description thereof is made with reference to FIG.

20 is a diagram showing a circuit configuration of an n-th B-stage according to a fourteenth embodiment of the present invention.

The nth B-stage (B-ST_n) according to the fourteenth embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B- CRO), a B-scan output switching element (B-SCO), and a B-carry discharge switching element (B-CRD).

Since the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the fourteenth embodiment are the same as those in Fig. 6 described above, respectively, Refer to FIG. 6 for a description.

The B-carry output switching element (B-CRO) in the fourteenth embodiment is the same as that in the above-described Fig. 17, and therefore, the description thereof is made with reference to Fig.

the B-carry discharge switching element B-CRD included in the n-th B-stage B-ST_n is controlled according to the voltage of the B-reset node B-QB and the B- COT) and a second discharge power supply line for transferring the second discharge voltage VSS2. The B-carry discharge switching element B-CRD is turned on or off according to the voltage of the B-reset node B-QB and is turned on or off at the B-carry output terminal B-COT And supplies the second discharge voltage VSS2.

Here, either the A-carry pulse, the start pulse, or the voltage of the reset node of the A-stage can be applied to the B-reset node B-QB.

FIG. 21 is a diagram showing a circuit configuration of an n-th B-stage according to a fifteenth embodiment of the present invention.

The nth B-stage B-ST_n according to the fifteenth embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B- CRO), a B-scan output switching element (B-SCO), and a B-carry discharge switching element (B-CRD).

The set switching element STr and the B-scan output switching element B-SCO in the fifteenth embodiment are the same as those in the above-described FIG. 6, respectively. do.

The reset switching element RTr in the fifteenth embodiment is the same as those in the above-described Fig. 7, and therefore, the description thereof is made with reference to Fig.

The B-carry output switching element (B-CRO) in the fifteenth embodiment is the same as that in the above-described Fig. 17, and therefore, the description of Fig. 17 is referred to.

The B-carry discharge switching element (B-CRD) in the fifteenth embodiment is the same as that in the above-described Fig. 20, and therefore, the description thereof is made with reference to Fig.

22 is a diagram showing a circuit configuration of an n-th B-stage according to a sixteenth embodiment of the present invention.

The n-th B-stage (B-ST_n) according to the sixteenth embodiment includes a set switching element STr, a first reset switching element RTr1, a second reset switching element (B-CRO), a B-scan output switching element (B-SCO) and a B-carry discharge switching element (B-CRD).

The set switching element STr and the B-scan output switching element B-SCO in the sixteenth embodiment are the same as those in the above-described FIG. 6, respectively. do.

The first reset switching element RTr1 in the sixteenth embodiment is the same as the reset switching element RTr in FIG. 6 described above, and therefore, the description of FIG. 6 is referred to.

The second reset switching element RTr2 in the sixteenth embodiment is the same as the reset switching element RTr in FIG. 7 described above, and therefore, the description thereof is made with reference to FIG.

The B-carry output switching element (B-CRO) in the sixteenth embodiment is the same as that in the above-described Fig. 17, and therefore, the description thereof is made with reference to Fig.

The B-carry discharge switching element (B-CRD) in the sixteenth embodiment is the same as that in the above-described FIG. 20, and therefore, the description of FIG. 20 is referred to.

23 is a diagram showing a circuit configuration of an n-th B-stage according to a seventeenth embodiment of the present invention.

The nth B-stage (B-ST_n) according to the 17th embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B- CRO), a B1-scan output switching element B1-SCO, a B2-scan output switching element B2-SCO and a B-carry discharge switching element B-CRD.

Since the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the seventeenth embodiment are the same as those in Fig. 6 described above, respectively, Refer to FIG. 6 for a description.

The B1-scan output switching element B1-SCO and the B2-scan output switching element B2-SCO in the 17th embodiment are the same as those in Fig. 9 described above, 9.

The B1-clock pulse B1-CLK and the B2-clock pulse B2-CLK in the 17th embodiment are the same as those in Fig. 9 described above, respectively. .

The B-carry output switching element B-CRO included in the n-th B-stage B-ST_n is controlled according to the voltage of the B-set node BQ and transmits the B1-clock pulse B1-CLK Clock transmission line and a B-carry output terminal (B-COT). The B-carry output switching element B-CRO is turned on or off according to the voltage of the B-set node BQ and the B-carry pulse B-CLK on the turn- Terminal (B-COT). The B1-clock pulse B1-CLK output through the B-carry output terminal B-COT of the n-th B-stage B-ST_n becomes the B-carry pulse B-CR_n.

FIG. 24 is a diagram showing a circuit configuration of an n-th B-stage according to an eighteenth embodiment of the present invention.

The nth B-stage B-ST_n according to the eighteenth embodiment includes the set switching element STr, the reset switching element RTr, the B-carry output switching element B- CRO), a B1-scan output switching element B1-SCO, a B2-scan output switching element B2-SCO and a B-carry discharge switching element B-CRD.

The set switching element STr and the B-scan output switching element B-SCO in the eighteenth embodiment are the same as those in the above-described FIG. 6, respectively. do.

Since the reset switching element RTr in the eighteenth embodiment is the same as that in the above-described FIG. 7, the description of FIG. 7 is referred to for the description.

The B1-scan output switching element B1-SCO and the B2-scan output switching element B2-SCO in the eighteenth embodiment are the same as those in FIG. 9 described above, 9.

The B-carry output switching element (B-CRO) in the eighteenth embodiment is the same as that in the above-described FIG. 23, and therefore, the description of FIG. 23 is referred to.

The B1-clock pulse B1-CLK and the B2-clock pulse B2-CLK in the eighteenth embodiment are the same as those in the above-described FIG. 9, respectively. .

25 is a diagram showing a circuit configuration of an n-th B-stage according to a nineteenth embodiment of the present invention.

The nth B-stage (B-ST_n) according to the nineteenth embodiment includes a set switching element STr, a first reset switching element RTr1, a second reset switching element (B2-SCO) and a B-carry discharge switching element (B-CRD), a B-carry output switching element (B-CRO) .

The set switching element STr and the B-scan output switching element B-SCO in the nineteenth embodiment are the same as those in the above-described FIG. 6, respectively. do.

The first reset switching element RTr1 in the nineteenth embodiment is the same as the reset switching element RTr in Fig. 6 described above, and therefore, the description of Fig. 6 is referred to.

The second reset switching element RTr2 in the nineteenth embodiment is the same as the reset switching element RTr in Fig. 7 described above, and therefore, the description thereof is made with reference to Fig.

The B1-scan output switching element B1-SCO and the B2-scan output switching element B2-SCO in the nineteenth embodiment are respectively the same as those in Fig. 9 described above, 9.

The B-carry output switching element (B-CRO) in the nineteenth embodiment is the same as that in Fig. 23 described above, and therefore, the description thereof is made with reference to Fig.

The B1-clock pulse B1-CLK and the B2-clock pulse B2-CLK in the nineteenth embodiment are the same as those in Fig. 9 described above, respectively. .

26 shows switching devices that may be added to the n-th B-stage, where the n-th stage shown in Figs. 6-12 and Figs. 14-25 includes the first structure shown in Fig. 26 (Fig. 26A), the second structure (Fig. 26B), and the third structure (Fig. 26C).

The first structure includes a circuit corresponding to (a) in Fig.

The first B-control switching element B-Ctr1 provided in the n-th B-stage B-ST_n receives the B-clock pulse B-CLK or F- Is controlled according to the clock pulse F-CLK and is connected between the B-set node BQ and the B-scan output terminal B-SOT. The first B-control switching element B-Ctr1 is turned on or off according to the B-clock pulse B-CLK or the F-clock pulse F-CLK, And connects the node BQ and the B-scan output terminal (B-SOT). Here, the F-clock pulse (F-CLK) is the same pulse as the A-clock pulse or another pulse.

The second structure includes a circuit corresponding to Fig. 26 (b).

This second structure includes a capacitor C1, a first B-control switching element B-Ctr1 and a second B-control switching element B-Ctr2, as shown in Figure 26 (b) do.

As shown in FIG. 26B, a B-clock pulse B-CLK or a G-clock pulse G (1) is supplied to one terminal of the capacitor C1 provided in the n-th B- -CLK) is supplied.

The first B-control switching element B-Ctr1 provided in the n-th B-stage B-ST_n is controlled according to the voltage of the B-related set node, as shown in Fig. 26 (b) Is connected between the other terminal of the capacitor C1 and the discharge power supply line for transmitting the discharge voltage VSS. The first B-control switching element B-Ctr1 is turned on or off according to the voltage of the B-related set node, and supplies the turn-on discharge voltage VSS to the other terminal of the capacitor C1 do.

26B, the second B-control switching element B-Ctr2 provided in the n-th B-stage B-ST_n is connected to the voltage applied to the other terminal of the capacitor C1 And is connected between the B related set node and the B related scan output terminal. The second B-control switching element B-Ctr2 is turned on or off according to the voltage applied to the other terminal of the capacitor C1, and the turn-on B related set node and the B related scan output terminal Connect.

Here, the G-clock pulse G-CLK is a clock pulse which is the same as or different from the B-clock pulse B-CLK, in particular within the pulse width of this G-clock pulse G- And a rising edge of the B-CLK.

The third structure includes a circuit corresponding to (c) in Fig.

As shown in Fig. 26C, the capacitor C2 provided in the n-th B-stage B-ST_n is connected between the B-related set node and the B-related scan output terminal.

On the other hand, the B related set node described in Fig. 26 means any one of the B-set node BQ, B1-set node B1-Q and B2-set node B2-Q described above, The B-related scan output terminals described in FIG. 26 denote any one of the B-scan output terminal (B-SOT), the B1-scan output terminal (B1-SOT), and the B2-scan output terminal (B2-SOT).

Hereinafter, a detailed circuit configuration of the A-stages will be described.

27 is a diagram showing a circuit configuration of an n-th A-stage according to the first embodiment of the present invention.

The nth A-stage according to the first embodiment includes a node controller NC, an A-carry output switching element A-CRO, an A1-scan output switching element A1-SCO, , An A2-scan output switching element (A2-SCO) and an A-carry discharge switching element (A-CRD).

The node controller NC provided in the n-th A-stage generates the A-set pulse in accordance with at least one of the A-carry pulse from the np-th stage and the A-carry pulse from the n + AQ and the A-reset nodes A-QB. For example, the node control unit NC provided in the n-th stage may receive the A-set node A-CR_n-1 according to the A-carry pulse A-CR_n-1 from the (n-1) AQ) to a charged state and the A-reset nodes A-QB to a discharged state. The A-set node AQ is put into the discharge state in accordance with the A-carry pulse A-CR_n + 2 from the (n + 2) th A-stage A- A-QB) to a charged state.

The A-carry output switching element A-CRO included in the n-th A-stage A-ST_n is controlled in accordance with the voltage of the A-set node AQ and transmits the A1- Clock transmission line and the A-carry output terminal (A-COT). The A-carry output switching element A-CRO is turned on or off according to the voltage of the A-set node AQ and outputs the A1-clock pulse A1-CLK at the turn- Terminal (A-COT). The A1-clock pulse A1-CLK outputted through the A-carry output terminal A-COT of the n-th A-stage A-ST_n becomes the A-carry pulse A-CR_n.

The A1-scan output switching device A1-SCO included in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A1- (A1-SOT). This A1-scan output switching element A1-SCO is turned on or off according to the voltage of the A-set node AQ and outputs A1-clock pulse A1-CLK at turn- To the terminals A1-SOT. The A1-clock pulse A1-CLK outputted through the A1-scan output terminal A1-SOT of the n-th A-stage A-ST_n becomes the A1-scan pulse A1-SC_n.

The A2-SCO output switching device A2-SCO included in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ and transmits the A2-clock pulse A2- And the A2-scan output terminal (A2-SOT). This A2-scan output switching element A2-SCO is turned on or off according to the voltage of the A-set node AQ and outputs A2-clock pulse A2-CLK at turn- Terminal (A2-SOT). The A2-clock pulse A2-CLK outputted through the A2- scan output terminal A2-SOT of the n-th A-stage A-ST_n becomes the A2-scan pulse A2-SC_n.

The A-carry discharge switching element A-CRD included in the n-th A-stage A-ST_n is controlled according to the voltage of the A-reset node A-QB, and the A- COT) and a discharge power supply line for transmitting a discharge voltage (VSS). This A-carry discharge switching element A-CRD is turned on or off according to the voltage of the A-reset node A-QB and is turned on at the A-carry output terminal A-COT Supply the discharge voltage (VSS).

Here, the A1-clock pulse A1-CLK may be the same clock pulse as the A-clock pulses A-CLK_1 to A-CLK_4 described above. For example, the A1-clock pulse A1-CLK may be any one of a first A-clock pulse A-CLK_1 to a fourth A-clock pulse A-CLK_4. And the A2-clock pulse A2-CLK may be the same clock pulse as this A1-clock pulse A1-CLK. This A2-clock pulse A2-CLK may also be in phase with the A1-clock pulse A1-CLK, or may be a clock pulse of different pulse width or of different amplitude.

28 is a diagram showing the circuit configuration of the n-th A-stage according to the second embodiment of the present invention.

The nth A-stage according to the second embodiment includes a node controller NC, an A-carry output switching element A-CRO, an A1-scan output switching element A1-SCO, , An A-control switching element (A-Ctr), an A2-scan output switching element (A2-SCO) and an A-carry discharge switching element (A-CRD).

Here, the A-carry discharge switching element (A-CRD) in the second embodiment is the same as that in Fig. 27 described above, and therefore, the description thereof is made with reference to Fig.

Here, the A1-clock pulse (A1-CLK) and the A2-clock pulse (A2-CLK) in the second embodiment are respectively the same as those in FIG. 27 described above, See the content.

The node controller NC provided in the n-th A-stage performs the A-carry operation in accordance with at least one of the A-carry pulse from the np-th stage and the A-carry pulse from the n + A1-Q and the A-reset nodes A-QB. For example, the node control unit NC provided in the n-th stage may receive the A-set node A-CR_n-1 according to the A-carry pulse A-CR_n-1 from the (n-1) AQ) to a charged state and the A-reset nodes A-QB to a discharged state. The A-set node AQ is put into the discharge state in accordance with the A-carry pulse A-CR_n + 2 from the (n + 2) th A-stage A- A-QB) to a charged state.

The A-carry output switching element A-CRO provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A1-set node A1-Q and the A1- And an A-COT output terminal (A-COT). This A-carry output switching element A-CRO is turned on or off according to the voltage of the A1-set node A1-Q, and turns on the A1-clock pulse A1- To the carry output terminal (A-COT). The A1-clock pulse A1-CLK outputted through the A-carry output terminal A-COT of the n-th A-stage A-ST_n becomes the A-carry pulse A-CR_n.

The A1-scan output switching device A1-SCO included in the n-th A-stage A-ST_n is controlled according to the voltage of the A1-set node A1-Q, and the A1- Output terminals A1 to SOT. This A1-scan output switching element A1-SCO is turned on or off according to the voltage of the A1-set node A1-Q and turns on the A1-clock pulse A1-CLK on the turn- To the scan output terminal (A1-SOT). The A1-clock pulse A1-CLK outputted through the A1-scan output terminal A1-SOT of the n-th A-stage A-ST_n becomes the A1-scan pulse A1-SC_n.

The A-control switching element A-Ctr provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A1-set node A1-Q, And is connected between A2-set nodes A2-Q. The A-control switching element A-Ctr is turned on or off according to the voltage of the A1-set node A1-Q and is turned on when the A1-set node A1- Node A2-Q.

The A2-SCO output switching element A2-SCO provided in the n-th A-stage A-ST_n is controlled in accordance with the voltage of the A2-set node A2-Q and the A2- And the A2-scan output terminal (A2-SOT). This A2-scan output switching element A2-SCO is turned on or off according to the voltage of the A2-set node A2-Q and turns on A2-clock pulse A2-CLK at turn- It is supplied to the scan output terminal (A2-SOT). The A2-clock pulse A2-CLK outputted through the A2- scan output terminal A2-SOT of the n-th A-stage A-ST_n becomes the A2-scan pulse A2-SC_n.

29 is a diagram showing a circuit configuration of the n-th A-stage according to the third embodiment of the present invention.

The n-th A-stage according to the third embodiment includes a node controller NC, an A-carry output switching element A-CRO, an A1-scan output switching element A1-SCO, , An A-control switching element (A-Ctr), an A2-scan output switching element (A2-SCO) and an A-carry discharge switching element (A-CRD).

Here, the A-carry discharge switching element (A-CRD) in the third embodiment is the same as that in Fig. 27 described above, and therefore, the description of Fig. 27 is referred to.

The node control section NC, the A-carry output switching element A-CRO, the A1-scan output switching element A1-SCO and the A2-scan output switching element A2-SCO in the third embodiment Are the same as those in Fig. 28, respectively, and therefore, the description thereof is made with reference to the contents of Fig.

Here, the A1-clock pulse A1-CLK and the A2-clock pulse A2-CLK in the third embodiment are the same as those in Fig. 27 described above, See the content.

The A-control switching element A-Ctr provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-carry output terminal A-COT, And the A2-set node A2-Q. The A-control switching element A-Ctr is turned on or off according to the voltage of the A-carry output terminal A-COT and is turned on when the A-control output terminal A- - Connect set nodes (A2-Q).

30 shows the switching elements that can be added to the nth A-stage. The n-th stage shown in Figs. 27 to 28 includes the A1-scan discharge switching elements A1-SCD and A2 - scan discharge switching elements (A2-SCD).

As shown in FIG. 30A, the A1-scan discharge switching element A1-SCD included in the n-th A-stage A-ST_n is connected to the voltage of the A-reset node A- And is connected between the A1-scan output terminal A1-SOT and the discharge power supply line for transmitting the discharge voltage VSS. The A1-scan discharge switching device A1-SCD is turned on or off according to the voltage of the A-reset node A-QB and is turned on at the A1-scan output terminal A1-SOT at the turn- Supply the discharge voltage (VSS).

As shown in FIG. 30B, the A2-scan discharge switching element A2-SCD included in the n-th A-stage A-ST_n is connected to the voltage of the A-reset node A- And is connected between the A2-scan output terminal (A2-SOT) and the discharge power supply line for transmitting the discharge voltage (VSS). The A2-scan discharge switching element A2-SCD is turned on or off according to the voltage of the A-reset node A-QB and is turned on at the A2-scan output terminal A2-SOT Supply the discharge voltage (VSS).

31 shows switching devices that can be added to the n-th A-stage. The n-th stage shown in Figs. 27 to 28 includes the first A-control switching element (A-Ctr1) and And a second A-control switching element (A-Ctr2).

As shown in FIG. 31A, the first A-control switching element A-Ctr1 provided in the n-th A-stage A-ST_n includes the A1-scan pulses A1-SC_n and A2- Is controlled according to any one of the scan pulses A2-SC_n and is connected between the A-reset node A-QB and the discharge power supply line for transmitting the discharge voltage VSS. The first A-control switching element A-Ctr1 is turned on or off according to one of the A1-scan pulse A1-SC_n and the A2-scan pulse A2-SC_n, And supplies the discharge voltage (VSS) to the A-reset nodes (A-QB).

The second A-control switching element A-Ctr2 provided in the n-th A-stage A-ST_n is controlled according to the B-clock pulse B-CLK as shown in FIG. 31 (b) And is connected between the A-related set node and the discharge power supply line for transmitting the discharge voltage (VSS). This second A-control switching element (A-Ctr2) is turned on or off according to the B-clock pulse (B-CLK) and turns on the discharge voltage (VSS) to the A- Supply. Here, the A related set node means any one of the above-mentioned A related set node A-Q, A1-set node A1-Q and A2-set node A2-Q.

32 is a diagram showing switching elements that can be added to the nth A-stage. The n-th stage shown in Figs. 27 to 28 corresponds to the third A-control switching element (A-Ctr3) and And a fourth A-control switching element (A-Ctr4).

As shown in FIG. 32 (a), the third A-control switching element A-Ctr3 provided in the n-th A-stage A-ST_n includes a B- And is connected between the A-related set node and the discharge power supply line for transmitting the discharge voltage (VSS). This third A-control switching element A-Ctr3 is turned on or off according to the B-carry pulse and transmits the discharge voltage VSS to the set node A related to turn-on. Here, the A related set node means any one of the above-mentioned A related set node A-Q, A1-set node A1-Q and A2-set node A2-Q.

As shown in Figure 32 (b), the fourth A-control switching element A-Ctr4 provided in the n-th A-stage A-ST_n is connected to the B- And is connected between the A-reset node A-QB and the discharge power supply line for transmitting the discharge voltage VSS. The fourth A-control switching element A-Ctr4 is turned on or off according to the B-carry pulse and the discharge voltage VSS is applied to the A-reset node A-QB at the turn- Supply.

Hereinafter, the configuration of the node control unit provided in the A-stage will be described in detail.

33 is a diagram showing the circuit configuration of the node control unit (NC) provided in the n-th A-stage.

The node controller NC provided in the nth A-stage A-ST_n includes a first A-switching element A-Tr1, a second A-switching element A-Tr2, ) And an A-INV (A-INV).

The first A-switching element A-Tr1 included in the n-th A-stage A-ST_n receives the A-carry pulse A-CR_n-1 from the n-1th A- 1), and is connected between the charging power supply line for transmitting the charging voltage VDD and the A-set node AQ. That is, the first A-switching element A-Tr1 is turned on or off according to the (n-1) th A-carry pulse A-CR_n-1, To the A-set node AQ. Here, the charging voltage VDD is a DC voltage having a value capable of turning on the switching element, and is higher than the discharging voltage VSS or the u-discharging voltage (u is a natural number) described above.

However, since there is no stage in the previous stage of the first A-stage (i.e., the first A-stage) that operates first among all the stages in one frame period T_F, the first A- The first A-switching element A-Tr1 provided in the first A-stage A-ST_n is supplied with the start pulse Vst from the previous A- The start pulse Vst is supplied instead.

the second A-switching element A-Tr2 provided in the n-th A-stage A-ST_n receives the A-carry pulse A-CR_n + 2 from the (n + 2), and is connected between the A-set node AQ and the first discharging power supply line for transmitting the first discharging voltage VSS1. The second A-switching element A-Tr2 is turned on or off according to the (n + 2) th A2-carry pulse A-CR_n + 2, And supplies the first discharge voltage VSS1.

The A-INV included in the n-th A-stage A-ST_n has the logic of the voltage of the A-set node AQ and the logic of the voltage of the A-reset node A-QB The voltage of the A-reset node A-QB is controlled in accordance with the voltage of the A-set node AQ so as to be opposite to the voltage of the A-set node AQ. For example, when the voltage of the A-set node AQ is in the high state (i.e., the charging state), the A-INV inverts the voltage of the A-reset node A- (A-INV) changes the voltage of the A-reset node A-QB to a high state (i.e., a discharge state). On the contrary, when the voltage of the A- . At this time, the A-INV inverts the voltage of the A-reset node A-QB to a high state using the high voltage VH and the voltage of the A-reset node A- (A-QB) to a low state.

The n-th A-stage A-ST_n includes an output unit OU. The output unit OU includes an A-carry output switching element A-CRO, an A- (A-SCD), an A-scan output switching element (A-SCO), and an A-scan discharge switching element (A-SCD).

The A-carry output switching element A-CRO, the A-carry discharge switching element A-CRD and the A-scan output switching element A-SCO shown in Fig. 33 correspond to the A- Scan discharge switching element A-SCD of FIG. 33 corresponds to the element A-CRO, the A-carry discharge switching element A-CRD and the A1-scan output switching element A1-SCO Corresponds to the A1-scan discharge switching element (A1-SCD) in Fig.

The operation of the A-stage (A-ST_n) will be described with reference to the configuration of the A-stage (A-ST_n) of FIG. 2 to FIG. 4 and FIG.

1) Set point

(A-OUT_n-1 in Fig. 2) from the (n-1) th A-stage (A-ST_n-1) to the set timing (t_s) Is supplied to the first A-switching element (A-Tr1) of the n-th A-stage (A-ST_n). Thus, the first A-switching device A-Tr1 is turned on and the charging voltage VDD is supplied to the n-th A-stage through the first A- Is supplied to the A-set node AQ of the node A-ST_n. Therefore, the A-set output node AQ is charged and the A-carry output switching element A-CRO and the A-scan output switching element (A-CRO) connected to the charged A- A-SCO) is turned on.

In addition, since the voltage of the charged A-set node A-Q is in a high state, the A-inverting part A-INV discharges the A-reset node A-QB to a low voltage. Therefore, the A-carry discharge switching element A-CRD and the A-scan discharge switching element A-SCD connected to the discharged A-reset nodes A to QB via the gate electrode are turned off .

(A-OUT_n + 2 in Fig. 2) from the (n + 2) th A-stage A-ST_n + 2 to the set time t_s of the nth A- Is in the low state, the second A-switching element (A-Tr2) supplied through the gate electrode thereof is turned off.

The A-set node AQ of the A-stage A-ST_n is charged at the set time t_s of the n-th A-stage A-ST_n and the A- Is discharged, thereby setting the A-stage (A-ST_n).

2) Output point

Then, a second A-clock pulse (A-CLK_2) is applied to the A-stage (A-ST_n) at the output timing t_o of the n-th A-stage (A-ST_n). That is, the second A-clock pulse (A-CLK_2) is applied to both the A-carry output switching element (A-CRO) and the A-scan output switching element (A-SCO) in the turn-on state. Thus, an A-carry pulse (A1-OUT_n in FIG. 2) is output via the turn-on A-carry output switching element A-CRO and the turn-on A- Scan pulse (A1-OUT_n in Fig. 2) is output via the A-scan pulse (-SCO).

At this time, as the first A-clock pulse A-CLK_1 transitions from the high state to the low state at the polling time TL of the first A-clock pulse A-CLK_1, the first A- (A-OUT_n-1 in FIG. 2) of the n-th A-stage (A-ST_n) generated by the n-th stage A-ST_n transitions from a high state to a low state, And the A-switching element (A-Tr1) is turned off. At this polling point TL, the A-set node AQ in the n-th A-stage A-ST_n is brought into a floating state, and thus the second A- The voltage of the A-set node AQ is bootstrapped by the instant coupling phenomenon when the pulse A-CLK_2 is input to the A-stage A-ST_n. Therefore, the A-carry output switching element A-CRO and the A-scan output switching element A-SCO are almost completely turned on and the A-carry pulse (A-OUT_n in FIG. - A scan pulse (A-OUT_n in FIG. 2) is stably outputted.

(A-OUT_n in FIG. 2) output through the A-carry output terminal (A-COT) of the n-th A-stage (A-ST_n) 1) and the (n-2) th A-stage (A-ST_n-2). Thus, the n + 1th A-stage A-ST_n + 1 is set and the n-2th A-stage A-ST_n-2 is reset.

The A-scan pulse (A-OUT_n in FIG. 2) output through the A-scan output terminal A-SOT of the n-th A-stage A-ST_n is supplied to the corresponding signal line.

3) Reset  Point

(A-OUT_n + 2 in Fig. 2) from the (n + 2) th A-stage A-ST_n + 2 at the reset time t_r of the nth A- Is in a high state. Thus, the second A-switching element (A-Tr2) of the nth A-stage (A-ST_n) receiving the A-carry pulse (A-OUT_n + 2 in FIG. 2) is turned on. Then, the first discharging voltage VSS1 is supplied to the A-set node A-Q through the turn-on second A-switching element A-Tr2. Therefore, the A-set output node AQ is discharged and the A-carry output switching element A-CRO and the A-scan output switching element (A-CRO) connected to the discharged A- A-SCO) is turned off.

In addition, since the voltage of the discharged A-set node A-Q is in the low state, the A-inverting part A-INV charges the A-reset node A-QB to the high voltage. Therefore, the A-carry discharge switching element A-CRD and the A-scan discharge switching element A-SCD connected to the charged A-reset nodes A to QB through the gate electrode are turned on .

Accordingly, the second discharge voltage VSS2 is output to the A-carry output terminal A-COT via the turn-on A-carry discharge switching element A-CRD, and the turn- The third discharge voltage VSS3 is output to the A-scan output terminal A-SOT via the scan discharge switching element A-SCD. Here, the third discharge voltage VSS3 output through the A-scan output terminal A-SOT of the n-th A-stage A-ST_n is supplied to the corresponding signal line, and the n-th A- Stage A-stage A-ST_n + 1 and the (n-2) -th stage A-ST_n via the A-carry output terminal A- (A-ST_n-2).

In this manner, all of the A-stages output the A-scan pulse and the A-carry pulse once. At this time, the B-stages are operated by the A-carry pulse from the A-stages, here, with reference to the operation of the n-th A-stage and the structure of the B- Stage B-stage will be described in detail.

First, the high-level A-carry pulse A-CR_n (i.e., A-OUT_n in FIG. 2) output from the n-th A-stage A-ST_n at the output timing t_o described above, And supplied to the reset switching element RTr provided in the stage B-ST_n. That is, the A-carry pulse A-CR_n is supplied to the gate electrode of the reset switching element RTr. Thus, the reset switching element RTr is turned on, and the discharge voltage VSS is applied to the B-set node B-Q through the turn-on reset switching element RTr. Then, the B-set node B-Q is discharged, and the B-scan output switching element B-SCO connected to the discharged B-set node B-Q through the gate electrode is turned off.

Next, the A-carry pulse A-CR_n + 2 from the (n + 2) th A-stage (A-ST_n + 2) to the high- And the A-carry pulse A-CR_n + 2 is supplied to the gate electrode of the set switching device STr included in the n-th B-stage B-ST_n. This set switching element STr is thus turned on and the enable signal EN is applied to the B-set node B-Q via the turn-on set switching element STr. Here, the B-set node BQ is discharged during the period from the reset time t_r to the enable time t_en since the enable signal EN is in the low state. However, the enable time t_en The B-set node BQ starts to be charged from the time point t_en as the enable signal EN transits to the high state. Accordingly, the B-scan output switching element B-SCO is turned on from the time point t_en. The B-scan output switching element B-SCO maintains the turned-on state until the n-th A-carry pulse A-CR_n generated in the next frame period is in a high state.

As described above, the B-scan output switching element B-SCO passes the blanking period to the generation time point of the n-th A-carry pulse A-CR_n in the next frame period The B-clock pulse B-CLK having the high state during the blank period is supplied to the B-scan output switching element B-SCO through the turned-on B-scan output switching element B- -SC_n (i.e., B-OUT_n in Fig. 2).

The remaining B-stages are also identical to the operation of the n-th B-stage described above.

The specific circuit configuration of the inverting unit in FIG. 33 will be described.

A- Inverse (A-INV)  1st Example

34 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the first embodiment.

The A-inverting portion A-INV provided in the n-th A-stage (A-Sub) includes the first A-inverting switching element A-iTr1 and the second A- And a switching element A-iTr2.

The first A-inverted switching element A-iTr1 provided in the n-th A-sub stage A-ST_n is controlled according to the first high voltage VH1 from the high power line, And is connected between set nodes A-QB. That is, the first A-inverted switching element A-iTr1 is turned on or off according to the high voltage VH and the high voltage VH on the turn-on state is applied to the A-reset node A-QB Supply.

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A- ) And a low power line carrying a low voltage (VL). That is, the second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- A-QB).

Here, when the first A-inverted switching element A-iTr1 and the second A-inverted switching element A-iTr2 are in the turn-on state, the A-reset node A-QB is brought into the discharging state The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  Second Example

35 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the second embodiment.

The A-inverting unit A-INV included in the n-th A-stage A-ST_n is constituted by a first A-inverting switching element A-iTr1 and a second A- And a switching element A-iTr2.

The first A-inverted switching element A-iTr1 provided in the n-th A-stage A-ST_n is controlled in accordance with a control signal CS from the outside and is connected to a high power line And is connected between the A-reset nodes A-QB. That is, the first A-inverted switching element A-iTr1 is turned on or off according to the control signal CS and the high voltage VH is turned on at the A-reset node A- .

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A- ) And a low power line carrying a low voltage (VL). That is, the second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- A-QB).

Here, the control signal CS is maintained at a low voltage when the A-set node AQ is in a charged state (i.e., high state), and when the A-set node AQ is in a discharging state (i.e., ≪ / RTI > When the control signal CS is at a high voltage, the first A-inverted switching element A-iTr1, which is supplied with the first A-inverted switching element, is turned on. When the control signal CS is at a low voltage, (A-iTr1) is turned off.

Also, when the first A-inversion switching element A-iTr1 and the second A-inversion switching element A-iTr2 are in the turn-on state, the A-reset node A-QB is placed in the discharging state The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  Third Example

36 is a detailed configuration diagram of the A-INV according to the third embodiment.

The A-inverting unit A-INV included in the n-th A-stage A-ST_n includes the first A-inverting switching elements A-iTr1 to A- And a switching element A-iTr4.

The first A-inverted switching element A-iTr1 provided in the n-th A-stage A-ST_n is controlled in accordance with a control signal CS from the outside and is connected to a high power line A-common node A-CN. That is, the first A-inverted switching element A-iTr1 is turned on or off according to the control signal CS and the high voltage VH is turned on to the A-common node A-CN Supply.

The second A-inversion switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, And a low power line that transmits a low voltage (VL). In other words, the second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- -CN).

The third A-inverted switching element A-iTr3 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-common node A-CN, And is connected between the original line and the A-reset nodes A-QB. That is, the third A-inverted switching element A-iTr3 is turned on or off according to the voltage of the A-common node A-CN, and the high voltage VH at the turn- And supplies it to nodes A-QB.

The fourth A-inverted switching element A-iTr4 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A- ) And a low power line carrying a low voltage (VL). That is, the fourth A-inverted switching element A-iTr4 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- A-QB).

Here, the control signal CS is maintained at a low voltage when the A-set node AQ is in a charged state (i.e., high state), and when the A-set node AQ is in a discharging state (i.e., ≪ / RTI > When the control signal CS is at a high voltage, the first A-inverted switching element A-iTr1, which is supplied with the first A-inverted switching element, is turned on. When the control signal CS is at a low voltage, (A-iTr1) is turned off.

Also, when the first A-inversion switching element A-iTr1 and the second A-inversion switching element A-iTr2 are in the turn-on state, the A-reset node A-QB is placed in the discharging state The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  Fourth Example

37 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the fourth embodiment.

The A-inverting unit A-INV included in the n-th A-stage A-ST_n includes the first A-inverting switching elements A-iTr1 to A- And a switching element A-iTr4.

The first A-inverted switching element A-iTr1 provided in the n-th A-stage A-ST_n is controlled according to the high voltage VH from the high power line, and the high- A-QB. That is, the first A-inverted switching element A-iTr1 is turned on or off according to the first high voltage VH1 and the high voltage VH on the turn- ).

The second A-inversion switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, And a low power line that transmits a low voltage (VL). In other words, the second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- -CN).

The third A-inverted switching element A-iTr3 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-common node A-CN, And is connected between the original line and the A-reset nodes A-QB. That is, the third A-inverted switching element A-iTr3 is turned on or off according to the voltage of the A-common node A-CN, and the high voltage VH at the turn- And supplies it to nodes A-QB.

The fourth A-inverted switching element A-iTr4 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A- ) And a low power line carrying a low voltage (VL). That is, the fourth A-inverted switching element A-iTr4 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- A-QB).

Here, when the first A-inverted switching element A-iTr1 and the second A-inverted switching element A-iTr2 are in the turn-on state, the A-reset node A-QB is brought into the discharging state The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  Fifth Example

38 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the fifth embodiment.

The A-inverting unit A-INV included in the n-th A-stage A-ST_n is constituted by the first A-inverting switching elements A-iTr1 to A- And a switching element A-iTr4.

The first A-inverted switching element A-iTr1 provided in the n-th A-stage A-ST_n is controlled according to the high voltage VH from the high power line, and the high- A-CN. The first A-inverted switching element A-iTr1 is turned on or off according to the high voltage VH and supplies the high voltage VH to the A-common node A-CN upon turn-on.

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the A-scan pulse A-SP_n from the n-th A-stage A- And is connected between the A-common node A-CN and a low power line for transmitting the low voltage VL. The second inversion switching element A-iTr2 turns on or off according to the A-scan pulse A-SP_n and turns on the low voltage VL at the turn-on to the A-common node A-CN Supply.

The third A-inverted switching element A-iTr3 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-common node A-CN, And is connected between the original line and the A-reset nodes A-QB. The third A-inverted switching element A-iTr3 is turned on or off according to the voltage of the A-common node A-CN and the high voltage VH on the turn- A-QB.

The fourth A-inverted switching element A-iTr4 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A- ) And a low power line carrying a low voltage (VL). The fourth A-inverted switching element A-iTr4 is turned on or off according to the voltage of the A-set node AQ and is turned on when the turn-on low voltage VL is applied to the A- QB.

On the other hand, when the first A-inverted switching element A-iTr1 and the second A-inverted switching element A-iTr2 are in the turn-on state, the A-reset nodes A- The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  My 6 Example

39 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the sixth embodiment.

The A-inverting unit A-INV included in the n-th A-stage A-ST_n includes a first A-inverting switching element A-iTr1, a second A- A switching element A-iTr2, and an A-capacitor AC.

The first A-inverted switching element A-iTr1 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A-reset node A- And a low power line that transmits a low voltage (VL). That is, the first A-inverted switching element A-iTr1 is turned on or off according to the voltage of the A-set node AQ, and the turn-on low voltage VL is applied to the A- A-QB).

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-reset node A-QB, And the A-scan output terminal (A-SOT). That is, the second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-reset node A-QB, and is turned on when the A-set node AQ Connect the A-scan output terminal (A-SOT).

The A-capacitor AC included in the n-th A-stage A-ST_n is connected to any one of the A-clock transmission line for transmitting the A-clock pulse A-CLK and the A- .

A- Inverse (A-INV)  Seventh Example

40 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the seventh embodiment.

The inverting unit A-INV provided in the n-th A-stage A-ST_n includes the first A-inverting switching elements A-iTr1 to A-inverting switching elements A- (A-iTr3).

The first A-inverted switching element A-iTr1 provided in the nth A-stage A-ST_n is controlled according to the first A-clock pulse A-CLK_1 from the first A-clock transmission line , And between the high power line for transmitting the high voltage (VH) and the A-reset nodes (A-QB). The first A-inverted switching element iTr1 is turned on or off according to the first A-clock pulse A-CLK_1 and the high-voltage VH is turned on at the A-reset node A- Qb. Here, the clock pulse supplied to the first A-inverted switching element iTr1 may be any one of the first through fourth A-clock pulses A-CLK_1 through A-CLK_4 shown in FIG. 2, As one example thereof, a first clock pulse (A-CLK_1) is presented.

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A-reset node A- And a low power line that transmits a low voltage (VL). The second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-set node AQ and is turned on at the A-reset node A- QB.

The third A-inverted switching element A-iTr3 provided in the n-th A-stage A-ST_n is controlled in accordance with the fourth A-clock pulse A-CLK_4 from the fourth A-clock transmission line , And between the A-reset node (A-QB) and the low power supply line for transmitting the low voltage (VL). The third A-inverted switching element A-iTr3 is turned on or off according to the fourth A-clock pulse (A-CLK_4), and the turn-on low voltage VL is applied to the A- A-QB). Here, the clock pulse supplied to the third A-inverted switching element iTr3 can be any one of the first to fourth A-clock pulses A-CLK_1 to A-CLK_4 shown in FIG. 2, As one example, a fourth A-clock pulse (A-CLK_4) is presented.

On the other hand, when the first A-inverted switching element A-iTr1 and the second A-inverted switching element A-iTr2 are in the turn-on state, the A-reset nodes A- The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  Eighth Example

41 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the eighth embodiment.

The inverting portion A-INV included in the n-th A-stage A-ST_n includes the first A-inverted switching elements A-iTr1 to A-inverted switching elements A- (A-iTr3).

The first A-inverted switching element A-iTr1 provided in the nth A-stage A-ST_n is controlled according to the first A-clock pulse A-CLK_1 from the first A-clock transmission line , And is connected between the first A-clock transmission line and the A-reset node (A-QB). The first A-inverted switching element iTr1 is turned on or off in accordance with the first A-clock pulse A-CLK_1 and the first A-clock pulse A-CLK_1 is turned on at A- - to reset nodes A-Qb. Here, the clock pulse supplied to the first A-inverted switching element iTr1 may be any one of the first through fourth A-clock pulses A-CLK_1 through A-CLK_4 shown in FIG. 2, As one example thereof, a first clock pulse (A-CLK_1) is presented.

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A-reset node A- And a low power line that transmits a low voltage (VL). The second A-inverted switching element A-iTr2 is turned on or off according to the voltage of the A-set node AQ and is turned on at the A-reset node A- QB.

The third A-inverted switching element A-iTr3 provided in the n-th A-stage A-ST_n is controlled in accordance with the fourth A-clock pulse A-CLK_4 from the fourth A-clock transmission line , And between the A-reset node (A-QB) and the low power supply line for transmitting the low voltage (VL). The third A-inverted switching element A-iTr3 is turned on or off according to the fourth A-clock pulse (A-CLK_4), and the turn-on low voltage VL is applied to the A- A-QB). Here, the clock pulse supplied to the third A-inverted switching element iTr3 can be any one of the first to fourth A-clock pulses A-CLK_1 to A-CLK_4 shown in FIG. 2, As one example, a fourth A-clock pulse (A-CLK_4) is presented.

On the other hand, when the first A-inverted switching element A-iTr1 and the second A-inverted switching element A-iTr2 are in the turn-on state, the A-reset nodes A- The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

A- Inverse (A-INV)  9th Example

42 is a detailed configuration diagram of the A-inverting unit (A-INV) according to the ninth embodiment.

The A-inverting unit A-INV included in the n-th A-stage A-ST_n includes the first A-inverting switching elements A-iTr1 to A- And a switching element A-iTr4.

The first inverted switching element A-iTr1 provided in the nth A-stage A-ST_n is controlled according to the first A-clock pulse A-CLK_1 from the first A-clock transmission line, (A-CN) and the high-power-line transmitting the voltage VH. The first A-inverted switching element iTr1 turns on or off according to the first A-clock pulse A-CLK_1 and turns on the high voltage VH on the A-common node A-CN ). Here, the clock pulse supplied to the first A-inverted switching element A-iTr1 may be any one of the first to fourth A-clock pulses A-CLK_1 to A-CLK_4 shown in FIG. 2 As an example of this, a first clock pulse (A-CLK_1) is presented.

The second A-inverted switching element A-iTr2 provided in the n-th A-stage A-ST_n is controlled in accordance with the fourth A-clock pulse A-CLK_4 from the fourth A- And is connected between the A-common node A-CN and a low power line for transmitting the low voltage VL. The second A-inverted switching element A-iTr2 is turned on or off according to the fourth A-clock pulse A-CLK_4 and the turn-on low voltage VL is applied to the A- -CN). Here, the clock pulse supplied to the second A-inverted switching element A-iTr2 may be any one of the first to fourth A-clock pulses A-CLK_1 to A-CLK_4 shown in FIG. 2 As an example, a fourth A-clock pulse (A-CLK_4) is presented.

The third A-inverted switching element A-iTr3 provided in the n-th stage A-STn_n is controlled in accordance with the voltage of the A-common node A-CN and is connected to the high- And the A-reset nodes A-QB. The third A-inverted switching element A-iTr3 is turned on or off according to the voltage of the A-common node A-CN and the high voltage VH on the turn- A-QB).

The fourth A-inverted switching element A-iTr4 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the A- ) And a low power line carrying a low voltage (VL). The fourth A-inverted switching element A-iTr4 is turned on or off according to the voltage of the A-set node AQ and is turned on when the turn-on low voltage VL is applied to the A- QB.

On the other hand, when the first A-inverted switching element A-iTr1 and the second inverted switching element A-iTr2 are turned on together, the A-reset node A-QB can be discharged , The size (for example, channel width) of the second A-inverted switching element A-iTr2 is formed to be larger than the size of the first A-inverted switching element A-iTr1.

43 is a diagram showing inverting switching elements that can be added to the A-inverting portion INV. The A-inverting portion A-INV according to the first to ninth embodiments shown in Figs. 34 to 42 And further includes at least one of the fifth to ninth A-inverted switching elements A-iTr5 to A-iTr9 shown in FIG.

The five switching elements will be described in detail as follows.

As shown in Fig. 43A, the fifth A-control switching element A-iTr5 provided in the A-INV of the n-th A-stage A- (A-CR_n-1) from the first A-stage (A-ST_n-1) Line. The fifth A-control switching element A-iTr5 is turned on or off according to the (n-1) th A-carry pulse A-CR_n-1, -QB). ≪ / RTI >

As shown in FIG. 43 (b), the sixth A-control switching element A-iTr6 provided in the A-INV of the n-th A-stage A- Is controlled according to the voltage of the reset nodes A to QB and is connected between the A-set node AQ and the low power line for transmitting the discharge voltage VSS. The sixth A-control switching element A-iTr6 is turned on or off according to the voltage of the A-reset node A-QB and is turned on when the A-set node AQ is turned on. VL).

The A-scan pulse (A-SC_n) or the A-scan pulse (A-SC_n) output from the nth A-stage (A-ST_n) is supplied to the sixth A- (A-SC_n) may be supplied.

As shown in Figure 43 (c), the seventh A-inverted switching element A-iTr7 provided in the A-inverted portion A-INV of the n-th A-stage A- Is connected between the A-set node AQ and the A-clock transmission line for transmitting any one of the A-clock pulses (e.g., A-CLK_1), controlled by the voltage of the reset nodes A- do. The seventh A-inverted switching element A-iTr7 is turned on or off according to the voltage of the A-reset node A-QB and is turned on or off according to the voltage of the A- A-clock pulse (A-CLK_1).

As shown in Figure 43 (d), the eighth A-inversion switching element A-iTr8 provided in the A-INV of the n-th A-stage A- (A1-SOT) of the n-1th A-stage (A-ST_n-1) and the A1-scan output terminal (A1-SOT) of the (A- (AQ). The eighth A-inverted switching element A-iTr8 is turned on or off according to the A-clock pulse (for example, A-CLK_2) And the A-set node AQ.

As shown in FIG. 43 (3), the ninth A-inverted switching element A-iTr9 provided in the A-inverted portion A-INV of the n-th A-stage A- (For example, A-SC_n) from the A-stage of the A-stage, and is connected between the A-reset node AQ and the low power supply line for transmitting the low voltage VL. The ninth A-inverted switching element A-iTr9 is turned on or off according to the scan pulse A-SC_n from the A-stage and is turned on when the low voltage (VL).

44 shows an inverting switching element that can be added to the A-inverting portion INV. The A-inverting portions A-INV shown in Figs. 36 and 37 are respectively the inverting switching elements A- And an A-inversion switching element (A-iTr10).

As shown in FIG. 44, the tenth A-control switching element A-iTr10 included in the A-INV of the n-th A-stage A-ST_n is connected to one of the A- (For example, A-SC_n) from the A-common node A-CN and is connected between the A-common node A-CN and the low power line for transmitting the low voltage VL. The 10th A-control switching element A-iTr10 is turned on or off according to the scan pulse A-SC_n from the A-stage and is turned on at the A-common node A-CN It supplies low voltage (VL).

On the other hand, the A-set node AQ in Figs. 34 to 44 is connected to the A1-set node A1-Q or the A2-Q node according to the circuit configuration of the A-stage including the A- And the A1-scan output terminal A1-SOT may be replaced with the A2-scan output terminal A2-SOT.

Hereinafter, specific configurations of the A-stage and the B-stage corresponding to each other will be described.

The first of the A-stage and B- Example

45 is a diagram showing a first embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the first embodiment includes the A-inverting unit A-INV, the first to third A-switching devices A-Tr1 to A- A-SCO, an A-scan output switching element A-SCO, and an A-scan discharge switching element A -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The third A-switching device A-Tr3 provided in the n-th A-stage A-ST_n is connected to the A-scan output terminal A-SOT of the n-th A-stage A- Is controlled according to the scan pulse A-SC_n and is connected between the A-reset node A-QB and the second discharge power supply line for transmitting the second discharge voltage VSS2. The third A-switching device A-Tr3 is turned on or off according to the n-th A-scan pulse A-SC_n, and is turned on when the A- And supplies the two-room dedicated voltage (VSS2).

The nth B-stage (B-ST_n) according to the first embodiment includes a set switching element STr, a reset switching element RTr and a B-scan output switching element B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the first embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

In the first embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A- - The scan pulse B-SC_n is outputted as one composite pulse Vg_n.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other in the first embodiment.

Stage of the A-stage and the second Example

46 is a diagram showing a second embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the second embodiment includes the A-inverting unit A-INV, the first to fourth A-switching devices A-Tr1 to A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The third A-switching element (A-Tr3) in the second embodiment is the same as that in the above-described Fig. 45, and therefore, the description of Fig. 45 is referred to.

The fourth A-switching element A-Tr4 provided in the n-th A-stage A-ST_n is controlled according to the F-clock pulse F-CLK, and the A- And a fifth discharge power supply line for transmitting the exclusive voltage VSS5. The fourth A-switching element A-Tr4 is turned on or off according to the F-clock pulse F-CLK and is turned on when the fifth discharge voltage VSS5).

Here, the F-clock pulse F-CLK may be a clock pulse having the same phase as the B-clock pulse B-CLK.

The F-clock pulse (F-CLK) may also be the same clock pulse as the B-clock pulse (B-CLK).

The F-clock pulse F-CLK may also be a clock pulse whose high and low voltages are equal to or different from the high and low voltages of the B-clock pulse B-CLK.

The nth B-stage (B-ST_n) according to the second embodiment includes a set switching element STr, a reset switching element RTr, and a B-scan output switching element B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the second embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

In the second embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A- - The scan pulse B-SC_n is outputted as one composite pulse Vg_n.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other in the second embodiment.

Stage of the A-stage and the third Example

47 is a diagram showing a third embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The n-th A-stage A-ST_n according to the third embodiment includes the A-inverting unit A-INV, the first through fifth A-switching devices A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A-carry output switching unit A (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The fourth A-switching device (A-Tr4) in the third embodiment is the same as that in the above-described Fig. 46, and therefore, the description of Fig. 46 is referred to.

The F-clock pulse (F-CLK) in the third embodiment is the same as that in the above-described FIG. 46, and therefore, the description of FIG. 46 is referred to.

The third A-switching device A-Tr3 provided in the n-th A-stage A-ST_n is connected to the B-stage B-CST through the B-carry output terminal B- Carry pulse B-CR_n and is connected between the A-reset node A-QB and the second discharge power supply line for transmitting the second discharge voltage VSS2. The third A-switching element A-Tr3 is turned on or off according to the n-th B-carry pulse B-CR_n and is turned on when the A-reset node A- And supplies the two-room dedicated voltage (VSS2).

The fifth A-switching device A-Tr5 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-reset node A-QB, and the second discharging voltage VSS2, (B-COT) of the n-th B-stage (B-ST_n). The fifth A-switching element A-Tr5 is turned on or off according to the voltage of the A-reset node A-QB and is turned on or off at the B-carry output terminal B-COT And supplies the second discharge voltage VSS2.

The nth B-stage B-ST_n according to the third embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B-CRO) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the third embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

The B-carry output switching element (B-CRO) in the third embodiment is the same as that in Fig. 17 described above, and therefore, the description thereof is made with reference to Fig.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A-SC_n and the B- - The scan pulse B-SC_n is outputted as one composite pulse Vg_n.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other in the third embodiment.

The A-stage and the 4 < th > Example

48 is a diagram showing a fourth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The n-th A-stage A-ST_n according to the fourth embodiment is constituted by the A-inverting unit A-INV, the first through fifth A-switching devices A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The fourth A-switching device (A-Tr4) in the fourth embodiment is the same as that in the above-described Fig. 46, and therefore, the description of Fig. 46 is referred to.

The third A-switching element A-Tr3 and the fifth A-switching element A-Tr5 in the fourth embodiment are the same as those in the above-described Fig. 47, respectively. .

The F-clock pulse (F-CLK) in the fourth embodiment is the same as that in the above-described FIG. 46, and therefore, the description of FIG. 46 is referred to.

The nth B-stage B-ST_n according to the fourth embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B-CRO) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the fourth embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

the B-carry output switching element B-CRO provided in the n-th B-stage B-ST_n is controlled according to the voltage of the B-set node BQ, Is connected between the B-carry output terminal (B-COT) and the F-clock transmission line for transmitting the F-clock pulse (F-CLK). The B-carry output switching element B-CRO is turned on or off according to the voltage of the B-set node BQ and is turned on by the B-carry output terminal B- And supplies a pulse (F-CLK).

In the fourth embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A- - The scan pulse B-SC_n is outputted as one composite pulse Vg_n.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other in the fourth embodiment.

The A-stage and the fifth of the B- Example

49 is a diagram showing a fifth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the fifth embodiment includes an A-inverting portion A-INV, first to fifth A-switching elements A-Tr1 to A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The third A-switching element A-Tr3 and the fifth A-switching element A-Tr5 in the fifth embodiment are respectively the same as those in the above-described Fig. 47, .

The F-clock pulse (F-CLK) in the fifth embodiment is the same as that in the above-described FIG. 46, and therefore, the description of FIG. 46 is referred to.

The fourth A-switching device A-Tr4 provided in the n-th A-stage A-ST_n is connected to the B-stage B-CST through the B-carry output terminal B- And is connected between the A-set node AQ and the fifth discharging power supply line for transmitting the fifth discharging voltage VSS5 according to the B-carry pulse B-CR_n. The fourth A-switching element A-Tr4 is turned on or off according to the B-carry pulse B-CR_n and is turned on when the fifth discharge voltage VSS5).

The nth B-stage (B-ST_n) according to the fifth embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B-CRO) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the fifth embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

The B-carry output switching element (B-CRO) in the fifth embodiment is the same as that in the above-described FIG. 48, and therefore, the description thereof is made with reference to FIG.

In the fifth embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A- - The scan pulse B-SC_n is outputted as one composite pulse Vg_n.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other in the fifth embodiment.

Stage of the A-stage and the sixth stage of the B- Example

50 is a diagram showing a sixth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the sixth embodiment includes an A-inverting unit A-INV, first to fifth A-switching devices A-Tr1 to A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The third A-switching element A-Tr3 and the fifth A-switching element A-Tr5 in the sixth embodiment are respectively the same as those in the above-described Fig. 47, .

Further, the fourth A-switching device (A-Tr4) in the sixth embodiment is the same as those in the above-described Fig. 46, and therefore, the description thereof is given with reference to Fig.

The F-clock pulse (F-CLK) in the sixth embodiment is the same as that in the above-described FIG. 46, and therefore, the description of FIG. 46 is referred to.

The nth B-stage B-ST_n according to the sixth embodiment includes a set switching element STr, a reset switching element RTr, a B-carry output switching element B-CRO) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the sixth embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

the B-carry output switching element B-CRO provided in the n-th B-stage B-ST_n is controlled according to the voltage of the B-set node BQ, B-scan output terminal (B-SOT). This B-carry output switching element (B-CRO) is turned on or off according to the voltage of the B-set node BQ, and is turned on when the B-carry output terminal Connect the output terminal (B-SOT).

In the sixth embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A- - The scan pulse B-SC_n constitutes one composite pulse Vg_n.

The A-scan output terminal (A-SOT) and the B-scan output terminal (B-SOT) may be separated from each other in the sixth embodiment.

The A-stage and the 7th stage of the B- Example

51 is a diagram showing a seventh embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the seventh embodiment includes the A-inverting unit A-INV, the first to fourth A-switching devices A-Tr1 to A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The third A-switching element A-Tr3, the fourth A-switching element A-Tr4 and the F-clock pulse F-CLK in the seventh embodiment are the same as those in the above- And therefore the description thereof is made with reference to the contents of FIG.

51, the n-th B-stage B-ST_n according to the seventh embodiment includes a set switching element STr, a reset switching element RTr, a first B-switching element B-Tr1) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr, and the B-scan output switching element B-SCO in the seventh embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

The first B-switching device B-Tr1 provided in the n-th B-stage B-ST_n is controlled according to the F-clock pulse F-CLK and the B- B-scan output terminal (B-SOT). The B-carry output switching element (B-CRO) is turned on or off according to the F-clock pulse (F-CLK) Connect the output terminal (B-SOT).

According to the seventh embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A- - The scan pulse B-SC_n constitutes one composite pulse Vg_n.

In the seventh embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other.

The A-stage and the 8th stage of the B- Example

52 is a diagram showing an eighth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the eighth embodiment includes the A-inverting unit A-INV, the first to fourth A-switching devices A-Tr1 to A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The fourth A-switching element A-Tr4 and the F-clock pulse F-CLK in the eighth embodiment are the same as those in the above-described Fig. 46, .

The third A-switching device A-Tr3 provided in the n-th A-stage A-ST_n is controlled in accordance with the B-clock pulse B-CLK and the A- And is connected between the second discharge power supply line for transmitting the second discharge specific voltage VSS2. The third A-switching element A-Tr3 is turned on or off according to the B-clock pulse B-CLK and is turned on by the A-reset node A- And supplies the exclusive voltage VSS2.

52, the nth B-stage B-ST_n according to the eighth embodiment includes a set switching element STr, a reset switching element RTr, a first B-switching element B-Tr1) and a B-scan output switching element (B-SCO).

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the eighth embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

The first B-switching element (B-Tr1) in the eighth embodiment is the same as that in the above-described FIG. 51, and therefore, the description of FIG. 51 is referred to.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A-SC_n and the B- - The scan pulse B-SC_n constitutes one composite pulse Vg_n.

The A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other in the eighth embodiment.

Stage of the A-stage and the 9th stage of the B- Example

Fig. 53 is a diagram showing a ninth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the ninth embodiment includes the A-inverting unit A-INV, the first to fourth A-switching devices A-Tr1 to A- (A-SCR), and the A-scan discharge switching element (A-SCR), the A-scan discharge switching element -SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- (A-SCRO), the A-scan discharge switching element (A-SCO) and the A-scan discharge switching element (A-SCD) are the same as those in Fig. 33 Therefore, the description thereof is made with reference to FIG. 33.

The third A-switching element A-Tr3, the fourth A-switching element A-Tr4 and the F-clock pulse F-CLK in the ninth embodiment are the same as those in the above- And therefore the description thereof is made with reference to the contents of FIG.

The nth B-stage (B-ST_n) according to the ninth embodiment includes a set switching element STr, a reset switching element RTr, a B-scan output switching element (B-SCO), a first B-control switching element B-Ctr1, a second B-control switching element B-Ctr2 and a capacitor C.

Here, the set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO in the ninth embodiment are the same as those in Fig. 6 described above, respectively, Refer to the contents of FIG.

The detergent 1 B-control switching element B-Ctr1, the second B-control switching element B-Ctr2, and the capacitor C in the ninth embodiment are the same as those in Fig. And therefore, the description thereof is the same as that of FIG. 26 (b).

In the ninth embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT are connected to each other. The A-scan pulse A- - The scan pulse B-SC_n constitutes one composite pulse Vg_n.

In the ninth embodiment, the A-scan output terminal A-SOT and the B-scan output terminal B-SOT may be separated from each other.

The 10th of the A-stage and B-stage Example

54 is a diagram showing a tenth embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The n-th A-stage A-ST_n according to the tenth embodiment includes the A-inverting unit A-INV, the first to fourth A-switching devices A-Tr1 to A- (A-CRO), an A-scan output switching device (A-SCO), an A-scan discharge switching device (A- SCD), an A2-scan output switching device (A2-SCO), and an A2-scan discharge switching device (A2-SCD).

The A-inverting unit A-INV, the first A-switching unit A-Tr1, the second A-switching unit A-Tr2, the A- -CRO) and the A-carry discharge switching element A-CRD are the same as those in Fig. 33, respectively, and therefore, the description thereof is made with reference to the contents of Fig.

The A1-scan output switching device A1-SCO and the A1-scan discharge switching device A1-SCD in the tenth embodiment are respectively connected to the A-scan output switching device A-SCO in FIG. 33, And the A-scan discharge switching element (A-SCD), respectively.

The third A-switching element A-Tr3, the fourth A-switching element A-Tr4 and the F-clock pulse F-CLK in the tenth embodiment are the same as those in the above- And therefore the description thereof is made with reference to the contents of FIG.

The A1-set node A1-Q, the A1-scan output terminal A1-SOT, the A1-scan pulse A1-SC_n and the second A1-clock pulse A1-CLK_2 in the tenth embodiment, Scan pulse A-SC_n and the second A-clock pulse A-CLK_2 in FIG. 33, respectively, in the same manner as the A-set node AQ, the A-scan output terminal A- Do.

The n-th B-stage B-ST_n according to the tenth embodiment includes B1-set switching element B1-STr, B1-reset switching element B1-RTr, , A B1-SCO output switching element B1-SCO, a B2-set switching element B2-STr, a B2-reset switching element B2-RTr and a B2-scan output switching element B2-SCO .

The B1-set switching element B1-STr, the B1-reset switching element B1-RTr and the B1-scan output switching element B1-SCO in the tenth embodiment are the same as those in FIG. Set switching element STr, the reset switching element RTr and the B-scan output switching element B-SCO, and therefore, the description thereof is made with reference to FIG.

The B1-set node B1-Q, B1-scan output terminal B1-SOT, B1-scan pulse B1-SC_n and B1-clock pulse B1-CLK in the tenth embodiment are Is the same as the B-set node BQ, the B-scan output terminal B-SOT, the B-scan pulse B-SC_n and the B-clock pulse B-CLK in FIG.

The B2-set switching element (B2-STr) and the B2-reset switching element (B2-RTr) in the tenth embodiment are similar to the B1-set switching element (B1-STr) and the B1- (B1-RTr), but differ only in that they are connected to the B2-set node (B2-Q).

Similarly, the B2-scan output switching element B2-SCO in the tenth embodiment is substantially the same as the B1-scan output switching element B1-SCO described above, and only when it is the B2-set node B2- And a B2-clock transmission line and a B2-scan output terminal (B2-SOT) for transmitting a B2-clock pulse (B2-CLK).

Here, the B2-clock pulse B2-CLK may be another kind of clock pulse having the same or different phase as the B1-clock pulse B1-CLK.

In the tenth embodiment, the A1-scan output terminal A1-SOT and the B1-scan output terminal B1-SOT are connected to each other. The A1-scan pulse A1-SC_n and the B1- - The scan pulses B1-SC_n are output as one composite pulse Vg1_n.

According to the tenth embodiment, the A2-scan output terminal A2-SOT and the B2-scan output terminal B2-SOT are connected to each other. The A2-scan pulse A2- And the B2-scan pulse B2-SC_n are output as one composite pulse Vg2_n.

In the tenth embodiment, the A1-scan output terminal A1-SOT and the B1-scan output terminal B1-SOT may be separated from each other.

Also, in the tenth embodiment, a structure in which the A2-scan output terminal (A2-SOT) and the B2-scan output terminal (B2-SOT) are separated from each other is also possible.

The A-stage and the 11th stage of the B- Example

55 is a diagram showing an eleventh embodiment of the circuit configuration of the n-th A-stage and the n-th B-stage.

The nth A-stage A-ST_n according to the eleventh embodiment includes the A-inverting unit A-INV, the first to fourth A-switching devices A-Tr1 to A- (A-CRO), an A-scan output switching device (A-SCO), an A-scan discharge switching device (A- SCD), an A2-scan output switching device (A2-SCO), and an A2-scan discharge switching device (A2-SCD).

The structure according to the eleventh embodiment is substantially the same as the structure in Fig. 54, except that the B1-scan output switching element B1-SCO and the B2-scan output switching element B2-SCO in Fig. - set node (BQ). 55, one set switching element STr and one reset switching element RTr are provided to control the B-set node B-Q.

56 is a diagram showing another embodiment of the n-th A-stage.

As shown in FIG. 56, the n-th A-stage A-ST_n includes a first A-switching element A-Tr1, a second A-switching element A- The switching element A-Tr3-1, the third A-switching element A-Tr3-2, the fourth A-switching element A-Tr4, the first A- The first A-inverted portion A-INV2, the A-carry output switching element A-CRO, the first A-carry discharge switching element A-CRD1 and the second A-carry discharge switching element A1- ).

The first A-switching element A-Tr1 and the second A-switching element A-Tr2 provided in the n-th A-stage A-ST_n are the same as those in FIG. 33 described above For a description of these, refer to the contents related to FIG.

The 3-1A-switching element A-Tr3-1 and the 3-2A-switching element A-Tr3-2 provided in the n-th A-stage A- Switching element (A-Tr3) in FIG. 45, and therefore, the description related to these is the same as that of FIG.

The fourth A-switching element A-Tr4 and the F-clock pulse F-CLK provided in the n-th A-stage A-ST_n are the same as those in Fig. 45 described above, See the description related to FIG. 45 for the explanation.

The first A-INV1 included in the n-th A-stage A-ST_n is connected to the logic of the voltage of the A-set node AQ and the logic of the voltage of the first A- The voltage of the first A-reset node A-QB1 is controlled in accordance with the voltage of the A-set node AQ so that the logic of the voltage is opposite. Specifically, the first A-inverting portion A-INV1 is configured to output the low voltage VL to the first A-reset node A-QB1 when the voltage of the A-set node AQ is logically high, And discharges the first A-reset node A-QB1. The first A-inverting unit A-INV1 is connected to the first A-resetting node A-QB1 when the voltage of the A-set node AQ is logically low, And the voltage AC1 is applied.

The second A-INV2 included in the n-th A-stage A-ST_n is connected to the logic of the voltage of the A-set node AQ and the logic of the voltage of the second A- And controls the voltage of the second A-reset node A-QB2 according to the voltage of the A-set node AQ so that the logic of the voltage is opposite. Specifically, the second A-INV2 is connected to the second A-reset node A-QB2 at a low voltage VL when the voltage of the A-set node AQ is logically high, And discharges this second A-reset node A-QB2. On the other hand, the second A-INV2 is connected to the second A-reset node A-QB2 when the voltage of the A-set node AQ is logically low, (AC2).

The first alternating-current voltage AC1 and the second alternating-current voltage AC2 are AC signals having alternating high voltage VH and low voltage VL in units of h frames (h is a natural number). The first AC type voltage AC1 is a signal which is inverted by 180 degrees with respect to the second AC type voltage AC2. Therefore, when the first alternating-current voltage AC1 is maintained at the high voltage VH for a certain frame period, then the second alternating-current voltage AC2 is maintained at the low voltage VL.

the A-carry output switching element A-CRO provided in the n-th A-stage A-ST_n is controlled according to the voltage of the A-set node AQ, and the second A- And an A-COT output terminal (A-COT).

The first A-carry discharge switching element A-CRD1 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the first A-reset node A-QB1, and the A- And is connected between a third discharge power supply line for transferring the terminal A-COT and the third discharge voltage VSS3.

The second A-carry discharge switching element A-CRD2 provided in the n-th A-stage A-ST_n is controlled according to the voltage of the second A-reset node A-QB2, and the A- Is connected between the terminal (A-COT) and the third discharge power supply line.

The discharge voltages and the enable signal EN in the above-described FIG. 45 to FIG. 56 may have a relation as shown in the following Equation 1.

[Equation 1]

VSS2 VSS3 = VSS1 VSS4 = VSS = L_EN

In Equation (1), L_EN denotes a low voltage of the enable signal EN.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

A-CLK: A- Clock pulse EN: Enable signal
B-CLK: B-clock pulse A-ST_ #: #th A-stage
B-ST_ #: #th B-stage A-OT: A- output terminal
B-OT: B- output terminal A-OUT_ #: #th A-output pulse
B-OUT_ #: #th B-output pulse

Claims (58)

A plurality of A-stages for receiving at least one of a plurality of A-clock pulses and outputting at least one A-carry pulse and at least one A-scan pulse; And
At least one of the A-carry pulses from at least one of the A-stages, the enable signal from the outside, and at least one of a plurality of B-clock pulses and outputs at least one B- And a single B-stage. The method according to claim 1,
The plurality of A-stages sequentially outputs a plurality of A-scan pulses and a plurality of A-carry pulses for every A-output period of each frame period; And,
And the B-scan pulse of the at least one B-stage is output in a B-output period of a specific frame period. The method according to claim 1,
The A-stages each include an A-carry output terminal and at least one A-scan output terminal;
The at least one B-stage comprises at least one B-scan output terminal;
Each of the A-stages outputs an A-carry pulse through its A-carry output terminal and an A-scan pulse through an A-scan output terminal;
The B-stage outputs a B-scan pulse through a B-scan output terminal;
Wherein the A-scan output terminal and the B-scan output terminal are the same or different. The method of claim 3,
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal; And
And a B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node. 5. The method of claim 4,
The n-th B-
stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, Further comprising a switching element. 5. The method of claim 4,
The n-th B-
And a reset switching element connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A shift register. 5. The method of claim 4,
The n-th B-
stage between the B-set node and the enable line or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A connected first reset switching element; And
A second reset connected between the B-set node and an enable line, or between a second discharge power supply line for transmitting a second discharge voltage source to the B-set node, Further comprising a switching element. 5. The method of claim 4,
The n-th B-
And a B-capacitor connected between the B-set node and the B-scan output terminal. The method of claim 3,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A switching element;
A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; And
And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B-set node. The method of claim 3,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
A reset switching element connected between the B-set node and an enable line, or between a B-set node and a discharge power supply line for transmitting a discharge voltage source, the reset switching element being controlled according to a control signal from the outside;
A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; And
And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B-set node. The method of claim 3,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage between the B-set node and the enable line, or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A first reset switching element connected to the second node;
A second reset connected between the B-set node and an enable line, or between a second discharge power supply line for transmitting a second discharge voltage source to the B-set node, A switching element;
A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal; And
And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B-set node. The method of claim 3,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled in accordance with an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and an B1-set node for transmitting an enable signal;
stage, and between the B1-set node and the enable line, or between the B1-set node and the first discharge power supply line for transmitting the first discharge voltage source A first B1-reset switching element connected thereto;
A B1-scan output switching element connected between the B1-clock transmission line for transmitting the B1-clock pulse and the B1-scan output terminal, the B1-scan output switching element being controlled according to the voltage of the B1-set node;
A B-control switching element controlled in accordance with the voltage of the B1-set node and connected between the B1-set node and the B2-set node;
stage between the B2-set node and the enable line, or between the B2-set node and the second discharge power supply line for transferring the second discharge voltage A first B2-reset switching element connected thereto; And
And a B2-scan output switching element connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal, the B2-scan output switching element being controlled according to the voltage of the B2-set node. 13. The method of claim 12,
A second B1-reset switching element controlled in accordance with a control signal from the outside, and connected between the B1-set node and an enable line, or between the B1-set node and a first discharge power supply line; And
And at least one of the second B2-reset switching elements connected between the B2-set node and the enable line or between the B2-set node and the second discharge power supply line is controlled according to a control signal from the outside The shift register further comprising: The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A switching element;
A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And
And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-carry output terminal and the B-scan output terminal. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
A reset switching element connected between the B-set node and an enable line, or between a B-set node and a discharge power supply line for transmitting a discharge voltage source, the reset switching element being controlled according to a control signal from the outside;
A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And
And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-carry output terminal and the B-scan output terminal. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage, and is connected between the B-set node and the enable line, or between the B-set node and the discharge power supply line for transferring the discharge voltage source to the first A reset switching element;
A second reset switching element connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, the second reset switching element being controlled according to a control signal from the outside;
A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And
And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-carry output terminal and the B-scan output terminal. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage, a reset connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, A switching element;
A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And
And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-clock transmission line and the B-carry output terminal. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
A reset switching element connected between the B-set node and an enable line, or between a B-set node and a discharge power supply line for transmitting a discharge voltage source, the reset switching element being controlled according to a control signal from the outside;
A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And
And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-clock transmission line and the B-carry output terminal. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage, and is connected between the B-set node and the enable line, or between the B-set node and the discharge power supply line for transferring the discharge voltage source to the first A reset switching element;
A second reset switching element connected between the B-set node and the enable line, or between the B-set node and a discharge power supply line for transmitting a discharge voltage source, the second reset switching element being controlled according to a control signal from the outside;
A B-scan output switching element connected between a B-clock transmission line for transmitting a B-clock pulse and a B-scan output terminal, the B-scan output switching element being controlled according to the voltage of the B-set node; And
And a B-carry output switching element controlled in accordance with the voltage of the B-set node and connected between the B-clock transmission line and the B-carry output terminal. 20. The method according to any one of claims 14 to 19,
The n-th B-stage is controlled in accordance with the voltage of the B-reset node, and further includes a B-carry discharge switching element connected between the B-carry output terminal and a discharge power supply line for transmitting a discharge voltage ;
Wherein the B-reset node is supplied with either the A-clock pulse, the A-carry pulse, the start pulse, or the voltage of the A-stage reset node. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage between the B-set node and the enable line or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A connected reset switching element;
A B-carry output switching element connected between the B1-clock transmission line and the B-carry output terminal for transmitting the B1-clock pulse, the B-carry output switching element being controlled according to the voltage of the B-set node;
A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal;
A B2-scan output switching element controlled in accordance with the voltage of the B-set node and connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal;
And a B-carry discharge switching element connected between the B-carry output terminal and a second discharge power supply line for transmitting a second discharge voltage, the B-carry discharge switching element being controlled according to the voltage of the B-reset node;
Wherein the B-reset node is supplied with either the A-clock pulse, the A-carry pulse, the start pulse, or the voltage of the A-stage reset node. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
A reset switching element connected between the B-set node and the enable line or between the B-set node and a first discharge power supply line for transmitting a first discharge voltage source, ;
A B-carry output switching element connected between the B1-clock transmission line and the B-carry output terminal for transmitting the B1-clock pulse, the B-carry output switching element being controlled according to the voltage of the B-set node;
A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal;
A B2-scan output switching element controlled in accordance with the voltage of the B-set node and connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal;
And a B-carry discharge switching element connected between the B-carry output terminal and a second discharge power supply line for transmitting a second discharge voltage, the B-carry discharge switching element being controlled according to the voltage of the B-reset node;
Wherein the B-reset node is supplied with either the A-clock pulse, the A-carry pulse, the start pulse, or the voltage of the A-stage reset node. The method of claim 3,
Wherein the at least one B-stage further comprises at least one B-carry output terminal;
The B-stage further outputs a B-carry pulse via a B-carry output terminal;
The number of A-stages and the number of B-stages are the same;
Wherein the at least one B-scan output terminal comprises a B1-scan output terminal and a B2-scan output terminal;
The plurality of B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The n-th B-stage (n is a natural number)
a set switching element controlled according to an A-carry pulse from an (n + x) th A-stage (x is a natural number) and connected to an enable line and a B-set node for transmitting an enable signal;
stage between the B-set node and the enable line or between the B-set node and the first discharge power supply line for transmitting the first discharge voltage source A connected first reset switching element;
A second reset connected between the B-set node and an enable line, or between a second discharge power supply line for transmitting a second discharge voltage source to the B-set node, A switching element;
A B-carry output switching element connected between the B1-clock transmission line and the B-carry output terminal for transmitting the B1-clock pulse, the B-carry output switching element being controlled according to the voltage of the B-set node;
A B1-scan output switching element controlled in accordance with the voltage of the B-set node, the B1-scan output switching element being connected between the B1-clock transmission line transmitting the B1-clock pulse and the B1-scan output terminal;
A B2-scan output switching element controlled in accordance with the voltage of the B-set node and connected between a B2-clock transmission line for transmitting a B2-clock pulse and a B2-scan output terminal;
And a B-carry discharge switching element connected between the B-carry output terminal and a third discharge power supply line for transmitting a third discharge voltage, the B-carry discharge switching element being controlled according to the voltage of the B-reset node;
Wherein the B-reset node is supplied with either the A-clock pulse, the A-carry pulse, the start pulse, or the voltage of the A-stage reset node. 5. The method of claim 4,
The n-th B-
A first B-control switching element controlled in accordance with a B-clock pulse or an F-clock pulse, and connected between the B-set node and the B-scan output terminal;
Wherein the F-clock pulse is equal to or different from the A-clock pulse. 5. The method of claim 4,
The n-th B-
A capacitor to which a B-clock pulse or a G-clock pulse is supplied to one terminal;
A first B-control switching element controlled in accordance with a voltage of the B-set node, the first B-control switching element being connected between the other terminal of the capacitor and a discharge power supply line for transmitting a discharge voltage;
And a second B-control switching element connected between the B-set node and the B-scan output terminal, the second B-control switching element being controlled according to a voltage applied to the other terminal of the capacitor;
Wherein a rising edge of the B-clock pulse is included within the pulse width of the G-clock pulse. The method of claim 3,
The n-th A-stage (n is a natural number) is determined according to at least one of the A-carry pulse from the npth A-stage and the A-carry pulse from the n + And a node control section for controlling the voltage of the set node or the voltage of the A1-set node and the A-reset node;
Wherein the nth A-stage comprises only one of an A-set node and an A1-set node. 27. The method of claim 26,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one A-scan output terminal comprises an A1-scan output terminal and an A2-scan output terminal;
The plurality of A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses;
The n-th A-
An A-carry output switching element controlled in accordance with the voltage of the A-set node and connected between the A1-clock transmission line for transmitting the A1-clock pulse and the A-carry output terminal;
An A1-scan output switching device controlled in accordance with the voltage of the A-set node and connected between the A1-clock transmission line and the A1-scan output terminal;
An A2-scan output switching element connected between the A2-clock transmission line and the A2-scan output terminal for transmitting the A2-clock pulse, the A2-scan output switching element being controlled according to the voltage of the A-set node; And
And an A-carry discharge switching element connected between the A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to the voltage of the A-reset node. 27. The method of claim 26,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one A-scan output terminal comprises an A1-scan output terminal and an A2-scan output terminal;
The plurality of A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses;
The n-th A-
An A-carry output switching element controlled in accordance with the voltage of the A1-set node and connected between the A1-clock transmission line for transmitting the A1-clock pulse and the A-carry output terminal;
An A1-scan output switching element controlled in accordance with the voltage of the A1-set node and connected between the A1-clock transmission line and the A1-scan output terminal;
An A-control switching element controlled in accordance with the voltage of the A1-set node, the A-control switching element being connected between the A1-set node and the A2-set node;
An A2-scan output switching element connected between the A2-clock transmission line and the A2-scan output terminal for transmitting the A2-clock pulse, the A2-scan output switching element being controlled according to the voltage of the A2-set node; And
And an A-carry discharge switching element connected between an A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to a voltage of the A-reset node. . 27. The method of claim 26,
The number of A-stages and the number of B-stages are the same;
Wherein the at least one A-scan output terminal comprises an A1-scan output terminal and an A2-scan output terminal;
The plurality of A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses;
The n-th A-
An A-carry output switching element controlled in accordance with the voltage of the A1-set node and connected between the A1-clock transmission line for transmitting the A1-clock pulse and the A-carry output terminal;
An A1-scan output switching element controlled in accordance with the voltage of the A1-set node and connected between the A1-clock transmission line and the A1-scan output terminal;
An A-control switching element controlled in accordance with the voltage of the A-carry output terminal and connected between the A-carry output terminal and the A2-set node;
An A2-scan output switching element connected between the A2-clock transmission line and the A2-scan output terminal for transmitting the A2-clock pulse, the A2-scan output switching element being controlled according to the voltage of the A2-set node; And
And an A-carry discharge switching element connected between an A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to a voltage of the A-reset node. . 28. The method according to any one of claims 27 to 29,
The n-th A-
An A1-scan discharge switching element controlled in accordance with a voltage of the A-reset node and connected between the A1-scan output terminal and the discharge power supply line; And
And at least one of A2-scan discharge switching elements controlled in accordance with the voltage of the A-reset node and connected between the A2-scan output terminal and the discharge power supply line. 28. The method according to any one of claims 27 to 29,
The n-th A-
A first A-control switching element connected between the A-reset node and a discharge power supply line for transmitting a discharge voltage, the first A-control switching element being controlled according to any one of the A1-scan pulse and the A2-scan pulse; And
And a second A-control switching element controlled in accordance with the B-clock pulse and connected between the A1-set node and the A2-set node and the discharge power supply line. Shift register. 30. The method according to any one of claims 27 to 29,
The n-th A-
And a third A-control switching element controlled between the A1-set node and the A2-set node and connected between a discharge power supply line for transmitting a discharge voltage, ; And
And a fourth A-control switching element controlled in accordance with a B-carry pulse from the B-stage and connected between the A-reset node and a discharge power supply line. . 27. The method of claim 26,
The n-th stage A-
(n-1) -th stage (n is a natural number smaller than n) A-stage, and between the charging power supply line and the A-set node for transmitting the charging voltage, or between the charging power supply line and the A1- A first A-switching element connected between the set nodes;
(n + q) th (where q is a natural number) A-stage, and between the A-set node and a discharge power supply line for transmitting a discharge voltage, or between the A1- A second A-switching element connected between the dedicated power supply lines; And
And an A-inverting unit for controlling the voltage of the A-reset node according to the voltage of the A-set node or the A1-set node. 34. The method of claim 33,
The A-
A first A-inversion switching element, controlled in accordance with a high voltage from a high power line, connected between the high power line and the A-reset node; And
And a second A-inversion switching element connected between the A-reset node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A- register. 34. The method of claim 33,
The A-
A first A-inverting switching element connected between the high power line for transmitting a high voltage and the A-reset node, the first A-inverting switching element being controlled according to a control signal from the outside; And
And a second A-inversion switching element connected between the A-reset node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A- register. 34. The method of claim 33,
The A-
A first A-inverting switching element connected between a high power line for transmitting a high voltage and an A-common node, the first A-inverting switching element being controlled in accordance with a control signal from the outside;
A second A-inversion switching element connected between the A-common node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node;
A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And
And a fourth A-inverted switching element controlled in accordance with the voltage of the A-set node or the A1-set node and connected between the A-reset node and the low power supply line. 34. The method of claim 33,
The A-
A first A-inversion switching element controlled in accordance with a high voltage from a high power line and connected between the high power line and the A-common node;
A second A-inversion switching element connected between the A-common node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node;
A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And
And a fourth A-inverted switching element controlled in accordance with the voltage of the A-set node or the A1-set node and connected between the A-reset node and the low power supply line. 34. The method of claim 33,
The A-
A first A-inversion switching element controlled in accordance with a high voltage from a high power line and connected between the high power line and the A-common node;
A second A-inverting switching element connected between the A-common node and a low power line for transmitting a low voltage, the second A-inverting switching element being controlled according to the voltage of the A1-scan output terminal or the A2-scan output terminal;
A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And
And a fourth A-inverted switching element controlled in accordance with the voltage of the A-set node or the A1-reset node and connected between the A-reset node and the low power supply line. 34. The method of claim 33,
The A-
A first A-inversion switching element connected between the A-set node and a low power supply line for transmitting a low voltage, the first A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node;
Set node and the A-set node and between the A-set node and the A-scan output terminal, or between the A-set node and the A- Connected between the A1-set node and the A1-scan output terminal, or between the A1-set node and the A2-scan output terminal, or between the A1-set node and the A- A-inverting switching device; And
And an A-capacitor connected between the A-reset transmission node and the A-clock transmission line for transmitting any one of the A-clock pulses. 34. The method of claim 33,
The A-
A first A-inverting switching element connected between an A-reset node and a high power line for transmitting a high voltage, the A-inverting switching element being controlled according to any one of the A-clock pulses;
A second A-inversion switching element connected between the A-set node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node; And
And a third A-inverted switching element coupled between the A-reset node and the low power supply line, the third A-inverted switching element being controlled according to another A-clock pulse. 34. The method of claim 33,
The A-
A first A-inverting switching element controlled in accordance with any one of the A-clock pulses and connected between the A-clock transmission line to which the A-clock pulse is transmitted and the A-resetting node;
A second A-inversion switching element connected between the A-set node and a low power supply line for transmitting a low voltage, the second A-inversion switching element being controlled according to the voltage of the A-set node or the A1-set node; And
And a third A-inverted switching element coupled between the A-reset node and the low power supply line, the third A-inverted switching element being controlled according to another A-clock pulse. 34. The method of claim 33,
The A-
A first A-inverting switching element connected between the high-power line transmitting the high voltage and the A-common node, the first A-inverting switching element being controlled according to any one of the A-clock pulses;
A second A-inverting switching element connected between the A-common node and a low power supply line for transmitting a low voltage, the second A-inverting switching element being controlled according to another A-clock pulse;
A third A-inversion switching element controlled in accordance with the voltage of the A-common node and connected between the high power line and the A-reset node; And
And a fourth A-inverted switching element controlled in accordance with the voltage of the A-set node or the A1-set node and connected between the A-reset node and the low power supply line. 43. The method according to any one of claims 34 to 42,
The A-
a fifth A-inversion switching element controlled in accordance with the A-carry pulse from the npth A-stage and connected between the A-reset node and the low power supply line;
Stage node and between the A-set node and the discharge power supply line, or between the A-set node and the A1-scan output terminal of any one of the A-stages, or between the A- Between the set node and the A2-scan output terminal of any one of the A-stages, or between the A-set node and the carry output terminal of any one of the A-stages, or between the A1- Or between the A1-set node and the A1-scan output terminal of any one of the A-stages, or between the A1-set node and the A2-scan output terminal of any one of the A-stages or between the A1- A sixth A-inverting switching element connected between the carry output terminals of any one of the A-stages;
The A-set node is controlled by the voltage of the A-reset node and between the A-set node and the A-clock transmission line transmitting any one A-clock pulse, or between the A- A seventh A-inverting switching element connected between the A-clock transmission line for transmitting the A-clock transmission line;
Stage output terminal and the A-set node, or between the A2-scan output terminal of the npth A-stage and the A-set node, and the A- Or an 8th A-inverting switching element connected between the A1-scan output terminal and the A1-set node of the npth A-stage or between the A2- scan output terminal of the npth A-stage and the A1-set node; And
And a ninth A-inversion switching element connected between the A-reset node and the low power supply line, the at least one of which is controlled according to a scan pulse from any one of the A-stages. . 37. The method according to any one of claims 36 to 37,
The A-
And a tenth A-inversion switching element controlled in accordance with a scan pulse from any one of the A-stages and connected between the A-common node and the low power supply line. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
Stage, the A-scan pulse output from the A-scan output terminal is controlled by the A-scan pulse from the A-scan output terminal of the n-th A-stage, Further comprising an A-switching device. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
Stage, the A-scan pulse output from the A-scan output terminal is controlled by the A-scan pulse from the A-scan output terminal of the n-th A-stage, A-switching device; And
And a fourth A-switching element connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, the fourth A-switching element being controlled according to a B-clock pulse or an F- . 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharging power supply line connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third discharging voltage being controlled in accordance with a B-carry pulse from the B- A-switching device; And
And a fourth A-switching element connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, the fourth A-switching element being controlled according to an F-clock pulse;
And a B-carry pulse from the B-stage is generated based on a B-clock pulse. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharging power supply line connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third discharging voltage being controlled in accordance with a B-carry pulse from the B- A-switching device; And
And a fourth A-switching element connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, the fourth A-switching element being controlled according to an F-clock pulse;
And a B-carry pulse from the B-stage is generated based on an F-clock pulse. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharging power supply line connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third discharging voltage being controlled in accordance with a B-carry pulse from the B- A-switching device; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, - further comprising a switching element;
And a B-carry pulse from the B-stage is generated based on an F-clock pulse. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharging power supply line connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third discharging voltage being controlled in accordance with a B-carry pulse from the B- A-switching device; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, - further comprising a switching element;
And a B-carry pulse from the B-stage is generated based on a B-scan pulse from the B-stage. 50. The method according to any one of claims 47 to 50,
The n-th A-
And a fifth A-switching element controlled by the voltage of the A-reset node and connected between the second discharge power supply line and the B-carry output terminal. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
Stage, the A-scan pulse output from the A-scan output terminal is controlled by the A-scan pulse from the A-scan output terminal of the n-th A-stage, A-switching device; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, - further comprising a switching element;
The n-th B-
And a first B-switching element connected between the B-scan output terminal of the n-th B-stage and the B-set node of the n-th B-stage, Shift register. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
A third A-switching element connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third A-switching element being controlled according to a B-clock pulse; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, - further comprising a switching element;
The n-th B-
And a first B-switching element connected between the B-scan output terminal of the n-th B-stage and the B-set node of the n-th B-stage, Shift register. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
Stage, the A-scan pulse output from the A-scan output terminal is controlled by the A-scan pulse from the A-scan output terminal of the n-th A-stage, A-switching device; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, - further comprising a switching element;
The n-th B-
A capacitor to which a B-clock pulse or a G-clock pulse is supplied to one terminal;
A first B-control switching element controlled in accordance with a voltage of the B-set node, the first B-control switching element being connected between the other terminal of the capacitor and a discharge power supply line for transmitting a discharge voltage;
And a second B-control switching element connected between the B-set node and the B-scan output terminal, the second B-control switching element being controlled according to a voltage applied to the other terminal of the capacitor;
Wherein a rising edge of the B-clock pulse is included within the pulse width of the G-clock pulse. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal, an A1-scan output terminal and an A2-scan output terminal;
The nth B-stage includes a B1-set node, a B2-set node, a B1-scan output terminal and a B2-scan output terminal;
The A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses;
B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The A1-scan output terminal of the n-th A-stage is connected to the B1-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The A2-scan output terminal of the n-th A-stage is connected to the B2-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharging power supply line connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third discharging power supply line being controlled in accordance with an A1-scan pulse from the A1- A-switching device; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, And a switching element. 34. The method of claim 33,
Stage comprises an A-set node, an A-reset node, an A-carry output terminal, an A1-scan output terminal and an A2-scan output terminal;
stage, the n-th B-stage includes a B-set node, a B1-scan output terminal and a B2-scan output terminal;
The A-clock pulses are divided into a plurality of A1-clock pulses having a phase difference and a plurality of A2-clock pulses;
B-clock pulses are divided into a plurality of B1-clock pulses having a phase difference and a plurality of B2-clock pulses;
The A1-scan output terminal of the n-th A-stage is connected to the B1-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The A2-scan output terminal of the n-th A-stage is connected to the B2-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharging power supply line connected between the A-reset node and a second discharging power supply line for transmitting a second discharging voltage, the third discharging power supply line being controlled in accordance with an A1-scan pulse from the A1- A-switching device; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, And a switching element. 34. The method of claim 33,
Stage comprises an A-set node, an A1-reset node, an A2-reset node, an A-carry output terminal and an A-scan output terminal;
The A-scan output terminal of the n-th A-stage is connected to the B-scan output terminal of the n-th B-stage corresponding to the n-th A-stage;
The n-th stage A-
And a third discharge power supply line connected between the A1-reset node and a second discharge power supply line for transferring a second discharge voltage, the third discharge power supply line being controlled in accordance with a B-carry pulse from the B- A1-switching element;
A third A2-switching device controlled in accordance with a B-carry pulse from the B-carry output terminal of the n-th B-stage and connected between the A2-reset node and a second discharge power supply line; And
Stage B-stage and a B-carry pulse from the B-carry output terminal of the n-th B-stage, and is connected between the A-set node and a first discharging power supply line for transmitting a first discharging voltage, - further comprising a switching element;
And a B-carry pulse from the B-stage is generated based on a B-scan pulse from the B-stage. 27. The method of claim 26,
Wherein the at least one A-scan output terminal comprises an A1-scan output terminal;
The plurality of A-clock pulses comprising a plurality of A1-clock pulses having a phase difference;
The n-th A-
An A-carry output switching element controlled in accordance with the voltage of the A-set node and connected between the A1-clock transmission line for transmitting the A1-clock pulse and the A-carry output terminal;
An A1-scan output switching device controlled in accordance with the voltage of the A-set node and connected between the A1-clock transmission line and the A1-scan output terminal;
And an A-carry discharge switching element connected between the A-carry output terminal and a discharge power supply line for transmitting a discharge voltage, the A-carry discharge switching element being controlled according to the voltage of the A-reset node.

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