KR20150008913A - Tiled x-ray imager panel and method of forming the same - Google Patents

Abstract

A tile type imager panel is disclosed. In certain embodiments, the tiled imager panels are formed of separate imager chips that are mechanically tiled together to minimize gaps between the tile-shaped imager chips. Additionally, in certain embodiments, the scintillator material associated with the tile type imager panel is in an enclosed sealed environment to protect it from moisture.

Description

[0001] TILED X-RAY IMAGE PANEL AND METHOD OF FORMING THE SAME [0002]

Non-invasive imaging techniques allow an image of the internal structure of a subject (e.g., a patient or an object) to be obtained without performing an invasive procedure on the patient or object. Non-invasive imaging systems can operate based on the transmission and detection of radiation through a subject subject (e.g., a patient or article of manufacture) or from a subject subject. For example, x-ray based imaging techniques (e.g., mammography, fluoroscopy, computed tomography (CT), etc.) are typically performed using an external X-ray radiation source And a detector located on the opposite side of the X-ray source for detecting X-rays transmitted through the subject. Other radiation-based imaging approaches, such as single photon emission computed tomography (SPECT) or positron emission tomography (PET), may use radiopharmaceuticals that are administered to a patient and cause the emission of gamma radiation from a location within the patient's body. The emitted gamma ray is then detected and the gamma ray emission is localized.

Thus, in such a radiation based imaging approach, the radiation detector is an integral part of the imaging process and enables the acquisition of data used to generate the target image. In certain radiation detection schemes, the radiation can be detected using a scintillating material that converts higher energy gamma or X-ray radiation to optical photons (e.g., visible light), and the photons May then be detected by a photodetector device such as a photodiode. However, scintillator materials are easily degraded when exposed to moisture or other environmental conditions.

Such scintillator degeneration can be a problem in situations where flat panel detectors are used, such as in general X-ray imaging applications and C-arm applications. In particular, it is necessary to combine several small panels to form the desired larger panel assembly in order to construct a plate of the desired size. However, such an assembly is susceptible to attack by moisture or other environmental elements. As a result, large panel assemblies formed using small imager panels can ultimately reduce efficiency as moisture or other environmental elements are infiltrated into large assemblies.

According to one embodiment, a method of manufacturing a tiled detector panel is provided. The method includes placing the imager chip face-down on a tiled array. On the backside of the imager chip, epoxy is applied along the periphery and internal seam of the tile array of imager chips. The substrate is applied to the epoxy on the backside of the imager chip. The epoxy ring is applied to the front side of the imager chip. A scintillator material is applied to the front side of the imager chip. A face plate is applied to the rings of the epoxy to form a sealed environment containing the scintillator material.

According to a further embodiment, a method of manufacturing a tiled detector panel is provided. The method includes placing the imager chips face-up in a tiled array. Epoxy is applied to the substrate at a location corresponding to the surrounding and internal bonding lines associated with the tile array of imager chips. The tile-like arrangement of the imager chips is applied to the epoxy on the substrate so that the peripheral and internal bond lines of the tile-like arrangement of imager chips are placed on the epoxy. The epoxy ring is applied to the front side of the imager chip. A scintillator material is applied to the front side of the imager chip. A face plate is applied to the ring of the epoxy to form a sealing environment containing the scintillator material.

According to another embodiment, a detector panel is provided. The detector panel includes a tiled array of imager chips, and the imager chip includes a front side and a back side. The detector panel is disposed on the back side of the tile array of imager chips at the junction between the imager chips; At least partially on the backside of the imager chip along the periphery of the tiled array of imager chips; And an epoxy applied to the front side of the imager chip in a ring around the perimeter of the tiled array of imager chips. The detector panel includes a substrate attached to a tiled array of imager chips by an epoxy applied to the backside of the imager chip and a faceplate attached to the tile array of imager chips by a ring of epoxy applied to the front side of the imager chip Also included. Epoxy and imager chips applied to the face plate, ring of epoxy, and bond line form a sealed environment. The detector panel also includes a scintillator material deposited on the front side of the imager chip in a sealed environment.

These and other features, aspects and advantages will be better understood by reading the following detailed description with reference to the accompanying drawings. Like reference numerals in the drawings denote like parts throughout the drawings.
1 is a block diagram illustrating an embodiment of a general imaging system including a focus grid, in accordance with an aspect of the present invention.
2 is a block diagram illustrating an embodiment of an X-ray imaging system including a focus grid, in accordance with an aspect of the present invention.
3 is a process flow diagram illustrating a process of forming a chip and a substrate assembly, in accordance with an aspect of the present invention.
4 is a view of a set of imager chips tiled down the front side, according to one aspect of the present invention.
Figure 5 is a view of the tile-type imager chip of Figure 4 after application of epoxy, in accordance with an aspect of the present invention.
Figure 6 is a view of the tile-shaped imager chip and epoxy of Figure 5 after application of a support plate, in accordance with an aspect of the present invention.
Figure 7 is a view of the mechanically tiled imager panel of Figure 6 after being inverted, in accordance with an aspect of the present invention.
8 is a process flow diagram illustrating a process of forming a chip and a substrate assembly, according to another aspect of the present invention.
Figure 9 is a view of a set of imager chips tiled with the front side facing up, according to one aspect of the present invention.
10 is a view showing a support plate to which an epoxy is applied, according to an embodiment of the present invention.
11 is a view showing a state in which the tile type imager chip of FIG. 9 is applied to the support plate and epoxy of FIG. 10, according to an embodiment of the present invention.
Figure 12 is a cross-sectional view taken along the view line 12 of Figures 7 and 11, in accordance with an aspect of the present invention.
13 is a process flow chart illustrating a process of forming a detector panel according to an embodiment of the present invention.
14 shows a tile-like chip and a substrate assembly, in accordance with an aspect of the present invention.
15 is a cross-sectional view of an imager chip junction after applying a filler to a gap between imager chips, in accordance with an aspect of the present invention.
16 is a top view of a tile-shaped imager chip assembly with a filler applied to a gap between imager chips, in accordance with an aspect of the present invention.
17 is a view of a tile-shaped imager chip assembly after depositing a scintillator material in a gap between imager chips and applying an epoxy ring, in accordance with an aspect of the present invention.
18 is a cross-sectional view taken along line 18 of FIG. 17, in accordance with an aspect of the present invention.
Figure 19 is a view of the tile-shaped imager chip assembly of Figure 17 after application of a radiation transparent faceplate, in accordance with an aspect of the present invention.
20 is a cross-sectional view of an imager chip junction bridged by a conductive material, in accordance with an aspect of the present invention.
21 shows an embodiment of a tiled detector panel having an electrically bridged scan line according to an aspect of the present invention.
22 shows an embodiment of a tiled detector panel having electrically bridged scan lines and data lines, according to one aspect of the present invention.

The present invention relates to a radiation detector assembly formed using a plurality of small imager panels. In certain embodiments, sealed detector panel assemblies in connection with environmental elements such as moisture and moisture are described with the manufacture of such assemblies. As a result, the detector assemblies described herein are less degraded than other assembled detector panels. In other embodiments, such as when a non-hygroscopic X-ray scintillator is used, the detector panel assembly need not be entirely sealed against environmental elements such as moisture.

It should be noted that the approach of the present invention can be utilized in various imaging situations such as product inspection and security inspection for quality control in medical images in several examples. However, for the sake of simplicity, the examples described herein are generally applicable to medical imaging, particularly conventional radiography, fluoroscopy, mammography, mammography, cirrhosis, single photon emission computed tomography (SPECT) And the like. However, it should be understood that these examples are merely illustrative, and may be described to simplify the description and provide context for the examples described herein. That is, the approach of the present invention may be used in conjunction with any imaging technology described herein, as well as other suitable radiation-based approaches, and in situations other than medical imaging. Specifically, Figures 1 and 2 show a generalized embodiment of a medical imaging system using a radiation detector panel assembly as described herein, wherein Figure 1 shows a general imaging system, Figure 2 shows a radiography, Ray image system or a cigarette image system.

With the foregoing in mind, FIG. 1 is a block diagram illustrating a generalized imaging system 10. The imaging system 10 includes a detector assembly 12 that detects signals 14 such as emitted gamma rays or transmitted X-rays. The detector assembly 12 is comprised of a plurality of small panels and can generate an electrical signal in response to incident radiation to the detector assembly 12. The signal 14 may be generated by a radiation source controlled with the imaging system 10 or may be generated in response to a radioactive decay of the radiopharmaceutical administered to the patient.

The detector assembly 12 generates an electrical signal in response to the detected radiation, which is transmitted to its data acquisition system (DAS) 16 via its respective channel. When the DAS 16 acquires an electrical signal that can be an analog signal, the DAS 16 digitizes or otherwise improves the data for easier processing. For example, the DAS 16 may filter the image data to remove noise or other image aberrations. The DAS 16 then provides data to the controller 20 that is operatively connected. The controller 20 may be a special purpose computer or a general purpose computer with properly configured software. The controller 20 may include computer circuitry configured to execute algorithms such as image protocol, data processing, diagnostic evaluation, and the like. As an example, the controller 20 may instruct the DAS 16 to perform image acquisition at a predetermined time to filter certain types of data, and so on. In addition, the controller 20 may include features for interfacing with an operator, such as an Ethernet connection, an Internet connection, a wireless transceiver, a keyboard, a mouse, a trackball, a display,

Referring to FIG. 2, a block diagram illustrating an X-ray imaging system 30 that may utilize a detector assembly in accordance with the present invention is shown. The X-ray imaging system 30 may be, for example, an inspection system for quality control, package screening and safety screening, or may be a medical imaging system. In the illustrated embodiment, system 30 is an X-ray medical imaging system, such as radiography, or a cigarette imaging system. The configuration of the system 30 may be similar in design from the generalized imaging system 10 described with respect to FIG. For example, the system 30 includes a controller 20 operatively connected to the DAS 16, with which the controlled acquisition of image data through the x-ray detector assembly 12 It is possible.

In system 30, for the collection of image data, the controller 20 may be coupled to an X-ray source 32, which may include one or more X-ray tubes or solid-state X- It is also operatively connected. The controller 20 may supply various control signals, such as timing signals, imaging sequences, etc., to the X-ray source 32 via the control link 34. In some embodiments, the control link 34 may also supply power, for example, to the X-ray source 32 via the control link 34. Generally, the controller 20 will transmit a series of signals to the x-ray source 32 to initiate the emission of the x-ray 36 directed to the subject, such as the patient 38. The controller can also modify the operating mode of the detector assembly 12 and synchronize the signal acquisition at the detector assembly 12 with the X-ray source 32 operation. Various features of the patient 38, such as skin, bone, etc., will attenuate the incident X-ray 36. The attenuated X-ray 40 that has passed through the patient 38 then hits the detector assembly 12 to produce an electrical signal indicative of a corresponding data scan (i.e., image). In various embodiments, the detector assembly 12 includes a scintillator material (e.g., cesium iodide (CsI) or gadolinium oxysulfide (GOS)) when exposed to high energy radiation (e.g., X- And a flat, large area optical image panel suitable for detecting photons generated by the light source. In some embodiments (e.g., digital X-ray applications), the detector assembly 12 (and the large area optical image panel included) may have dimensions from 13 cm x 13 cm to a maximum of 43 cm x 43 cm Lt; / RTI >

Large area optical imaging panels are typically fabricated in 8 "or 12" wafer form factors. However, a single chip imager size (i.e., imager chip size) typically requires less than about 10 cm x 12 cm when using an 8 "wafer configuration to produce CMOS imager wafers, or less than about 10 cm x 12 cm using a 12 & 20 cm x 20 cm. Therefore, in order to fabricate a large area optical imaging panel for use in many X-ray applications, smaller image chips can be mechanically tiled together to form a desired size imager panel. Such mechanical tiling treatments are susceptible to water ingress, which can be problematic in situations where hygroscopic scintillator materials such as CsI are used. Also, as described herein, in certain implementations, it may also be desirable to form electrical interconnections between mechanically tiled chips.

With respect to the mechanical tiling of the imager chip when creating a large assembly, the imager chip is mechanically aligned and tiled to minimize the physical gap between the imager chips and thereby also minimize the non-functional space or lines between the chips . For example, it is desirable that the gap between the imager chips is not greater than one pixel pitch, i.e., a single defective line of light or X-ray image. Also, as described herein, imager panels that are mechanically tiled in accordance with the present invention can be sealed against moisture and environment (e. G., Along a joint and seam) to provide moisture impermeable epoxy , Thereby improving the useful life of any material, such as CsI, where physical properties may be degraded if exposed to such conditions.

In connection with the potential electrical interconnection between the chips, it is desirable to physically connect the two address lines of any two imager chips so that they can be electrically connected together and thereby be treated as a single entity during read processing . This electrical connection technique is referred to as "electrical tiling ". For example, if there are four sets of "on-chip" or "off-chip" readout electronics attached to each of the four chips (ie, each set of electronics is on each chip) 2 tile chips do not require electrical tiling. The "on-chip" reading electronics situation refers to an example where the reading electronics are fabricated on the same 8 "or 12" silicon wafer as that of the optical imaging chip, and the "off chip" Quot; refers to an example made on an 8 "or 12" silicon wafer different from that of the chip. However, the electrical tiling described herein can cut the required reading electronics in half, thereby greatly reducing the detector cost and / or complexity in most cases.

With the foregoing in mind, FIG. 3 is a process flow diagram for fabricating a tile-shaped imager chip assembly according to one embodiment. According to this embodiment, the imager chips to be tiled are arranged face-down (i. E. Active or photosensitive face down) in a tiled array (block 50). Epoxy is applied along the edge and bond line of the imager chip (block 52). In certain embodiments, such as when using a hygroscopic scintillator material (e.g., CsI), the epoxy may be water impermeable. In other embodiments, such as where the scintillator material used is non-hygroscopic (e.g., GOS), the epoxy used may not be water impermeable. The substrate is then applied to the backside of the imager chip at the top of the epoxy (block 54). The assembly 58, including the substrate, epoxy and imager chips, can then be inverted (such as to raise the active or photosensitive surface) to face up for further processing as described herein ).

Referring to Figures 4-7, each step of the "face down" assembly process is graphically illustrated. 4, the backside 62 of each imager chip 60 is arranged face up with a 2x2 tile-like arrangement with little or no gaps between the imager chips 60. As shown in FIG. In one embodiment, each imager chip 60 includes an amorphous silicon (e.g., silicon) layer 60 having a photodetecting surface (i. E., Front or active surface 82) A-Si) chip. According to the "face down" tiling approach of the present invention, the photosensitive surface (i.e., the front surface) of the imager chip 60 is capable of producing a larger tiled panel having a flat, optically flat photosensitive surface at the support surface . Such an optically flat photosensitive surface enables seamless application of X-ray scintillator material, such as CsI or GOS, to the photosensitive surface of the detector panel, according to the present embodiment.

As is known, the tiled imager chip 60 may be different depending on which edge (if any) is provided with a reading electronics. In particular, each imager chip 60 can not be interchanged (i.e., not identical) with each other due to the asymmetry associated with the placement of the reading electronics. That is, the presence and / or position of the reading electronics at the various edges of the imager chip 60 can be converted into a predetermined imager chip 60 that is distinct from each other (i.e., can not be interchanged with each other) The other imager chips 60 can be rotated about the same, but substantially the same.

Referring to Figure 5, the epoxy is applied or otherwise applied along the perimeter of the tile-shaped imager chip assembly (peripheral epoxy 70). In some embodiments, air may escape when adhering the substrate to the epoxy, leaving a space in the surrounding corner or other location. In the illustrated embodiment, the epoxy is also applied along the inner bond line between the tile-shaped imager chips 60 (bond line epoxy 72). In one embodiment, such as when using a hygroscopic scintillator material, the epoxy (e.g., bondline epoxy 72) may be a moisture impermeable epoxy suitable for forming a hermetically sealed environment for the scintillator material . In other embodiments, such as where the scintillator material used is not hygroscopic, the epoxy need not be water impermeable.

The surrounding epoxy 70 allows a substrate (e.g., a backing plate) to be attached to the tile-like imager chip 60, as will be described later. In addition, the peripheral epoxy 70 may also function to support the edge of the imager chip 60 during bonding to the reading electronics module (e.g., anisotropic conductive film (ACF) bonding). The bondline epoxy 72 also facilitates the attachment of the tile-shaped imager chip 60 to the substrate and forms a moisture seal between the tile-like imager chips 60 when using a moisture impermeable epoxy to provide moisture Can be prevented from leaking through the rear side of the tile type imager chip panel.

Referring to Figure 6, in one embodiment, a substrate 78 is applied to the surrounding epoxy 70 and bond line epoxy 72, whereby the imager chip 60 is secured to the substrate 78. In one embodiment, the substrate 78 may be glass, ceramic, plastic or metal, or the substrate 78 may also be formed of other suitable materials. When the epoxy is cured (e.g., by applying heat or UV light), the chip and substrate assembly are turned over as shown in FIG. 7 to expose the front surface 82. 7, each imager chip 60 includes a scan finger 84 (for electrical interconnection with the scan line) and a data finger 86 (for electrical interconnection with the data line) Each reading electronic device in the form of a readable electronic device. As is known, each scan line and data line may be used together to control the readout of the detector panel assembly 12. [

8 is a process flow diagram illustrating a "face up" approach for fabricating chips and substrate assemblies, while the foregoing discussion is directed to a "face down" approach for fabricating chip and substrate assemblies. According to this embodiment, the imager chips to be tiled are arranged in a tiled arrangement (i.e., active or photosensitive side up) (block 100). Epoxy (i.e., moisture impermeable or otherwise) is applied to the substrate at a location corresponding to the edge and bond line of the imager chip (block 102). The tile-type imager chip is inverted and applied to a substrate having an epoxy at the edge and junction position of the corresponding imager chip (block 104). This creates the assembly 58 containing the substrate, epoxy and imager chips and is ready for further processing as described herein.

Referring to Figures 9-11, each step of the "face to face" assembly process is graphically illustrated. Referring to Figure 9, in the example shown, each imager chip 60 is arranged next to top in a 2x2 tile shape with little or no gaps between the imager chips 60 . According to the "face up" tiling approach of the present invention, the photosensitive surface (i.e., the front surface) and the reading electronics of the imager chip 60 are visible and therefore can be precisely aligned with each other. As discussed above, the tiled imager chip 60 may be different depending on which edge (if any) is provided with a reading electronics. In particular, each imager chip 60 can not be interchanged (i.e., not identical) with each other due to the asymmetry associated with the placement of the reading electronics (i.e., scan finger 84 and data finger 86) .

Referring to FIG. 10, the epoxy is printed or otherwise applied to the substrate 78 at a location corresponding to the peripheral and bonding lines associated with the tile-like imager chip 60. In the illustrated example, the epoxy is applied in a position corresponding to the inner bond line between the tile-type imager chips 60 (peripheral epoxy 70) and the perimeter corresponding to the tile-type imager chip (bondline epoxy 72) ). In one embodiment, the epoxy (e.g., bond line epoxy 72) is water impermeable and forms a moisture impermeable seal between the tile type imager chips 60. In another embodiment, the epoxy need not be water impermeable. In certain embodiments, leaving the space at the corners or other locations of the perimeter allows air to escape when the tile-like imager chip is bonded to the epoxy.

Referring to Figure 11, in one embodiment, a tile-shaped imager chip 60 is applied to a substrate 78 having a surrounding epoxy 70 and a bondline epoxy 72, whereby the imager chip 60 And is fixed to the substrate 78. For example, in one embodiment, a 2x2 tile type imager chip 60 is simultaneously picked up using a vacuum chuck to place a tile type imager chip on top of the epoxy on the substrate 78 . In some embodiments, a planar surface or weight is used to obtain an optically flat surface for the tile-like assembly after placing the tile-like imager chip 60 on the epoxy 70, . When the epoxy is cured (e.g., by applying heat or UV light), the chip and substrate assembly may be used for subsequent processing steps as described herein.

Referring to Fig. 12, a cross-sectional view taken from view line 12 of Figs. 7 and 11 is shown. This cross-section shows both the front side down and front side up chip and substrate assembly treatments described herein. As shown in Figure 12, the substrate 78 shown in cross-section is bonded to the tile-type imager chip through a line of peripheral epoxy 70 at the periphery of the tile- Type imager chip 60 by the line of the tilting-type imager chip 72. [ In the illustrated example, each imager chip 60 has a different thickness, for example due to variations or tolerances in the fabrication process for the imager chip 60. As shown, epoxies 70 and 72 can accommodate or accommodate this variation of the imager chip 60 to provide an optically flat surface of the assembly of the tile-like imager chip 60.

In one embodiment, the trench 90 between each tile-shaped imager chip 60 has a width of about 20 microns. That is, the tile-shaped imager chips 60 are separated by about 20 탆 from their respective inner edges. Typical pixel widths range from about 50 [mu] m to about 200 [mu] m. Further, in an embodiment, the height of the bondline epoxy 72 associated with the front side 82 of the imager chip 60 may range from about 20 [mu] m to about 50 [mu] m below the front side 82. [ That is, the groove 90 may have a depth in the range of about 20 탆 - 50 탆 in such an embodiment. In the illustrated example, there is no electrical interconnect between each imager chip 60 across the groove 90.

Referring to FIG. 13, a process flow diagram for illustrating subsequent processing of the chip and substrate assembly 58 is shown. In the illustrated process flow example, an optional step (block 122) of applying epoxy along an internal bond line formed by the front surface 82 of the tile-shaped imager chip assembly is performed. The epoxy is applied along or around the perimeter of the front surface of the tile-shaped imager chip assembly (block 124). A scintillator material (e.g., CsI) is applied to the front side of the tile-shaped imager chip 60 (block 126) and a faceplate is applied over the scintillator material (block 128) to the front side of the chip and substrate assembly 58 Bonded to the applied epoxy.

14, a chip and a substrate assembly 58 are shown with a data module 140 and a scanning module 144 electrically connected to a data finger 86 and a scan finger 84, respectively. In the illustrated example, one scanning module 144 and one data module 140 are attached to each imager chip 60. The number of data modules 140 and scanning modules 144 can be reduced in embodiments in which the imager chip 60 is electrically connected or bridged, as will be described in greater detail below.

Referring to Figures 15 and 16, in one embodiment, the grooves 90 in the inner bond line between the tile-like imager chips 60 are formed by thermal or UV curable epoxy or other organic film stripes or polymers, (Not shown). This filling process can provide a substantially smooth surface for the tile-like imager chip assembly prior to the scintillator deposition, and can eliminate or reduce image artifacts near the tiling joint lines. In such an embodiment, the polymer 150 may not extend over the trench 90 (i.e., the top surface of the polymer 150 coincides with the front surface 82 of the imager chip 60), or And can protrude beyond the front surface 82 of the imager chip 60 by less than 10 mu m. In another embodiment, the polymer 150 is not applied to the inner bond line of the tile-

17 and 18, in one embodiment, a closed epoxy ring 160 is printed or otherwise applied around the periphery of the tile-shaped imager chip 60. In embodiments where the hygroscopic scintillator material 162 (e.g., CsI) is applied, the epoxy need not be water impermeable. In one embodiment, the epoxy ring 160 is formed by a line of epoxy about 2 mm to 3 mm wide and about 4 to 20 mm thick (about 0.01 mm to about 0.5 mm) in thickness.

A layer of scintillator material 162 (e.g., CsI) is also deposited on the front side 82 of the imager chip 60. In one embodiment, the layer of scintillator material 162 ranges in thickness from about 300 [mu] m to about 1,000 [mu] m.

In one embodiment, the epoxy ring 160 surrounds the scintillator material 162 along the flat front surface defined by the tile-shaped imager chip 60 and protects the scintillator material 162 from, for example, moisture And is used as a gasket. In certain embodiments, the epoxy ring 160 is separated from the scintillator material by, for example, a gap of about 5 mm in width. 18, the epoxy from the epoxy ring 160, at the junction, or groove 90, formed between the imager chips 60, is the same as in the embodiment where the epoxy material is water impermeable , And joins with the lower bonding line epoxy (72) to form a hermetic seal.

19, a face plate 166 is secured to the epoxy ring 160, thereby covering the scintillator material 162. The faceplate 166 is provided with an enclosed seal against the scintillator material 162 in embodiments in which the epoxy material is water impermeable, together with the imager chip 60 and various epoxy applications . In one embodiment, the face plate is a low X-ray attenuation cover plate formed of aluminum and graphite, such as graphite coated or coated with aluminum.

Although the above description focuses on the imager chip 60 that is not electrically connected and that is separately read and controlled, in other implementations, the imager chip may be electrically connected (i.e., electrically ). ≪ / RTI > For example, referring to FIG. 20, a cross-section of a junction between two mechanically tiled imager chips 60 is shown. According to this embodiment, the contact pads 174 (e.g., aluminum pads) of each imager chip 60 are electrically conductive to form electrical connections between the respective imager chips 60, ) Or a line (e. G., Aluminum or copper) by direct writing or otherwise depositing. In the illustrated example, the conductive material 172 is applied by directly writing metal stitches between the pads 174 on each imager chip 60 or shorting the bars. In the illustrated example, a dielectric layer 170 is applied over the conductive material 172 to provide passivation. In this way, the scan lines and / or data lines of two different imager chips 60 can be continuous.

21, a tile-shaped imager chip 60, in which the scan lines are electrically connected or tiled between respective imager chips 60, is shown as a conductive bridge 180, . In this example, the data lines of each imager chip 60 are not electrically connected as shown by the non-conductive gaps or materials 182. [ Because of the electrical bridging between the scan lines of each imager chip 60, each bridged pair of imager chips 60 can be handled or read by a single scan module 144. [ That is, only one scanning module 144 is required for each row of imager chip 60. [ Conversely, since the data lines of the imager chip 60 are not electrically bridged, each data module 140 is required to read each imager chip 60. [ That is, each column of imager chip 60 requires two data modules 140, one for each imager chip 60 in the column for reading. In such an embodiment, the pixels of the detector panel may extend all the way to the edge of the panel (here the right edge of the panel) because the reading electronics are not needed at that edge.

22, in a further example, the data lines and scan lines of adjacent imager chips 60 are electrically bridged or otherwise connected, as indicated by respective conductive bridges 180. [ Because of the electrical bridging between the scan lines of each imager chip 60, each bridged pair of imager chips 60 can be handled or read by a single scan module 144. [ That is, only one scanning module 144 is required for each row of imager chip 60. [ Similarly, due to the electrical bridging between the data lines of each imager chip 60, each bridged pair of imager chips 60 may be handled or read by a single data module 140. That is, only one data module is required for each column of the imager chip 60. In such an embodiment, the pixels of the detector panel may extend both towards the two edges of the panel (here the right and bottom edges of the panel) because the reading electronics are not needed at that edge. Note that the "off-chip" read electronics (ie, the "off-chip" scan module 144 and the data module 140) are shown in Figures 14, 16, 21 and 22 for simplicity of illustration. In other embodiments, however, readout electronics (i.e., scan and data circuits or modules) may be fabricated as "on-chip ", i.

The technical effect includes the fabrication of a detector panel comprising a plurality of tile-shaped imager chips with a gap between the imager chips being one pixel wide or less. A further technical effect is in the manufacture of detector panels comprising a plurality of tile-shaped imager chips with the scintillator material hermetically sealed. Further, the technical effect is in the manufacture of a detector panel including a plurality of tile-shaped imager chips in which data lines and / or scanning lines of other imager chips are electrically continuous.

To describe the present approach, including the best mode, and any person skilled in the art, including making and using any device or system and performing any integrated method, In order to enable the described invention to be practiced, a plurality of examples have been used. The patentable scope is defined by the claims and may include other examples that one of ordinary skill in the art might conceive. Such another example would be that if the other example had a structural element that was not substantially different from that described in the claims or if it contained an equivalent structural element that was a non-substantial difference from that described in the claims, Are intended to be included.

Claims (22)

A method of manufacturing a tiled detector panel,
Placing the imager chip in a tiled arrangement with the front side down;
Applying an epoxy to the backside of the imager chip along an internal bond line of the tile array of imager chips;
Applying a substrate to the epoxy on the backside of the imager chip;
Applying a ring of epoxy to the front side of the imager chip;
Depositing a scintillator material on the front side of the imager chip;
And applying a faceplate to the ring of epoxy to form a sealed environment containing the scintillator material. The method of claim 1, wherein the epoxy applied to at least the inner bond line to form a ring is a water impermeable epoxy. 2. The method of claim 1, further comprising applying a polymeric composition to the front side of the imager chip to fill the grooves between the imager chips prior to depositing the scintillator material. The method of claim 1, further comprising electrically connecting one or more scan lines of adjacent imager chips such that the electrically connected scan lines can be read by a single scan module. The method of claim 1, further comprising electrically connecting one or more data lines of adjacent imager chips such that the electrically connected data lines can be read by a single data module. 2. The method of claim 1, wherein the substrate comprises a glass, metallic, plastic or ceramic support plate. The method of claim 1, wherein the face plate comprises graphite and aluminum. The method of claim 1, wherein the gap between the tile type imager chips is less than one pixel wide. A method of manufacturing a tiled detector panel,
Placing the imager chip in a tiled arrangement with the front side facing up;
Applying epoxy on the substrate at a location corresponding to an inner bond line associated with the tile-like arrangement of the imager chip;
Applying a tile-like arrangement of imager chips to the epoxy on the substrate such that an internal bond line of the tile-like arrangement of the imager chip is disposed over the epoxy;
Applying a ring of epoxy to the front side of the imager chip;
Depositing a scintillator material on the front side of the imager chip;
And applying a face plate to the ring of epoxy to form a sealed environment containing the scintillator material. 10. The method of claim 9, wherein the epoxy corresponding to at least the inner bond line and forming the ring is a water impermeable epoxy. 10. The method of claim 9, further comprising applying a polymer composition to the front side of the imager chip to fill the grooves between the imager chips prior to depositing the scintillator material. 10. The method of claim 9, further comprising electrically connecting one or more scan lines of adjacent imager chips such that the electrically connected scan lines can be read by a single scan module. 10. The method of claim 9, further comprising electrically connecting one or more data lines of adjacent imager chips such that the electrically connected data lines can be read by a single data module. 10. The method of claim 9, wherein the gap between the tile type imager chips is less than one pixel wide. 10. The method of claim 9, wherein the tile-like arrangement of the imager chips is applied to an epoxy on the substrate using a vacuum chuck for picking up the tile-like arrangement. In the detector panel,
A tiled array of imager chips including a front side and a back side;
At the junction between the imager chips, is applied to the backside of the tile-like arrangement of the imager chip and is applied at least partially to the backside of the imager chip along the periphery of the tile-like arrangement of the imager chip, An epoxy applied to the front side of the imager chip in a ring around the perimeter of the tile arrangement of the imager chip;
A substrate attached to the tile-like arrangement of the imager chip by an epoxy applied to a backside of the imager chip;
A faceplate attached to a tile-like arrangement of the imager chip by a ring of epoxy applied to the front side of the imager chip, the faceplate, the ring of epoxy, the epoxy applied to the bonding line and the imager chip forming a sealing environment - and;
And a scintillator material deposited on the front side of the imager chip within the sealing environment. 17. The detector panel of claim 16 wherein the tiled array of imager chips is separated by a gap of less than one pixel width. 17. The detector panel of claim 16, further comprising a polymeric composition applied to a front side of the tile-like arrangement of the imager chip to fill a gap between the tile-shaped imager chips. 17. The detector panel of claim 16, further comprising an electrical connection formed between one or more scan lines of adjacent imager chips such that electrically connected scan lines can be read by a single scan module. 17. The detector panel of claim 16, further comprising an electrical connection formed between one or more data lines of adjacent imager chips such that electrically connected data lines can be read by a single data module. 17. The detector panel of claim 16, wherein the tile-shaped imager chips are separated by less than about 20 microns. 17. The detector panel of claim 16, wherein the epoxy is also applied at least partially to the backside of the imager chip along the periphery of the tiled array of the imager chip.

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