KR20150008552A - Semiconductor Apparatus and Method for Manufacturing The same - Google Patents

Abstract

Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device according to the present technique includes a lower electrode formed on a semiconductor substrate and a support layer pattern which supports the lower electrode. The width of the upper part of the lower electrode can be smaller than that of the lower part of the lower electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a lower electrode and a manufacturing method thereof.

Recently, in the case of a semiconductor device such as a DRAM, the area occupied by the device is reduced as the degree of integration increases, while the required capacitance is required to be maintained or increased. In general, examples of a method for ensuring sufficient cell capacitance within a limited area include a method of using a high dielectric material as a dielectric film, a method of reducing a thickness of a dielectric film, and a method of increasing an effective area of a lower electrode . Among them, the method of using the high dielectric material requires material and time investment such as introduction of new equipment, necessity of verification of reliability and mass production of dielectric film, and lowering of the subsequent process. Accordingly, a method of increasing the effective area of the lower electrode is widely used in actual processes because the dielectric film used in the past can be used continuously and the process can be relatively easily implemented.

According to an embodiment of the present invention, a support film (NFC nitride film) is formed on an insulating film, a support hole and an insulating film are etched to form a wide hole, a lower electrode is formed in the hole, A semiconductor device for patterning a support film supporting each other, then partially dipping out the exposed insulating film, then trimming the exposed lower electrode, and full dip-out the remaining insulating film, and And a manufacturing method thereof.

A semiconductor device according to an embodiment of the present invention includes a first lower electrode provided on a semiconductor substrate, a second lower electrode provided on the first lower electrode, and a supporting film pattern supporting the second lower electrode together The width of the lower portion of the second lower electrode may be smaller than the width of the upper portion of the first lower electrode.

A semiconductor device according to another embodiment of the present invention includes a first lower electrode provided on a semiconductor substrate, a first supporting film pattern for supporting the first lower electrode together, a second lower electrode provided on the first lower electrode, And a second supporting film pattern for supporting the second lower electrode with respect to each other. The width of the lower portion of the second lower electrode may be smaller than the width of the upper portion of the first lower electrode.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a lower electrode provided on a semiconductor substrate; and a supporting film pattern for supporting the lower electrode, wherein a thickness of the supporting film pattern connecting the lower electrode contacts a supporting film pattern Can be formed larger than the thickness of the lower electrode of the region.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes sequentially forming a first insulating film and a supporting film on a semiconductor substrate, etching the supporting film and the first insulating film until the semiconductor substrate is exposed, Forming an electrode contact hole, forming a lower electrode in the lower electrode contact hole, forming a supporting film pattern supporting the lower electrode by etching the supporting film, etching the first insulating film Forming a lower electrode having a reduced width by trimming the exposed lower electrode, and etching the remaining first insulating film.

The lower electrode may be formed in a pillar shape.

The support film pattern may include a nitride film.

The first etching step may perform a partial dip out process.

The second etching step may be performed by a full dip-out process.

After forming the support film, the method further includes forming a second insulating film on the support film.

And forming an etch stop film between the semiconductor substrate and the first insulating film.

     According to another aspect of the present invention, there is provided a semiconductor device including a core unit for performing an operation corresponding to the instruction using data in accordance with an instruction input from the outside, data for performing the operation, A cache memory unit for storing at least one of data and an address of data for performing the operation, a bus interface connected between the core unit and the cache memory unit, for transmitting data between the core unit and the cache memory unit, An embedded memory unit for storing data, a communication module unit capable of transmitting and receiving data wired or wirelessly with an external device, a memory control unit for driving an external memory device, and an external interface device, And a media processing unit for processing and outputting data input from the apparatus, The embedded memory unit includes a first lower electrode provided on a semiconductor substrate, a second lower electrode provided on the first lower electrode, and a support film pattern for supporting the second lower electrode with each other, And the width of the lower portion of the lower electrode may be smaller than the width of the upper portion of the first lower electrode.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a processor for interpreting a command input from the outside and controlling an operation of information according to a result of analyzing the command; a program for interpreting the command; A main storage device for moving and storing the program and the information from the auxiliary storage device so that the processor can perform the operation using the program and the information when the program is executed; And an interface device for performing communication with at least one of the main memory devices and the outside, wherein the main memory device includes a first lower electrode provided on a semiconductor substrate, a second lower electrode provided above the first lower electrode, And a support film pattern for supporting the second lower electrodes with each other, The width of the lower portion of the lower electrode 2 may include a structure wherein the formed smaller than the top width of the first lower electrode.

A semiconductor device according to another embodiment of the present invention includes a storage device that stores data and stores data stored regardless of a supplied power source, a controller that controls data input / output of the storage device according to an instruction input from the outside, And an interface for communicating with at least one of the storage device, the controller, and the temporary storage device, and an interface for performing external communication with the at least one of the storage device, the controller, and the temporary storage device, And a supporting film pattern for supporting the first lower electrode provided on the substrate, the second lower electrode provided above the first lower electrode, and the second lower electrode, wherein the width of the lower portion of the second lower electrode is The lower electrode may have a width smaller than an upper width of the first lower electrode.

A semiconductor device according to another embodiment of the present invention includes a memory for storing data and storing data regardless of a supplied power source, a memory controller for controlling data input / output of the storage device according to an instruction input from the outside, And an interface for communicating with at least one of the storage device, the memory controller, and the buffer memory, wherein the buffer memory is provided on the semiconductor substrate And a supporting film pattern for supporting the first lower electrode, the second lower electrode provided above the first lower electrode, and the second lower electrode, wherein a width of a lower portion of the second lower electrode is larger than a width of the first May be formed to have a width smaller than the width of the upper portion of the lower electrode.

In this technique, a support film (NFC nitride film) is formed on an insulating film, a support hole and an insulating film are etched to form a wide hole, a lower electrode is formed in the hole, After the film is patterned, the exposed insulating film is partially dipped out, then the exposed lower electrode is trimmed, and the remaining insulating film is full-dip-out to increase the height of the lower electrode. And it has the effect of increasing Cs (capacitance) without adding manufacturing equipment or manufacturing process.

1A to 1D are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.
2 is a plan view for explaining a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.
3A to 3E are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present invention.
4 is a block diagram of a processor according to an embodiment of the present invention.
5 is a configuration diagram of a system according to an embodiment of the present invention.
6 is a configuration diagram of a data storage system according to an embodiment of the present invention.
7 is a block diagram of a memory system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1A to 1D are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 1A, a first insulating layer 110 is formed on a semiconductor substrate 100, and a supporting layer 120 is formed on a first insulating layer 110.

Here, the first insulating layer 110 may be defined or named as a sacrificial layer. In addition, the support film 120 may be defined or named as an NFC (Nitride Floating Cap) film, and may include a nitride film. In addition, the etch stop layer 105 may be formed between the semiconductor substrate 100 and the first insulating layer 110. Here, the etch stop film 105 may include a nitride film. The etch stop layer 105 serves as a buffer layer or a buffer layer to prevent excessive etching when forming a lower electrode contact hole or a storage node contact hole in a subsequent process.

In addition, the first insulating layer 110 may be formed of a layer of a phosphosilicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer, or may be formed of a single layer of a TEOS layer.

Thereafter, a second insulating layer 130 is formed on the support layer 120. Here, the second insulating layer 130 may be a layered structure of a PSG (Phospho Silicate Glass) layer and a TEOS (Tetraethylorthosilicate) layer, or may be a single layer of a TEOS layer.

Then, a photoresist film is formed on the second insulating film 130, and then a photoresist pattern (not shown) is formed by performing exposure and development processes using a mask defining a lower electrode contact hole (storage node contact hole).

Next, the second insulating film 130, the supporting film 120, the first insulating film 110, and the etching stopper film 105 are etched until the semiconductor substrate 100 is exposed using the photoresist pattern as an etching mask, A contact hole 140 is formed. Here, the lower electrode contact hole 140 is formed to be wider than the lower electrode contact hole using the conventional technique, thereby reducing the aspect ratio (A / R), which is a ratio of the bottom area and the height of the lower electrode contact hole 140 .

Referring to FIG. 1B, a conductive film is embedded in the lower electrode contact hole 140 to form the lower electrode 150. Here, the lower electrode 150 may have a pillar structure or a cylinder structure, and the pillar structure of the present invention will be described in detail. The lower electrode 150 may be formed of a laminate structure of titanium (Ti) and titanium nitride (TiN) or a single layer.

Here, the height of the lower electrode 150 may be about the same as the height of the second insulating layer 130 (see FIG. 1A). In addition, the height of the lower electrode 150 may be higher than that of the supporting film (120 of FIG. 1A) and the second insulating film (130 of FIG. 1A).

Next, the second insulating layer 130 is completely removed until the first insulating layer 110 is exposed, and a part of the support layer 120 is etched to form the support layer pattern 125 supporting the lower electrode 150 . At this time, since the second insulating layer 130 and the supporting layer 120 are different materials, they can be etched using a plurality of etching solutions.

Here, the shape of the support film pattern 125 can be embodied in various shapes. For example, rectangular, rectangular, annular or diamond-shaped.

Referring to FIG. 1C, a part of the exposed first insulation layer 110 is partially removed using a partial dip-out process. The removed first insulating film 110 is not to exceed a half of the total height of the first insulating film 110.

Next, the lower electrode 150 exposed by the partial dip-out process is trimmed to reduce the diameter or the width W. This trimmed upper-side lower electrode 150a can prevent the leakage of the leakage current to the adjacent upper-side lower electrode 150a. At this time, the upper and lower electrodes 150a may be defined as a second lower electrode.

The diameter or the width W of the upper side lower electrode 150a is smaller than the diameter or the width W of the lower side lower electrode 150b by removing the remaining first insulating film 110 by using a full dip- May be formed to be smaller than the diameter or width W '. More specifically, the width of the lower portion of the upper-side lower electrode 150a may be smaller than the width of the upper portion of the lower-side lower electrode 150b. In addition, the lower lower electrode 150b may be defined as a first lower electrode or may be named. The thickness D of the supporting film pattern 125 connecting the upper and lower electrodes 150a is thicker or thicker than the thickness D 'of the upper lower electrode 150a in the region contacting the supporting film pattern 125 And may be formed to have the same thickness as each other.

As described above, in the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, a supporting film (NFC nitride film) is formed on the insulating film, a hole is formed by etching the supporting film and the insulating film, After the supporting film supporting the neighboring lower electrodes is patterned, the exposed insulating film is partially dipped out, the exposed lower electrode is trimmed, and the remaining insulating film is fully dipped out (Full Dip Out) Dip-out), the height of the lower electrode can be increased, and Cs (capacitance) can be increased without adding manufacturing equipment or manufacturing process.

2 is a plan view for explaining a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.

Referring to FIG. 2, the diameter or the width W of the upper-side lower electrode 150a is smaller than the diameter or the width W 'of the lower-side lower electrode 150b. The present invention increases the height of the lower electrodes 150a and 150b and increases the space between the adjacent lower electrodes 150a, thereby preventing leakage current between the adjacent lower electrodes 150a.

3A to 3E are plan views illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present invention.

Referring to FIG. 3A, a first insulating layer 210 is formed on a semiconductor substrate 200, and then a first supporting layer 220 is formed on a first insulating layer 210.

Here, the first insulating layer 210 may be defined or named as a sacrificial layer. In addition, the first supporting film 220 may be defined or named as an NFC (Nitride Floating Cap) film, and may include a nitride film. In addition, the etch stop layer 205 may be formed between the semiconductor substrate 200 and the first insulating layer 210. Here, the etch stop film 205 may include a nitride film. The etch stop layer 205 acts as a buffer layer or a buffer layer to prevent excessive etching when forming a lower electrode contact hole or a storage node contact hole in a subsequent process. In addition, the first insulating layer 210 may be formed of a layer of a phosphosilicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer, or may be formed of a single layer of a TEOS layer.

Thereafter, a second insulating layer 230 is formed on the first supporting layer 220. Here, the second insulating layer 230 may be a laminated structure of a PSG (Phospho Silicate Glass) layer and a TEOS (Tetraethylorthosilicate) layer, or may be formed of a single layer of a TEOS layer.

A second supporting film 240 and a third insulating film 250 are sequentially formed on the second insulating film 230. The third insulating layer 250 may include a phosphorus silicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer. The second insulating layer 250 may be a NIT (Nitride Floating Cap) layer or a nitride layer. ) Film, or a single layer of a TEOS film.

Then, a photoresist film is formed on the third insulating film 250, and then a photoresist pattern (not shown) is formed by performing exposure and development processes using a mask defining a lower electrode contact hole (storage node contact hole).

Next, the third insulating film 250, the second supporting film 240, the second insulating film 230, the first supporting film 220, and the third insulating film 250 are sequentially patterned using the etching mask until the semiconductor substrate 200 is exposed. 1 insulating film 210 and the etching stopper film 205 are etched to form a lower electrode contact hole 255. Here, the lower electrode contact hole 255 is formed to be wider than the lower electrode contact hole of the related art, thereby reducing the aspect ratio (A / R), which is the ratio of the bottom area and the height of the lower electrode contact hole 255.

Referring to FIG. 3B, a conductive film is embedded in the lower electrode contact hole 255 to form the lower electrode 260. Here, the lower electrode 260 may be formed of a pillar structure or a cylinder structure, and the pillar structure of the present invention will be described in detail. Here, the lower electrode 260 may be formed of a laminate structure of titanium (Ti) and titanium nitride (TiN) or a single layer.

The height of the lower electrode 260 may be approximately the same as the height of the third insulating film 250 (FIG. 3A). In addition, the height of the lower electrode 260 may be higher than the height of the second supporting film (240 in FIG. 3A) and the third insulating film (250 in FIG. 3A).

Next, the third insulating film 250 is completely removed until the second insulating film 230 is exposed, and a part of the second supporting film 240 is etched to form a second supporting film pattern (245). At this time, since the third insulating layer 250 and the second support layer 240 are different materials, they can be etched using a plurality of etching solutions.

Here, the shape of the second supporting film pattern 245 can be implemented in various shapes. For example, rectangular, rectangular, annular or diamond-shaped.

Referring to FIG. 3C, the exposed second insulation layer 230 is removed until the first support layer 220 is exposed using a partial dip-out process.

Next, the lower electrode 260 exposed by the partial dip-out process is trimmed to reduce the diameter or the width W. [ This trimmed upper-side lower electrode 260a can prevent the leakage of the leakage current to the adjacent upper-side lower electrode 260a. At this time, the upper-side lower electrode 260a may be defined or named as the second lower electrode.

Referring to FIG. 3D, the exposed first support film 220 is etched to form a first support film pattern 225. Here, the shape of the first supporting film pattern 225 may be embodied in various shapes. For example, rectangular, rectangular, annular or diamond-shaped.

Referring to FIG. 3E, the remaining first insulating layer 210 is removed until the etch stop layer 205 is exposed using a full dip-out process.

Next, the lower electrode 260 exposed by the full dip-out process is trimmed to reduce the diameter or the width W. FIG. Here, after the full dip-out process, the entire surface of the lower electrodes 260a and 260b may be exposed and all trimmed.

The trimming upper and lower electrodes 260a and 260b can prevent the leakage current from being generated between the upper and lower electrodes.

The diameter or the width W of the upper side lower electrode 260a may be smaller than the diameter or the width W 'of the lower side lower electrode 260b. More specifically, the width of the lower portion of the upper-side lower electrode 260a may be smaller than the width of the upper portion of the lower-side lower electrode 260b. Here, the lower lower electrode 260b may be defined or named as the first lower electrode. The present invention has the effect of preventing leakage current by increasing the height of the lower electrodes 260a and 260b while enlarging the space between the adjacent lower electrodes 260a and 260b.

The thickness D of the second supporting film pattern 245 connecting the upper side lower electrode 260a is greater than the thickness D 'of the upper side lower electrode 260a in the region contacting the second supporting film pattern 245 They may be thick or large, and they may be formed to have the same thickness. The thickness D of the first supporting film pattern 225 connecting the lower lower electrode 260b is greater than the thickness D 'of the upper lower electrode 260b in the region contacting the first supporting film pattern 225 They may be thick or large, and they may be formed to have the same thickness.

The second supporting film pattern 245 and the first supporting film pattern 225 can prevent the falling-off failure even if the aspect ratio of the lower electrode 260 is greatly increased. In addition, Can be prevented. That is, the present invention can be implemented using a plurality of supporting film patterns and a trimming process, and the operating characteristics of the semiconductor device can be improved.

4 is a block diagram of a processor 1100 according to an embodiment of the present invention.

As shown in FIG. 4, the processor 1100 includes various functions other than a microprocessor for controlling and adjusting a series of processes of receiving data from various external devices, processing the data, and transmitting the result to an external device And may include a core unit 1110, a cache memory unit 1120, and a bus interface 1130. In addition, The core unit 1110 of the present embodiment may include a storage unit 1111, an arithmetic unit 1112, and a control unit 1113 for performing arithmetic and logic operations on data input from an external apparatus. The processor 1100 may be a system-on-chip (SoC) such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

The storage unit 1111 may include a data register, an address register, and a floating-point register as a part for storing data in the processor 1100 by a processor register or a register, . The storage unit 1111 may temporarily store an address in which data for performing an operation, execution result data, and data for execution in the operation unit 1112 are stored. The arithmetic operation unit 1112 performs arithmetic operations within the processor 1100 and performs various arithmetic operations or logical operations according to the result of decoding the instructions by the control unit 1113. [ The computing unit 1112 may include one or more arithmetic and logic units (ALUs). The control unit 1113 receives signals from the storage unit 1111 and the arithmetic unit 1112 and the external apparatuses of the processor 1100 to extract and decode instructions and control input and output, do.

Unlike the core unit 1110 which operates at high speed, the cache memory unit 1120 temporarily stores data in order to compensate for a difference in data processing speed of an external device at a low speed. The cache memory unit 1120 includes a primary storage unit 1121, Unit 1122, and a tertiary storage unit 1123. [0051] FIG. In general, the cache memory unit 1120 includes a primary storage unit 1121 and a secondary storage unit 1122, and may include a tertiary storage unit 1123 when a high capacity is required. have. That is, the number of storage units included in the cache memory unit 1120 may vary depending on the design. Here, the processing speeds for storing and discriminating data in the primary, secondary, and tertiary storage units 1121, 1122, and 1123 may be the same or different. If the processing speed of each storage unit is different, the speed of the primary storage unit may be the fastest. One or more storage units of the primary storage unit 1121, the secondary storage unit 1122 and the tertiary storage unit 1123 of the cache memory unit may include one of the embodiments of the semiconductor device described above.

4 illustrates the case where the primary, secondary, and tertiary storage units 1121, 1122, and 1123 are all configured in the cache memory unit 1120. However, the primary, secondary, and tertiary storage units 1121, The car storage units 1121, 1122, and 1123 may be configured outside the core unit 1110 to compensate for a difference in processing speed between the core unit 1110 and the external device. The primary storage unit 1121 of the cache memory unit 1120 may be located inside the core unit 1110 and the secondary storage unit 1122 and the tertiary storage unit 1123 may be located inside the core unit 1110. [ So that the function for supplementing the processing speed can be further strengthened.

The bus interface 1430 connects the core unit 1110 and the cache memory unit 1120 to efficiently transmit data.

The processor 1100 according to the present embodiment may include a plurality of core units 1110 and a plurality of core units 1110 may share the cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be connected through a bus interface 1430. The plurality of core portions 1110 may all have the same configuration as the core portion described above. The primary storage unit 1121 of the cache memory unit 1120 is configured in each of the core units 1110 corresponding to the number of the plurality of core units 1110, The main storage unit 1122 and the tertiary storage unit 1123 may be shared by a plurality of core units 1110 through a bus interface 1430. Here, the processing speed of the primary storage unit 1121 may be faster than the processing speed of the secondary and tertiary storage units 1122 and 1123.

The processor 1100 according to the present embodiment includes an embedded memory unit 1140 for storing data, a communication module unit 1150 for transmitting and receiving data wired or wirelessly with an external apparatus, The memory control unit 1160 may further include a media processing unit 1170 for processing and outputting data processed by the processor 1100 or data input from the external input device to the external interface device. . ≪ / RTI > In this case, a plurality of modules added to the core unit 1110, the cache memory unit 1120, and mutual data can be exchanged through the bus interface 1430. The embedded memory unit 1140 A lower electrode provided on the semiconductor substrate and a supporting film pattern supporting the lower electrode, wherein a width of an upper portion of the lower electrode is smaller than a width of a lower portion of the lower electrode.

A support film (NFC nitride film) is formed on the insulating film as above, a hole is formed by etching the support film and the insulating film, a lower electrode is formed in the hole, a support film supporting the neighboring lower electrode is patterned, The height of the lower electrode can be increased by partially dipping out the exposed insulating film, trimming the exposed lower electrode, and full dip-out the remaining insulating film. , It has the effect of increasing Cs (capacitance) without adding manufacturing equipment or manufacturing process. Accordingly, the performance characteristics of the processor 1100 including the embedded memory unit 1140 can be improved, so that the performance of the processor 1100 can be improved.

In addition, the embedded memory unit 1140 may include a nonvolatile memory as well as a volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a mobile DRAM, and a static random access memory (SRAM). The nonvolatile memory may be a read only memory (ROM), a Nor Flash memory, (PRAM), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a magnetic random access memory (MRAM), and the like. have.

The communication module unit 1150 may include both a module capable of connecting with a wired network and a module capable of connecting with a wireless network. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), and the like. (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless Local Area Network (WLAN) Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC) , A wireless broadband Internet (Wibro), a high speed downlink packet access (HSDPA), a wideband code division multiple access (WCDMA), an ultra wideband UWB), and the like.

The memory control unit 1160 is used for managing data transmitted between the processor 1100 and an external storage device operating according to a different communication standard. The memory control unit 1160 may include various memory controllers, IDE (Integrated Device Electronics), Serial Advanced Technology Attachment ), A SCSI (Small Computer System Interface), a RAID (Redundant Array of Independent Disks), an SSD (Solid State Disk), an eSATA (External SATA), a PCMCIA (SD), mini Secure Digital (mSD), micro Secure Digital (SD), Secure Digital High Capacity (SDHC), Memory Stick Card, a smart media card (SM), a multi media card (MMC), an embedded multimedia card (eMMC), a compact flash card F), and the like.

The media processing unit 1170 is a graphics processing unit (GPU) that processes data processed by the processor 1100 or data input from an external input device and outputs the processed data to an external interface device for transmission in video, audio, A Digital Signal Processor (DSP), a High Definition Audio (HD Audio), a High Definition Multimedia Interface (HDMI) controller, and the like.

5 is a configuration diagram of a system 1200 according to an embodiment of the present invention.

As shown in FIG. 5, the system 1200 can perform input, processing, output, communication, storage, and the like to perform a series of operations on data with a device that processes data, and includes a processor 1210, Device 1220, an auxiliary storage device 1230, and an interface device 1240. The system of this embodiment may be a computer, a server, a PDA (Personal Digital Assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, A mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, a voice recorder And may be various electronic systems operating using a process such as a Recorder, a Telematics, an Audio Visual System, and a Smart Television.

The processor 1210 is a core configuration of a system for controlling the processing of input commands and the processing of data stored in the system, and includes a microprocessor unit (MPU), a central processing unit (CPU) ), A single / multi core processor, a graphics processing unit (GPU), an application processor (AP), and a digital signal processor (DSP) Lt; / RTI >

The main memory unit 1220 may include a semiconductor device according to the above-described embodiment as a memory unit in which a program or data can be moved and executed from the auxiliary memory unit 1230 when the program is executed. The main memory unit 1220 includes a lower electrode provided on the semiconductor substrate and a supporting film pattern for supporting the lower electrode, and the width of the upper portion of the lower electrode is smaller than the width of the lower portion of the lower electrode .

A support film (NFC nitride film) is formed on the insulating film as above, a hole is formed by etching the support film and the insulating film, a lower electrode is formed in the hole, a support film supporting the neighboring lower electrode is patterned, The height of the lower electrode can be increased by partially dipping out the exposed insulating film, trimming the exposed lower electrode, and full dip-out the remaining insulating film. , It has the effect of increasing Cs (capacitance) without adding manufacturing equipment or manufacturing process. Accordingly, the performance of the system 1200 including the main memory 1220 can be improved, and thus the performance of the system 1200 can be improved.

In addition, the main memory 1220 may include volatile memory type static random access memory (SRAM), dynamic random access memory (DRAM), or the like, all of which are erased when the power is turned off.

The auxiliary storage device 1230 refers to a storage device for storing program codes and data. The auxiliary storage device 1230 may be a magnetic tape using a magnetic tape, a magnetic disk, a laser disk using light, a magneto-optical disk using both of them, a solid disk A solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a Secure Digital (SD) card, a mini Secure Digital card (mSD) , A Secure Digital High Capacity (SDHC), a Memory Stick Card, a Smart Media Card (SM), a MultiMediaCard (MMC), a built-in multimedia card An Embedded MMC (eMMC), a Compact Flash (CF), and the like.

The interface device 1240 may be used for exchanging commands and data between the system of the present embodiment and an external device. The interface device 1240 may include a keypad, a keyboard, a mouse, a speaker, a microphone, , A display device, various human interface devices (HID), and a communication device. The communication device may include both a module capable of connecting with a wired network and a module capable of connecting with a wireless network. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), and the like. (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless Local Area Network (WLAN) Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC) , A wireless broadband Internet (Wibro), a high speed downlink packet access (HSDPA), a wideband code division multiple access (WCDMA), an ultra wideband UWB), and the like.

6 is a configuration diagram of a data storage system 1300 according to an embodiment of the present invention.

6, the data storage system 1300 includes a storage device 1310 having a nonvolatile property for storing data, a controller 1320 for controlling the storage device 1310, and an interface 1330 for connecting to an external device . The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read only memory (CDROM), a digital versatile disk (DVD), a solid state disk (USB) memory, Secure Digital (SD), mini Secure Digital card (mSD), microSecure digital card (micro SD), high capacity secure digital card Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC), Embedded MMC (eMMC) And may be in the form of a card such as a flash card (Compact Flash; CF).

The controller 1320 may control the exchange of data between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for computing and processing instructions entered via the interface 1330 outside the data storage system 1300.

The interface 1330 is used for exchanging commands and data between the data storage system 1300 and the external device. When the data storage system 1300 is a card, a USB (Universal Serial Bus Memory), a Secure Digital A mini Secure Digital card (mSD), a micro Secure Digital card (SD), a Secure Digital High Capacity (SDHC), a Memory Stick Card, a Smart Media Card An interface compatible with a Smart Media Card (SM), a Multi Media Card (MMC), an Embedded MMC (eMMC), and a Compact Flash (CF). In the case of a disk, it is possible to use an IDE (Integrated Device Electronics), a SATA (Serial Advanced Technology Attachment), a SCSI (Small Computer System Interface), an eSATA (External SATA), a PCMCIA It can be a compatible interface.

The data storage system 1300 of the present embodiment is a temporary storage device for efficiently transferring data between the interface 1330 and the storage device 1310 in accordance with diversification and high performance of an interface with an external device, 1340). The storage device 1310 or the temporary storage device 1340 may include the semiconductor device according to the above-described embodiments. The storage device 1310 or the temporary storage device 1340 includes a lower electrode provided on a semiconductor substrate and a supporting film pattern for supporting the lower electrode, wherein a width of an upper portion of the lower electrode is greater than a width of a lower portion of the lower electrode Lt; / RTI >

A support film (NFC nitride film) is formed on the insulating film as above, a hole is formed by etching the support film and the insulating film, a lower electrode is formed in the hole, a support film supporting the neighboring lower electrode is patterned, The height of the lower electrode can be increased by partially dipping out the exposed insulating film, trimming the exposed lower electrode, and full dip-out the remaining insulating film. , It has the effect of increasing Cs (capacitance) without adding manufacturing equipment or manufacturing process. This can improve the operational characteristics of the data storage system 1300 including the storage device 1310 or the temporary storage device 1340, thereby enabling the performance enhancement of the data storage system 1300.

7 is a block diagram of a memory system 1400 according to one embodiment of the present invention.

As shown in FIG. 7, the memory system 1400 includes a memory 1410 having a non-volatile characteristic, a memory controller 1420 for controlling the memory 1410, and an interface 1430 for connecting to an external device, can do. The memory system 1400 may include a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a Secure Digital (SD), a mini Secure Digital card (mSD) , A micro secure digital card (micro SD), a secure digital high capacity (SDHC), a memory stick card, a smart media card (SM), a multi media card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

In addition, the memory of the present embodiment may be a non-volatile memory such as a ROM (Read Only Memory), a Nor Flash Memory, a NAND Flash Memory, a Phase Change Random Access Memory (PRAM), a Resistive Random Access Memory ), A magnetic random access memory (MRAM), and the like.

Memory controller 1420 may control the exchange of data between memory 1410 and interface 1430. [ To this end, the memory controller 1420 may include a processor 1421 for computing and processing instructions entered via the interface 1430 outside the memory system 1400.

The interface 1430 is used for exchanging commands and data between the memory system 1400 and an external device and includes a USB (Universal Serial Bus), a Secure Digital (SD) card, a mini Secure Digital card mSD), a microsecure digital card (micro SD), a secure digital high capacity (SDHC), a memory stick card, a smart media card (SM), a multi media card (Multi Media card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

The memory system 1400 of the present embodiment includes a buffer memory (not shown) for efficiently transmitting and receiving data between the interface 1430 and the memory 1410 in accordance with diversification and high performance of an interface with an external device, a memory controller, 1440). The buffer memory 1440 for temporarily storing data may include the semiconductor device according to the above-described embodiment. The buffer memory 1440 includes a lower electrode provided on a semiconductor substrate and a supporting film pattern for supporting the lower electrode, wherein a width of an upper portion of the lower electrode is smaller than a width of a lower portion of the lower electrode .

 As described above, the buffer memory 1440 is formed by forming a supporting film (NFC nitride film) on the insulating film, etching the supporting film and the insulating film to form holes, then forming the lower electrode in the hole, After the supporting film is patterned, the exposed insulating film is partially dipped out, then the exposed lower electrode is trimmed, and the remaining insulating film is fully dipped out, so that the height of the lower electrode ), And it has an effect of increasing Cs (capacitance) without adding manufacturing equipment or manufacturing process. This can improve the operating characteristics of the memory system 1400 including the buffer memory 1440, thereby enabling high performance of the memory system 1400.

In addition, the buffer memory 1440 of the present embodiment may include a static random access memory (SRAM) having dynamic characteristics, a dynamic random access memory (DRAM), a phase change random access memory (PRAM) having nonvolatile characteristics, A Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a magnetic random access memory (MRAM), and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (13)

A first lower electrode provided on a semiconductor substrate:
A second lower electrode provided on the first lower electrode; And
Wherein the width of the lower portion of the second lower electrode is smaller than the width of the upper portion of the first lower electrode. The method according to claim 1,
Wherein the first and second lower electrodes are pillar-shaped. The method according to claim 1,
Wherein the supporting film pattern comprises a nitride film. The method according to claim 1,
Wherein the support film pattern includes a shape of a rectangle, a rectangle, an annular shape, or a diamond shape. A first lower electrode provided on a semiconductor substrate:
A first supporting film pattern for supporting the first lower electrodes with each other;
A second lower electrode provided on the first lower electrode; And
Wherein a width of the lower portion of the second lower electrode is smaller than a width of an upper portion of the first lower electrode. The method of claim 5,
Wherein the first and second lower electrodes are pillar-shaped. The method of claim 5,
Wherein the first and second supporting film patterns comprise a nitride film. The method of claim 5,
Wherein the first and second supporting film patterns include a shape of a rectangle, a rectangle, an annular shape or a diamond shape. A lower electrode provided on a semiconductor substrate; And
And a supporting film pattern for supporting the lower electrode,
Wherein a thickness of the supporting film pattern connecting the lower electrode is formed to be larger than a thickness of the lower electrode in a region in contact with the supporting film pattern. The method of claim 9,
And the thickness of the lower electrode contacting the supporting film pattern is equal to the thickness of the supporting film pattern. The method of claim 9,
Wherein the lower electrode is a pillar shape. The method of claim 9,
Wherein the supporting film pattern comprises a nitride film. The method of claim 9,
Wherein the support film pattern includes a shape of a rectangle, a rectangle, an annular shape, or a diamond shape.

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