KR20150002006A - Liquid crystal display and method of driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof, capable of reducing power consumption. The liquid crystal display device according to the present invention includes a liquid crystal panel which realizes a moving picture and a still image, a gate driver which drives a gate line of the liquid crystal panel, a data driver which drives a data line of the liquid crystal panel, and a timing control unit which controls the gate driver and the data driver. The liquid crystal panel includes a first liquid crystal cell and a second liquid crystal cell which are formed at each of a plurality of sub pixel regions which are formed by the intersection of the gate line and the data line and are charged with data voltages of different polarities, a first thin film transistor which is connected to the first liquid crystal cell and has an oxide semiconductor layer, and a second thin film transistor which is connected to the second liquid crystal cell which is located in the same sub pixel region as the first liquid crystal cell and has the oxide semiconductor layer.

Description

Technical Field [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device capable of reducing power consumption and a driving method thereof.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, a liquid crystal display (LCD) device is attracting attention as a flat panel display device which can reduce weight and volume, which is a disadvantage of a cathode ray tube (CRT).

The liquid crystal display displays an image by adjusting the light transmittance of liquid crystal having dielectric anisotropy according to an electric field. Such a liquid crystal display device includes an active matrix type liquid crystal panel in which a thin film transistor is formed for each liquid crystal cell formed in an intersection of a gate line and a data line, a gate driver for driving a gate line of the liquid crystal panel, And a data driver for driving the data lines of the liquid crystal panel.

The image displayed on the liquid crystal panel is divided into a still image and a moving image. If the image displayed on the display panel is the same as the adjacent frame, it is determined that the image is a still image.

In the case of realizing a still image for a long period of time on a liquid crystal panel determined as a still image, the amorphous silicon forming the semiconductor layer of the liquid crystal panel has poor off current characteristics, and the same image data must be supplied to each liquid crystal panel every frame. There is a problem to be consumed.

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device and a method of driving the same that can reduce power consumption.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel for implementing moving images and still images; A gate driver for driving a gate line of the liquid crystal panel; A data driver for driving a data line of the liquid crystal panel; And a timing controller for controlling the gate driver and the data driver, wherein the liquid crystal panel is formed in each of a plurality of sub pixel areas provided at intersections of the gate line and the data line, 2 liquid crystal cell; A first thin film transistor connected to the first liquid crystal cell and having an oxide semiconductor layer; And a second thin film transistor connected to a second liquid crystal cell located in the same sub pixel area as the first liquid crystal cell and having the oxide semiconductor layer.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device including first and second liquid crystal cells formed in a plurality of sub pixel regions provided at intersections of a gate line and a data line, And a second thin film transistor connected to the second liquid crystal cell and having the oxide semiconductor layer, the second thin film transistor being connected to the first liquid crystal cell and including the oxide semiconductor layer Determining whether the image data to be displayed on the liquid crystal panel is a still image or a moving image; Filling the first and second liquid crystal cells with data voltages having different polarities and storing the data voltages to implement a moving picture; And storing the data voltage charged in the first and second liquid crystal cells to implement a still image when the still image is determined.

Wherein the first thin film transistor is connected to the odd-numbered data line and the gate line of the data line, the second thin film transistor is connected to the odd-numbered data line of the data line, And the first thin film transistor and the second thin film transistor are arranged in left and right or up and down directions in each sub pixel region.

Wherein the first liquid crystal cell comprises: a first pixel electrode connected to the first thin film transistor and supplied with a data voltage of either a positive polarity or a negative polarity; And a first common electrode that forms a horizontal, vertical, or fringing electric field with the first pixel electrode, wherein the second liquid crystal cell is connected to the second thin film transistor, and the other one of the positive polarity and the negative polarity is a data voltage A second pixel electrode to be supplied; And a second common electrode that forms a horizontal, vertical, or fringing electric field with the second pixel electrode.

Wherein a gate line voltage is supplied to the gate line of the liquid crystal panel and a common voltage is supplied to the first and second common electrodes while the liquid crystal panel implements the still image, Is turned off.

Wherein the liquid crystal panel is driven at a first frequency when implementing the still image and at a second frequency higher than the first frequency when implementing the moving image.

And the first and second thin film transistors are arranged in a zigzag pattern with respect to each of the data lines.

The present invention can reduce power consumption because the driving power of the system, the driving power of the data driver, and the driving power of the gate driver are turned off except for the gate low voltage and the common voltage during the still image period. In addition, since the first and second TFTs using an oxide semiconductor layer having a lower leakage current than the amorphous silicon can maintain the data signal charged in the liquid crystal cell during the still image period, the same luminance as the moving image can be maintained .

1 is a block diagram showing a liquid crystal display device according to the present invention.
2 is a driving waveform diagram of a liquid crystal display according to the present invention.
FIGS. 3A and 3B are views showing various embodiments of the liquid crystal panel shown in FIG. 1. FIG.
FIG. 4 is a view for explaining ON / OFF characteristics of the first and second thin film transistors shown in FIGS. 3A and 3B.
FIG. 5 is a view for explaining driving waveforms supplied to the first and second thin film transistors and the liquid crystal cell shown in FIGS. 3A and 3B.
FIG. 6 is a diagram illustrating the first and second thin film transistors shown in FIGS. 3A and 3B arranged in a DRD manner.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a liquid crystal display device according to the present invention.

1 includes a liquid crystal panel 102 for displaying an image, a gate driver 104 and a data driver 106 for driving the liquid crystal panel 102, a gate driver 104 and a data driver And a system 108 for supplying video data and a synchronization signal to the timing controller 108. The system controller 108 controls the timing controller 108 and the system controller 108,

The system 108 generates image data for an image to be displayed on the liquid crystal panel 102 and a plurality of synchronization signals DE, Hsync, Vsync, and CLK for controlling the timing controller 110, ).

Particularly, the system 108 includes a PSR signal generation unit 105 for generating a panel self refresh (PSR) signal by determining whether the image to be displayed on the liquid crystal panel 102 is a still image or a moving image, (118).

The PSR signal generation unit 118 compares the continuously input video data on a frame basis.

As a result of comparison, if the amount of change of the image data is less than a predetermined threshold value between the current frame and the previous frame, the PSR signal generation unit 118 generates a high-level PSR by judging the image of the current frame as a still image, . If it is determined that the image data of the current frame is still image data, the system 108 does not supply the image data of the input current frame to the timing controller 110, Power can be turned off and power consumption can be reduced.

If the amount of change of the image data between the current frame and the previous frame is equal to or greater than a predetermined threshold value, the PSR signal generation unit 118 generates a low-level PSR signal by determining the video of the current frame as a moving image, 110). When it is determined that the video data of the current frame is video data, the system 108 supplies the video data of the input current frame to the timing controller 110.

The timing controller 110 includes a control signal generator 112, a data aligner 114, and a frame memory 116.

The frame memory 116 stores image data input from the system 108 on a frame-by-frame basis.

The data sorting unit 114 arranges the image data stored in the frame memory 116 and supplies the sorted image data to the data driver 106.

The control signal generating unit 112 generates a gate control signal for controlling the gate driver 104 and a data control signal for controlling the data driver 106 by using a plurality of synchronization signals input through the system 108 do. The control signal generator 112 supplies the gate control signal to the gate driver 104 and the data control signal to the data driver 106 in response to the low level PSR signal. The control signal generator 112 stops the supply of the gate control signal, the data control signal, and the driving power in response to the high level PSR signal.

The gate driver 104 sequentially supplies the gate high voltage VGH to the gate line GL in response to the gate control signal from the timing controller 110 and supplies the gate off voltage VGL to the other periods . Particularly, the gate driver 104 supplies the gate high voltage VGH and the gate low voltage VGL to the gate line GL during the period in which the low level PSR signal is supplied as shown in FIG. 2, The supply of the gate high voltage VGH to the gate line GL is interrupted and the gate low voltage VGL is supplied only during the period in which the PSR signal of the gate line GL is supplied. The gate driver 104 may be located in the liquid crystal panel using a driving transistor formed in the same process as the thin film transistor formed in the liquid crystal panel 102.

The data driver 106 converts the digital image data into the analog data voltage using the data control signal and the gamma voltage from the timing controller 110 and supplies the changed data voltage to the data line DL. That is, the data driver 106 supplies the data voltage to the data line DL at the first frequency because all the driving power sources (for example, VDD and VSS) are continuously supplied while the low level PSR signal is supplied. The data driver 106 can not supply the data voltage to the data line DL because the driving power source (e.g., VDD, VSS) is not supplied while the PSR signal of the high level is supplied. In consideration of the leakage current of the thin film transistor formed in the liquid crystal panel 102, the data driver 106 applies a low-level PSR signal to the data line DL every 30 seconds to several minutes And may supply the data voltage at the second frequency.

The liquid crystal panel 102 has a plurality of sub pixel regions located at intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm. First and second liquid crystal cells Clc1 and Clc2 and first and second thin film transistors T1 and T2 are formed in the plurality of sub pixel regions, respectively, as shown in FIGS. 3A and 3B.

The gate lines GL1 to GLn supply gate signals to the gate electrodes of the first and second thin film transistors T1 and T2, respectively, as shown in Figs. 3A and 3B.

The data lines DL1 to DLm are formed to cross the gate lines GL1 to GLn to form a sub pixel region. The odd-numbered data lines DL1, DL3, ..., DLi among the data lines DL supply a first data signal to the source electrode of the first thin-film transistor T1, DL2, DL4, ..., DLj supply the second data signal to the source electrode of the second thin film transistor T2.

The first thin film transistor T1 is charged in the first pixel electrode 122a with the first data signal supplied to the odd-numbered data line DLi in response to the gate high voltage VGH supplied to the gate line GL . To this end, the first thin film transistor T1 includes a gate electrode connected to the gate line GL, a source electrode connected to the odd-numbered data line DLi, a drain electrode connected to the first pixel electrode 122a, And an oxide semiconductor layer for forming a channel between the source and drain electrodes.

The second thin film transistor T2 supplies a second data signal supplied to the odd data line DLj to the second pixel electrode 122b in response to the gate high voltage VGH supplied to the gate line GL . To this end, the second thin film transistor T2 includes a gate electrode connected to the gate line GL, a source electrode connected to the even-numbered data line DLj, a drain electrode connected to the second pixel electrode 122b, And an oxide semiconductor layer for forming a channel between the source and drain electrodes.

The first and second thin film transistors T1 and T2 form a channel as an oxide semiconductor layer. As shown in FIG. 4, the first and second thin film transistors T1 and T2 having an oxide semiconductor layer have a lower off current than a thin film transistor formed of amorphous silicon as a channel layer. Accordingly, the first and second thin film transistors T1 and T2 can maintain the data signal charged in the liquid crystal cells C1c1 and Clc2 during the still image interval during which the data signal is not supplied to the liquid crystal panel 102. [

The first and second liquid crystal cells Clc1 and Clc2 are formed in each sub pixel region.

The first liquid crystal cell Clc1 forms a vertical electric field, a horizontal electric field or a fringe electric field with the first pixel electrode 122a connected to the first thin film transistor T1 and the first pixel electrode 122a with the liquid crystal interposed therebetween And a first common electrode 124a. In the first liquid crystal cell Clc1, a voltage equal to the difference between the common voltage Vcom and the data signal having the positive polarity (negative polarity) is applied, and the liquid crystal is driven according to the applied voltage to adjust the light transmittance, The display unit 102 displays an image.

The second liquid crystal cell Clc2 forms a vertical electric field, a horizontal electric field or a fringe electric field with the second pixel electrode 122b connected to the second thin film transistor T1 and the second pixel electrode 122b with the liquid crystal interposed therebetween And a second common electrode 124b. The second liquid crystal cell Clc2 is applied with a voltage equal to the data voltage of the common voltage Vcom and negative (positive polarity), and drives the liquid crystal according to the applied voltage to adjust the light transmittance, 102) displays an image.

The gate high voltage VGH and the gate low voltage VGL are applied to the gate line GL and the data voltage Vdd is applied to the odd and even data lines DLi and DLj while the moving picture is implemented in the liquid crystal panel 102. [ The common voltage Vcom is supplied to the first and second common electrodes 124a and 124b. The first and second liquid crystal cells Clc1 and Clc2 are connected to the data voltages supplied to the pixel electrodes 122a and 122b through the data lines DLi and DLj and the thin film transistors T1 and T2, And a common voltage supplied to the second common electrodes 124a and 124b to drive the liquid crystal to display a moving image.

Also, while the still image is implemented in the liquid crystal panel 102, only the gate low voltage is supplied to the gate line GL and only the common voltage is supplied to the first and second common electrodes 124a and 124b. Accordingly, the first and second thin film transistors T1 and T2 having the oxide semiconductor layer maintain the charged data voltage in the moving picture implementation, so that the first and second liquid crystal cells Clc1 and Clc2 are in the first and second The liquid crystal is driven according to a voltage equal to the difference between the common voltage supplied to the common electrodes 124a and 124b and the data voltage to display a still image.

On the other hand, when the still image is implemented for a long period of time, positive charges are accumulated in the liquid crystal cell to which the positive data voltage is supplied, and negative charges are accumulated in the liquid crystal cell to which the negative data voltage is supplied. Therefore, in the present invention, as shown in FIG. 5, the positive (high-potential) data voltage (voltage) of the odd-numbered data line DLi is applied to the first pixel electrode 122a of the first liquid crystal cell Clc1, (Low potential) data voltage of the even-numbered data line DLj is supplied to the second pixel electrode 122b of the second liquid crystal cell Clc2. When the negative (low potential) data voltage of the odd-numbered data line DLi is supplied to the first pixel electrode 122a of the first liquid crystal cell Clc1, the second liquid crystal cell Clc2 is supplied with the negative (High-potential) data voltage of the even-numbered data line DLj is supplied to the odd-numbered data line DLj. Accordingly, even when the still image is implemented for a long period of time, the present invention compensates for both positive (negative) charges accumulated in the first liquid crystal cell Clc1 and positive (positive) charges accumulated in the second liquid crystal cell Clc2, Can be prevented.

3A and 3B, since two data lines DLi and DLj are required to drive two thin film transistors T1 and T2 for each sub-pixel, the data driver 106 The number of data integrated circuits to be formed becomes larger than in the prior art. Thus, as shown in FIG. 6, a double-rate driving (DRD) method is used in which the first and second thin film transistors T1 and T2 are arranged in a staggered manner with respect to each data line DL Thereby reducing the number of data integration circuits.

As described above, according to the present invention, the driving power of the system 108 excluding the gate low voltage (VGL) and the common voltage (Vcom), and the driving of the data driver 106 during the supply of the high level PSR signal, The driving power of the power source and gate driver 104 is turned off, so that power consumption can be reduced. In addition, the first and second thin film transistors T1 and T2 using an oxide semiconductor layer having a lower leakage current than the amorphous silicon during the supply of the high level PSR signal, that is, during the still image period, are connected to the liquid crystal cells C1c1 and Clc2 Since the charged data signal can be maintained as it is, it is possible to maintain the same luminance as the moving picture period.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

102: liquid crystal panel 104: gate driver
106: data driver 108: system
110: timing control unit 112: control signal generating unit
114: data sorting unit 116: frame memory
118: PSR signal generator

Claims (11)

A liquid crystal panel for implementing a moving image and a still image;
A gate driver for driving a gate line of the liquid crystal panel;
A data driver for driving a data line of the liquid crystal panel;
And a timing controller for controlling the gate driver and the data driver,
The liquid crystal panel
First and second liquid crystal cells formed in each of a plurality of sub pixel regions provided at intersections of the gate lines and the data lines and charged with data voltages of different polarities;
A first thin film transistor connected to the first liquid crystal cell and having an oxide semiconductor layer;
And a second thin film transistor connected to a second liquid crystal cell located in the same sub pixel area as the first liquid crystal cell and having the oxide semiconductor layer. The method according to claim 1,
Wherein the first thin film transistor is connected to the odd-numbered data line and the gate line of the data line,
The second thin film transistor has a second thin film transistor connected to the odd data line among the data lines and connected to the same gate line as the first thin film transistor,
Wherein the first and second thin film transistors are arranged in left and right or up and down directions in each sub pixel region. 3. The method of claim 2,
The first liquid crystal cell
A first pixel electrode connected to the first thin film transistor and supplied with a data voltage of either a positive polarity or a negative polarity;
And a first common electrode that forms a horizontal, vertical, or fringing electric field with the first pixel electrode,
The second liquid crystal cell
A second pixel electrode connected to the second thin film transistor and supplied with the other one of the positive polarity and the negative polarity;
And a second common electrode which forms a horizontal, vertical, or fringing electric field with the second pixel electrode. The method of claim 3,
Wherein a gate line voltage is supplied to the gate line of the liquid crystal panel and a common voltage is supplied to the first and second common electrodes while the liquid crystal panel implements the still image, Is turned off. The method according to claim 1,
Wherein the liquid crystal panel is driven at a first frequency when implementing the still image and at a second frequency higher than the first frequency when implementing the moving image. The method according to claim 1,
Wherein the first and second thin film transistors are arranged in a zigzag pattern with respect to each of the data lines. A first thin film transistor connected to the first liquid crystal cell and having an oxide semiconductor layer; and a second thin film transistor connected to the first liquid crystal cell and the second liquid crystal cell, Determining whether the image data to be displayed on the liquid crystal panel including the second thin film transistor connected to the second liquid crystal cell located in the same sub pixel region and having the oxide semiconductor layer is a still image or a moving image;
Filling the first and second liquid crystal cells with data voltages having different polarities and storing the data voltages to implement a moving picture;
And when the moving image is determined to be the still image, generating a still image by maintaining a data voltage charged in the first and second liquid crystal cells when the moving image is implemented. 8. The method of claim 7,
Wherein the first thin film transistor is connected to the odd-numbered data line and the gate line of the data line,
The second thin film transistor has a second thin film transistor connected to the odd data line among the data lines and connected to the same gate line as the first thin film transistor,
Wherein the first and second thin film transistors are arranged in the left-right direction or the up-down direction in each sub pixel region. 9. The method of claim 8,
The first liquid crystal cell
A first pixel electrode connected to the first thin film transistor and supplied with a data voltage of either a positive polarity or a negative polarity;
And a first common electrode that forms a horizontal, vertical, or fringing electric field with the first pixel electrode,
The second liquid crystal cell
A second pixel electrode connected to the second thin film transistor and supplied with the other one of the positive polarity and the negative polarity;
And a second common electrode that forms a horizontal, vertical, or fringing electric field with the second pixel electrode. 10. The method of claim 9,
Wherein a gate line voltage is supplied to the gate line of the liquid crystal panel and a common voltage is supplied to the first and second common electrodes while the liquid crystal panel implements the still image, Is turned off. ≪ Desc / Clms Page number 19 > 8. The method of claim 7,
Wherein the liquid crystal panel is driven at a first frequency when implementing the still image and at a second frequency higher than the first frequency when implementing the moving image.

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