KR20140138523A - Optical input/output device and optical electronic system having the same - Google Patents

Optical input/output device and optical electronic system having the same Download PDF

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KR20140138523A
KR20140138523A KR1020130099082A KR20130099082A KR20140138523A KR 20140138523 A KR20140138523 A KR 20140138523A KR 1020130099082 A KR1020130099082 A KR 1020130099082A KR 20130099082 A KR20130099082 A KR 20130099082A KR 20140138523 A KR20140138523 A KR 20140138523A
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South Korea
Prior art keywords
light source
optical
silicon substrate
vertical
type light
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KR1020130099082A
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Korean (ko)
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KR102031953B1 (en
Inventor
김경옥
박현대
김인규
김상훈
장기석
김상기
주지호
최용석
권혁제
박재규
김선애
오진혁
곽명준
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한국전자통신연구원
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Priority to US14/062,454 priority Critical patent/US9690042B2/en
Publication of KR20140138523A publication Critical patent/KR20140138523A/en
Priority to US15/607,726 priority patent/US10168474B2/en
Priority to US15/607,717 priority patent/US10466413B2/en
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Publication of KR102031953B1 publication Critical patent/KR102031953B1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12007—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind forming wavelength selective elements, e.g. multiplexer, demultiplexer
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Optical Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)

Abstract

The present invention relates to an optical I/O device and an optical electronic system including the same. The device includes: a bulk silicon substrate; a vertical incidence type photo-detecting element which is integrated on a side of the bult silicon substrate; and a vertical output light source element integrated on the other side of the bulk silicon substrate adjacent to the vertical incidence type photo-detecting element. The vertical output light source element can include an III-V group chemical semiconductor light source activating layer which is coupled to the silicon substrate through wafer bonding.

Description

TECHNICAL FIELD [0001] The present invention relates to an optical input / output device and an optical electronic system having the optical input /

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a photo input / output device and an optoelectronic system including the same.

Semiconductor devices such as CPU, memory, and logic circuitry of a computer can be integrated on a silicon substrate in large part. Semiconductor chips composed of such integrated circuits send and receive signals through metal wiring. However, such an interconnection method using metal wiring has many problems such as signal processing speed of semiconductor devices, heat generated in proportion to cumulative use time, and crosstalk. Accordingly, there is a demand for data optical communication between chips based on silicon photonics technology, or data communication within the chip, as a solution to the problem of high performance and high speed of a computing system, a large-capacity optical communication system, and an image processing system. In response to these demands, researches on silicon photonics for optical interconnection at a silicon chip level are being actively developed.

Generally, silicon optical communication devices that are developed and developed by silicon photonics technology are not the conventional bulk silicon substrates that implement general CMOS integrated circuits, but optical waveguide type silicon photonics devices using SOI (silicon on insulator) substrates are mainstream have. Silicon optical interconnections based on these optical waveguide type silicon photonics devices are being sought. However, such an SOI substrate is more expensive than a bulk silicon substrate. This is because the SOI substrate must be formed with a buried oxide (BOX) layer near the surface of the silicon substrate through several additional steps in its fabrication. Due to the crystal defects in the substrate due to the BOX layer formation step, the performance of SOI-based electronic devices is lower than that of conventional well-established bulk silicon based devices. Furthermore, in the fabrication of SOI-based optoelectronic fusing chips, there is a lot of additional effort and additional cost due to the change of the manufacturing process of the electronic integrated circuit to the SOI substrate-based technology. The same applies to the case where the optical waveguide type silicon photonics device is integrated on the SOI portion formed locally on the bulk silicon substrate. Additional processes such as high temperature heat treatment are required in the process of forming the local SOI on the bulk silicon substrate, which may affect the performance of the integrated circuit formed on the bulk silicon substrate. The optical waveguide type silicon photonics device itself formed in the local SOI portion also has disadvantages such as high optical loss and low performance.

And the light source for silicon optical I / O is based on a III-V compound semiconductor light source. The integration of the light source based on the silicon photonics is performed by a hybrid laser method, a die-bonding packaging method, or a PCB module packaging method. The hybrid laser method is a method of wafer-bonding a light source based on an optical waveguide such as III-V compound semiconductor DFB LD to a SOI substrate. The die bonding packaging method is a mounting method in which a III-V compound semiconductor DFB LD chip is flip-chip bonded to an SOI-based silicon photonics chip. Both hybrid laser and die-bonding packaging methods must basically use expensive SOI substrates. Therefore, the conventional optical input / output device has a disadvantage that productivity is low.

Thus, in order for silicon photonics devices to be used practically in silicon integrated circuits, all electronic circuits, optical components, need to be implemented on the same bulk silicon substrate. This requires optical I / O devices and optical interconnect schemes that can deliver the benefits of high performance, high speed, high efficiency, high functionality, low cost, and low packaging costs

It is an object of the present invention to provide an optoelectronic system in which the optical communication elements are monolithically integrated on a bulk silicon substrate and / or have it.

Another object of the present invention is to provide an optical input / output device capable of improving productivity and / or an optical electronic system having the same.

The present invention provides a light input / output device. The apparatus includes a bulk silicon substrate; At least one vertical incidence type photodetecting device integrated on one side of the bulk silicon substrate; And at least one vertical output type light source element which is integrated on the other side of the bulk silicon substrate adjacent to the vertical incident type light detecting element, wherein the vertical output type light source element is formed by wafer bonding, Lt; RTI ID = 0.0 > III-V < / RTI > compound semiconductor light source active layer.

For example, the vertical incidence type photodetecting device includes germanium.

For example, the vertical incidence type photodetecting device includes a Ge1-xSix / Ge1-ySiy superlattice (0? X, y? 1), a germanium-based quantum dot or a quantum wire array, or a silicon photodiode.

For example, the vertical output type light source device includes a surface emitting laser or a surface emitting light emitting diode.

For example, the light emitting device further includes a protection layer on the vertical output type light source device and the vertical incidence type light detection device.

In one example, the protective layer comprises silicon oxide.

In one example, the protective layer has holes exposing the vertical output type light source element and the vertical incidence type light detecting element, and the apparatus further includes a light via formed in the holes.

In one example, the optical via comprises silicon nitride.

In one example, the apparatus further comprises a horizontal optical waveguide provided on the protective layer and coupled to the optical via.

In one example, the apparatus further comprises an optical passive circuit provided on the protection layer and including an optical MUX / DEMUX, an optical switch, or a grating coupler, coupled to the horizontal optical waveguide.

In one example, the apparatus further includes a single integrated CMOS interface circuit electrically connected to the vertical input type light detecting element or the vertical output type light source element and on the bulk silicon substrate.

The apparatus includes a bulk silicon substrate; At least one vertical incidence type light detecting element formed in a single integrated manner on one side of the bulk silicon substrate; And at least one vertical output type light source element mounted on the other side of the bulk silicon substrate by die bonding via a III-V group compound semiconductor substrate.

For example, the vertical output type light source device includes a III-V group compound semiconductor light source active layer.

The present invention provides an optoelectronic system. The system includes a bulk silicon substrate; A signal processing device integrated on the bulk silicon substrate; And a plurality of signal processing chips connected to the signal processing device and having an optical input / output device having a single vertical incidence type light detecting element array and a vertical output type light source element array on the bulk silicon substrate, Wherein the plurality of signal processing chips are stacked in a three-dimensional manner, and the vertical incidence type photodetection error and the vertical output type light source array of each of the plurality of signal processing chips are arranged to face each other one-to-one, And is optically connected in three dimensions.

For example, the vertical output type light source element array includes a III-V compound semiconductor active layer bonded on the bulk silicon substrate by wafer bonding.

In one example, the signal processing apparatus includes a CPU, a memory, a data bus interface circuit, a peripheral control device, a user-defined ASIC, or an optical communication circuit.

As described above, the optical input / output device according to the embodiment of the present invention includes single integrated vertical incident light detecting elements and vertical output light source elements (for example, surface emitting laser or surface emitting LED). The vertically incident type photodetecting devices may include a germanium photodiode grown from a bulk silicon substrate. The vertical output type light source elements may include a III-V group compound semiconductor layer bonded on a bulk silicon substrate by wafer bonding. Vertically incident light sensing elements and wafer bonded vertical output light source elements can be single integrated on a bulk silicon substrate. Further, the optical input / output device may include passive optical device circuits such as optical vias on the vertically incident type light detecting devices and the vertical output type light source devices, and WDM devices based on optical waveguides. Therefore, the optical input / output device and the optical electronic system including the optical input / output device according to the embodiment of the present invention provide a structure of a high performance / high performance photoelectric fusion chip system for silicon optical communication and interconnection based on a bulk silicon substrate, Can be improved.

Figs. 1A and 1B are plan views showing an optoelectronic system according to a first embodiment of the present invention.
Figs. 2 and 3 are cross-sectional views taken along line II 'of Figs. 1A and 1B.
4 is a plan view showing an optoelectronic system according to a second embodiment of the present invention.
5 is a cross-sectional view taken along line II-II 'of FIG.
FIGS. 6 and 7 are cross-sectional views taken along line III-III 'of FIG.
8 and 9 are respectively a cross-sectional view and an exploded perspective view showing an optoelectronic system according to a third embodiment of the present invention.
FIGS. 10 to 17 are process sectional views showing a manufacturing method of an optoelectronic system according to the first embodiment.
18A and 18B are plan views showing an optical electronic system according to a fourth embodiment of the present invention.
19 is a cross-sectional view taken along the line IV-IV 'in Figs. 18A and 18B.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' do not exclude the presence or addition of one or more other elements, steps, operations and / or components, elements, steps, operations and / .

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Figs. 1A and 1B are plan views showing an optoelectronic system according to a first embodiment of the present invention. 2 is a cross-sectional view taken along the line I-I 'in Figs. 1A and 1B.

Referring to FIGS. 1A, 1B, and 2, the optical electronic system according to the first embodiment of the present invention includes a signal processing apparatus 100 integrated on a bulk silicon substrate 10, (200). The signal processing apparatus 100 can calculate and control an input / output signal of the optical input / The signal processing apparatus 100 may include at least one signal processing sub-apparatus 110-150. The signal processing subdevices may include a CPU, a memory, an ASIC, a data bus interface circuit, a peripheral control device, a user defined ASIC, or a block of an optical communication circuit. The present invention is not limited thereto. For example, the signal processing apparatus 100 may include a CPU area, a memory area, an ASIC area, a data bus interface circuit area, a peripheral control device area, a user defined ASIC area, or an optical communication circuit area And < RTI ID = 0.0 > a < / RTI >

The optical input / output device 200 may replace an existing electrical signal input / output device. The optical input / output device 200 may be monolithically integrated into the bulk silicon substrate 10. The light input / output device 200 may include vertical incidence type light detecting elements 210, vertical light emitting (surface emitting type) light source elements 220, and a CMOS interface circuit 230. The vertical incidence type light detecting elements 210 are light receiving units and the vertical emitting type (surface emitting type) light source elements 220 are light transmitting units. Vertical emission type light source elements 220 may include a surface emitting laser 220A or a surface emitting light emitting diode (LED) 220B. The normal-incidence type light detecting elements 210 may include a photodiode having a light-absorbing layer of germanium-on-silicon (Ge-on-Si). The 100% germanium-on-silicon vertical incidence type light detecting elements 210 can absorb light in a wavelength band of 650 nm to 1600 nm.

The present invention is not limited thereto and can be variously changed and changed. For example, the vertical incidence type photodetecting elements 210 may include a Ge 1 - x Si x / Ge 1 - y Si y superlattice (0 ≤ x, y ≤ 1) or a germanium based quantum dot or quantum line array structure Of photodiodes. Alternatively, the vertical incidence type light detecting elements 210 may include a silicon photodiode. In such cases, the light wavelength may be in a wavelength band shorter than 650 nm.

Vertical emission type light source elements 220 may include a light source active layer of a III-V semiconductor bonded by wafer bonding. Vertical emission type light source elements 220 can be integrated into a single bulk silicon substrate 10. The vertical emission type light source devices 220 may be a vertical waveguide-based (VCSEL) or a surface-emitting distributed feedback laser (VFD) laser. Surface emitting lasers. The vertically-emitting light source elements 220 and the bulk silicon substrate 10 can be bonded together by the adhesive layer 20. [ The adhesive layer 20 may include an oxide film or an adhesive material. According to one example, the adhesive layer 20 may have a thickness of several nanometers to several hundreds of nanometers. The adhesive layer 20 may mean a silicon oxide film for wafer bonding. Since the bulk silicon substrate 10 is relatively inexpensive as compared with the conventional SOI substrate, the compatibility can be very high.

The vertical incidence type light detecting elements 210 and the vertical light emitting elements 220 may constitute a vertical input / output array. The CMOS interface circuit 230 may interface between the signal processing apparatus 100 and the vertically incident light detecting elements 210 or between the signal processing apparatus 100 and the vertically emitting light source elements 220 . The CMOS interface circuit 230 includes a transimpedance amplifier (TIA) 232, a light source driver 234, a limiting amplifier (LA) 236, a serialize / Deserialize circuit, a clock-data-recovery (CDR) circuit, a PLL circuit, or a protocol integrated circuit.

The vertical emission type light source elements 220 can output light in the 480 nm band, the 650 nm band, the 780 nm band, the 850 nm band, the 980 nm band, the 1310 nm band, or the 1550 nm band. When a wavelength in each band is configured using a combination of different light sources, a WDM function can be added. When a wafer-bonded VCSEL having a wavelength of 850 nm is applied, a multi-mode fiber 50 having low optical coupling loss may be used. When a wafer-bonded VCSEL having a 650 nm wavelength band is applied, inexpensive plastic optical fibers (POF) 50 can be used.

The first passivation layer 30 may be provided on the vertical incidence type light detecting elements 210 and the vertically emitting type light source elements 220. The first passivation layer 30 may include a silicon oxide film. The optical fibers 50 may be formed on the first passivation layer 30 and connected to the vertical incidence type light detecting elements 210 and the vertical light emitting elements 220.

FIG. 3 shows another example of the optical input / output device 200 based on FIG. 3, the optical input / output device 200 is configured to include the optical fibers 50 between the vertically incident type photodetecting elements 210 and the optical fibers 50, or between the vertically emitting type light source elements 220 and the optical fibers 50. [ Vias 40 may be included. The optical vias 40 are formed between the first protection layer 30 between the vertically incident type photodetecting elements 210 and the optical fibers 50 or between the vertically emitting type light source elements 220 and the optical fibers 50. [ As shown in FIG.

The light vias 40 may comprise silicon nitride (Si x N y ). For example, x = 3 and y = 4. The refractive index of the silicon nitride film may be about 2. The refractive index of the first protective layer 30 may be about 1.537. The light vias 40 can guide light vertically. The optical vias 40 can improve the optical coupling efficiency between the optical fibers 50 and the normal incidence type photodetector elements 210. [ The optical vias 50 can improve the optical coupling efficiency between the optical fibers 60 and the vertical emission type light source elements 220. The present invention is not limited thereto and can be variously changed and changed.

The optical input / output device 200 of FIG. 3 includes a protection layer 220 between the vertical incidence type light detecting elements 210 and the optical fibers 50 of FIG. 2 or between the vertically emitting type light source elements 220 and the optical fibers 50 And optical vias 40 are added to the optical fiber 30.

4 shows an optical electronic system according to a second embodiment of the present invention. 5 shows a cross section of the optical input / output device 200 taken along line II-II 'of FIG. 6 and 7 show a junction cross section of the optical via 40 and the optical waveguide 60 of the optical input / output device 200 taken along line III-III 'of FIG. 4. In the first embodiment and The description of the similar configuration is omitted, and the difference is mainly described.

4 to 7, the optical vias 40 of the optical input / output device 200 may be connected to a plurality of horizontal optical waveguides 60. The horizontal optical waveguides 60 and the optical vias 40 may be optically coupled by a connecting method such as a grating coupler 74 or a 45 ° tilting mirror surface 76. The grating coupler 74 and the 45 o inclined mirror surface 76 may be replaced with each other.

The horizontal optical waveguides 60 optically coupled to the vertical emission type light source elements 220 may be coupled to the optical MUX 70. The optical MUX 70 can output optical signals of a plurality of wavelengths provided from the vertically-emitted light source elements 220 integrated under the optical multiplexer 70 to a single horizontal optical waveguide 62. The horizontal optical waveguides 60 optically coupled to the vertical incidence type light detecting elements 210 may be coupled to a dielectric-based optical DEMUX 72. The optical DEMUX 72 can divide the optical signal input to the single horizontal optical waveguide 62 into a plurality of wavelength signals and separately provide the optical signals to the vertical incidence type photodetector elements 210. Passive optical device circuits such as a plurality of horizontal optical waveguides 60, a single horizontal optical waveguide 62 and an optical MUX 70 / DEMUX 72 are formed in the second passivation layer 80. The third passivation layer 90 may cover the passive photonic device circuits and the second passivation layer 80. [ Passive optical device circuits such as a plurality of horizontal optical waveguides 60, a single horizontal optical waveguide 62, and optical MUX 70 / DEMUX 72 may include silicon nitride. The second passivation layer 80 and the third passivation layer 90 may include a silicon oxide layer.

A horizontal optical waveguide 60, a grating coupler 74, a WDM element, and a waveguide element are formed on the single-crystal vertical incidence type light detecting elements 210 and the vertically-emitting type light source elements 220 on the bulk silicon substrate 10, Optical functional dielectric layers, such as optical switches, or functional passive optical circuitry, can be single integrated. Therefore, the optoelectronic system according to the second embodiment of the present invention can provide a high performance / high performance photoelectric fusion chip system.

8 and 9 show an optical electronic system according to a third embodiment of the present invention. The description of the configuration similar to that of the first embodiment is omitted, and the differences are mainly described.

8 and 9, an optoelectronic system according to a third embodiment of the present invention is a three-dimensional stacked multi-chip system in which efficient chip-to- -chip) optical interconnections. For example, the signal processing chips 101-106 may be connected to the CPU 101, the memory 102, the peripheral control device 103, the ASIC 104, the data bus interface 105, and the optical communication circuit 106 .

Each of the signal processing chips 101 to 106 includes first to fifth light detecting elements 211 to 215 which are integrated into the first to fifth bulk silicon substrates 12, 14, 16, 18 and 19, Elements 221-225. For example, on the first bulk silicon substrate 12, the first vertical incidence type photodetecting elements 211 and the first vertical emitting type light source elements 221 may be integrated into an array. The second vertical incidence type photodetecting devices 212 and the second vertical emitting type light source devices 222 may be integrated into an array on the second bulk silicon substrate 14. [ On the third bulk silicon substrate 16, the third vertical incidence type photodetecting elements 213 and the second vertical emitting type light source elements 223 can be integrated into an array. On the fourth bulk silicon substrate 18, the fourth vertical incidence type photodetecting elements 214 and the fourth vertically emitting type light source elements 224 can be integrated into an array. The fifth vertical incidence type photodetecting elements 215 and the fifth vertical emitting type light source elements 225 may be integrated into an array on the fifth bulk silicon substrate 19 in a single manner.

The optical signal can be three-dimensionally transmitted between the first to fifth light detecting elements 211 to 215 and the light source elements 221 to 225. The first vertical incidence type light source elements 221 and the second vertical incidence type light detection elements 212 may be disposed between the first vertical incidence type light detecting elements 211 and the second vertical direction light emitting elements 222, The optical signal can be transmitted. The fourth protective film 32 and the fifth protective film 34 are formed between the first vertical incidence type light detecting elements 211 and the second vertical emitting type light source elements 222 and between the first vertical incidence type light source elements 222 221) and the second vertical incidence type photodetector elements 212. The first vertical incidence type photodetector elements 212 may be disposed between the first vertical incidence type photodetector elements 221 and the second vertical incidence type photodetector elements 212. [

Similarly, the second through fifth vertical incidence type light detecting elements 212, 213, 214, 215 and the second through fifth vertical light emitting elements 222, 223, 224, (Light source element-light detection element) so as to face each other in a contiguous manner. In addition, the sixth to eighth protective films 34, 38, 39 may be provided. Accordingly, the plurality of signal processing chips can be optically coupled three-dimensionally.

FIGS. 10 to 17 are process sectional views showing a manufacturing method of an optoelectronic system according to the first embodiment.

Referring to FIG. 10, a bulk silicon substrate 10 is provided. The step of providing the bulk silicon substrate 10 may include a manufacturing process of the signal processing device 100 and the CMOS interface circuit 230 of FIG.

Referring to FIGS. 1 and 11, a single vertical integration type light detecting element 210 is integrated on one side of a bulk silicon substrate 10. The normal-incidence type photodetecting elements 210 may include a vertically-incident germanium-on-silicon (Ge-on-Si) photodiode grown from the surface of the bulk silicon substrate 10. Germanium can be epitaxially grown on the bulk silicon substrate 10. [ The vertical incidence type light detecting elements 210 may be integrated together with the signal processing apparatus 100 and the CMOS interface circuit 230 in a batch process. The present invention is not limited thereto and can be variously changed and changed. For example, the vertical incident type photodetecting device 210 is Ge 1 formed on a bulk silicon substrate (10) - x Si x / Ge 1 - y Si y superlattice, germanium-based quantum dot or quantum picture of the line array structure A diode, or a silicon photodiode.

Referring to FIGS. 1 and 12, a single integrated vertical incidence type light detecting elements 210, a CMOS interface circuit 230, and a signal processing apparatus 100 are mounted on one side of a bulk silicon substrate 10, Layer 31, and then the wafer 290 is bonded to the other side of the bulk silicon substrate 10. Then, The device protection layer 31 may cover the vertical incidence type photodetecting elements 210. The wafer 290 may include a III-V compound semiconductor substrate 280 and a III-V compound semiconductor light source active layer 270 on the semiconductor substrate 280. The III-V compound semiconductor substrate 280, which is a dummy substrate, may include a substrate such as gallium arsenide, indium phosphide, or gallium nitride. The III-V compound semiconductor light source active layer 270 may be bonded to the bulk silicon substrate 10 using the adhesive layer 20 or may be wafer bonded to the bulk silicon substrate 10. The adhesive layer 20 may include a silicon oxide film or an adhesive material. The adhesive layer 20 may mean a silicon oxide film for wafer bonding.

Referring to FIG. 13, the III-V compound semiconductor substrate 280 as a dummy substrate is removed. The III-V compound semiconductor substrate 280 may be removed by an etching process. The device protection layer 31 may protect the vertical incidence type photodetecting devices 210 from the etching gas or etching solution when the III-V compound semiconductor substrate 280 is removed.

Referring to FIGS. 1 and 14, vertical emission type light source elements (for example, surface emitting lasers) 220 are formed by patterning a group III-V compound semiconductor light source active layer 270. The patterning process of the III-V group compound semiconductor light source active layer 270 may include a plurality of photolithography processes and an etching process. The device protection layer 31 may protect the vertical incidence type photodetector elements 210 during the patterning process of the III-V group compound semiconductor light source active layer 270. When the patterning of the III-V compound semiconductor light source active layer 270 is completed, the electrodes of the vertical emission type light source elements 220 and the electrodes of the vertical incident light detection elements 210 are connected to the CMOS interface circuit 230 (Not shown) and can be electrically connected to each other. Vertical emission type light source elements 220 may have a height of several tens to several tens of micrometers and a width of several tens to several thousands of micrometers 2 depending on the type. The vertical emission type light source elements 220 and the vertical incidence type light detection elements 210 can be integrated on a single bulk silicon substrate 10 that is inexpensive compared to a conventional SOI substrate. Further, since the present invention is based on a conventional bulk silicon CMOS process, optical I / O introduction of a photoelectric fusion type silicon chip is possible with a minimum additional process / additional cost. The present invention has the advantages of high efficiency, high speed, low power, high performance, high functionality, low productivity, and high efficiency packaging. The present invention can greatly simplify the photoelectric fusion IC composition as a whole. The present invention provides a practical optical I / O and optical interconnection scheme for silicon chip-to-chip optical communication and provides a favorable structure for inter-chip optical interconnection in three-dimensionally stacked chips.

Referring to FIG. 15, a first passivation layer 30 is formed on the vertically incident light-sensing elements 210 and the vertically-ejecting light-source elements 220. The first passivation layer 30 may include a silicon oxide film formed by a chemical vapor deposition method or an atomic layer deposition method. Here, the first passivation layer 30 may include a device protection layer 31. The device protection layer 31 protects the normal incidence type photodetecting devices 210, but the first protection layer 30 may have a light guiding property. The device protection layer 31 may be formed in plurality when the vertical incidence type light detecting elements 210 are formed. The first passivation layer 30 protects the vertical incidence type photodetectors 210 and the vertical emission type light source elements 220 as well as the vertical incidence type photodetector elements 210 and the vertical emission type light source elements 220. [ The light guide 220 may be a light guide. The present invention is not limited thereto and can be variously changed and changed. For example, the first passivation layer 30 may be formed on the bulk silicon substrate 10 after removal of the device protection layer 31.

Referring to FIG. 16, the first passivation layer 30 is locally etched to form holes 42 exposing the vertically incident light-detecting elements 210 and the vertically-emitting light-source elements 220. Holes 42 can be formed by a photolithography process and an etching process. The etching process of the first passivation layer 30 may include a dry etching process.

Referring to FIG. 17, optical vias 40 are formed in holes 42. The optical vias 40 may comprise a silicon nitride film formed by a chemical vapor deposition process or an atomic layer deposition process.

18A and 18B show the optical input / output device 200 according to the fourth embodiment of the present invention. 19 is a cross-sectional view taken along the line IV-IV 'in Figs. 18A and 18B. The description of the configuration similar to that of the first embodiment is omitted, and the differences are mainly described.

18A, 18B, and 19, the optical input / output device 200 according to the fourth embodiment of the present invention includes a bulk silicon substrate 10 on which monomoleically integrated vertically incident type photodetecting elements 210 are integrated The chip die 260 can be mounted by a die bonding method. The chip die 260 may include a III-V compound semiconductor substrate 280 and vertically-emitted light source elements 220 on the III-V compound semiconductor substrate 280. Vertical emission type light source elements 220 may be formed from a III-V group compound semiconductor light source active layer.

Although not shown, the vertically-emitting light source elements 220 are electrically connected to the bulk silicon substrate 10 or the CMOS interface circuit 230, for example, as surface emitting lasers by wire bonding or flip chip bump bonding . The fourth embodiment includes the III-V group compound semiconductor substrate 280 in which the vertical-discharge-type light source elements 220 in the first embodiment are mounted.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (19)

Bulk silicon substrate;
At least one vertical incidence type photodetecting device integrated on one side of the bulk silicon substrate; And
And at least one vertical output light source element that is integrated on the other side of the bulk silicon substrate adjacent to the vertical incidence type light detecting element,
Wherein the vertical output type light source element is bonded onto the bulk silicon substrate by wafer bonding to include a single integrated III-V compound semiconductor light source active layer. The method according to claim 1,
Wherein the vertical incidence type photodetecting device comprises germanium. The method according to claim 1,
The vertical incident type photodetecting device is Ge 1 - x Si x / Ge 1 - y Si y superlattice (0≤x, y≤1), light including a quantum dot or quantum wire array, or a silicon germanium-based photodiode of the Input / output device. The method according to claim 1,
Wherein the vertical output type light source element includes a surface emitting laser or a surface emitting light emitting diode. The method according to claim 1,
And a protective layer on the vertical output type light source device and the vertical incidence type photodetecting device. 6. The method of claim 5,
Wherein the protective layer comprises silicon oxide. 6. The method of claim 5,
Wherein the passivation layer further comprises light vias formed in the holes, the holes having holes exposing the vertical output type light source element and the vertical incidence type light detecting element. 8. The method of claim 7,
Wherein the optical vias include silicon nitride. 9. The method of claim 8,
And a horizontal optical waveguide provided on the protective layer and coupled to the optical vias. 10. The method of claim 9,
Further comprising an optical passive circuit provided on the protection layer and including an optical MUX / DEMUX, an optical switch, or a grating coupler, the optical passive circuit being coupled to the horizontal optical waveguide. The method according to claim 1,
Further comprising a single integrated CMOS interface circuit electrically connected to the vertical input photodetecting device or the vertical output type light source device and on the bulk silicon substrate. 12. The method of claim 11,
Wherein the CMOS interface circuit comprises a transimpedance amplifier, a light source driver limiting amplifier, a serializer / digitizer circuit, a PLL circuit, a clock data recovery circuit, or a protocol integrated circuit. Bulk silicon substrate; A signal processing device integrated on the bulk silicon substrate; And a plurality of signal processing chips connected to the signal processing device, the signal processing chips having a light input / output device having a single vertical incidence type light detecting element array and a vertical output type light source element array on the bulk silicon substrate,
Wherein the plurality of signal processing chips are stacked in a three-dimensional manner, the vertical incidence type photodetection array and the vertical output type light source array of each of the signal processing chips are arranged to face each other one-by-one, Optically coupled optically dimensionally. 14. The method of claim 13,
Wherein the vertical output type light source element array includes a III-V compound semiconductor active layer bonded on the bulk silicon substrate by wafer bonding. 14. The method of claim 13,
Wherein the signal processing device comprises a CPU, a memory, a data bus interface circuit, a peripheral control device, a user defined ASIC, or an optical communication circuit. Bulk silicon substrate;
At least one vertical incidence type light detecting element formed in a single integrated manner on one side of the bulk silicon substrate; And
And at least one vertical output type light source element mounted on the other side of the bulk silicon substrate by die bonding via a III-V group compound semiconductor substrate. 17. The method of claim 16,
Wherein the vertical output type light source element comprises a III-V group compound semiconductor light source active layer. Providing a bulk silicon substrate;
Forming a vertical incidence type light detecting element on one side of the bulk silicon substrate in a single integrated manner; And
And forming a vertical output type light source device on the other side of the bulk silicon substrate in a single integrated manner,
The forming of the vertical output type light source device comprises:
Forming a device protection layer covering the vertical incidence type photodetecting device on one side of the bulk silicon substrate;
Bonding a wafer including a III-V semiconductor substrate and a III-V semiconductor light source active layer on the III-V semiconductor substrate to the other side of the bulk silicon substrate;
Removing the III-V semiconductor substrate;
Forming the surface emitting laser or the surface emitting light emitting diode by patterning the III-V semiconductor light source active layer; And
And forming a protective layer on the vertical incidence type light detecting element and the vertical output type light source element. 19. The method of claim 18,
Etching the passivation layer to form holes that expose the vertical incidence type photodetecting device and the vertical output type light source device;
Forming light vias in the holes;
Bonding the horizontal optical waveguides coupled to the optical via on the protective layer; And
And forming on the protection layer an optical passive circuit coupled to the horizontal optical waveguide and including an optical MUX / DEMUX, an optical switch, or a grating coupler.
KR1020130099082A 2013-05-23 2013-08-21 Optical input/output device and optical electronic system having the same KR102031953B1 (en)

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US15/607,726 US10168474B2 (en) 2013-05-23 2017-05-30 Method of manufacturing optical input/output device
US15/607,717 US10466413B2 (en) 2013-05-23 2017-05-30 Opto-electronic system including optical input/output device

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US20030022414A1 (en) * 2001-07-25 2003-01-30 Motorola, Inc. Structure and method for fabricating anopto-electronic device having an electrochromic switch
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