KR20140135588A - Thin film Transistor - Google Patents

Thin film Transistor Download PDF

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Publication number
KR20140135588A
KR20140135588A KR20130127995A KR20130127995A KR20140135588A KR 20140135588 A KR20140135588 A KR 20140135588A KR 20130127995 A KR20130127995 A KR 20130127995A KR 20130127995 A KR20130127995 A KR 20130127995A KR 20140135588 A KR20140135588 A KR 20140135588A
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KR
South Korea
Prior art keywords
conductive layer
forming
gate electrode
layer
substrate
Prior art date
Application number
KR20130127995A
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Korean (ko)
Inventor
조성행
박상희
황치선
Original Assignee
한국전자통신연구원
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Publication of KR20140135588A publication Critical patent/KR20140135588A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention provides a method of manufacturing a thin film transistor. The method of manufacturing a thin film transistor includes forming a gate electrode on a substrate, forming a gate insulating film on the substrate on which the gate electrode is formed, forming a first conductive layer on the gate insulating film, Forming a second conductive layer on the first conductive layer; forming a second conductive layer on the second conductive layer; forming a second conductive layer on the first conductive layer, Forming a first photoresist pattern comprising a second region having a second thickness that is less than one thickness; etching the first and second conductive layers using the first photoresist pattern; Removing the resist in the second region while leaving the resist in the first region to form a second photoresist pattern; Etching the second conductive layer using a photoresist pattern, applying a negative type resist on the substrate, exposing the back side to remove the negative type resist on the gate electrode, Etching the first conductive layer; forming an oxide semiconductor layer on the gate insulating film on the gate electrode; forming a protective layer on the substrate on which the oxide semiconductor layer is formed; Lt; / RTI >

Description

Thin film transistor

The present invention relates to a thin film transistor, and more particularly, to an oxide thin film transistor.

Recently, the direction of display development is focusing on large-area high-definition TV, 3D TV, non-glasses TV, large AMOLED, high-resolution tablet PC and flexible display. In accordance with the development direction of such a display, the characteristics of a thin film transistor as a driving element are also required to be gradually adapted to drive a high-resolution, large-area display. In addition to high-end specifications, displays are also increasingly demanding price competitiveness. Therefore, a thin film transistor which can be manufactured at a large area at a low cost is required

SUMMARY OF THE INVENTION The present invention provides a method of fabricating an oxide thin film transistor in which a channel is formed by self-alignment to minimize parasitic storage capacitance.

It is another object of the present invention to provide a method of manufacturing an oxide thin film transistor that simplifies a process by simultaneously forming a source line / drain bus line and a display pixel electrode, eliminates cross-talk, and increases an aperture ratio.

A manufacturing method of a thin film transistor for solving the above-mentioned technical problems is presented.

A method of manufacturing a thin film transistor according to an embodiment of the present invention includes forming a gate electrode on a substrate, forming a gate insulating film on the substrate on which the gate electrode is formed, forming a first conductive layer on the gate insulating film Forming a second conductive layer on the first conductive layer; a first region having a first thickness in a source region on one side of the gate electrode on the second conductive layer; Forming a first photoresist pattern in a drain region of the first photoresist pattern, the first photoresist pattern including a second region having a second thickness that is thinner than the first thickness; Etching the layer, removing the resist in the second region while leaving the resist in the first region to form a second photoresist pattern , Etching the second conductive layer using the second photoresist pattern, applying a negative resist on the substrate, exposing the back surface to remove the negative type resist on the gate electrode, Etching the first conductive layer on the gate electrode; forming an oxide semiconductor layer on the gate insulating film on the gate electrode; forming a protective layer on the substrate on which the oxide semiconductor layer is formed; And forming a flat layer on the layer.

A method of fabricating a thin film transistor according to an embodiment of the present invention may be self-aligned with a source / drain electrode by back exposure using a gate electrode as a mask. As a result, the RC delay problem can be reduced.

In addition, a method of manufacturing a thin film transistor according to an embodiment of the present invention uses a source / drain electrode as a transparent oxide electrode. As a result, it is possible to improve the uniformity of the thin film transistor and the bonding property with the semiconductor layer.

In addition, the method of manufacturing a thin film transistor according to an embodiment of the present invention can simplify the process because the layer for strengthening the bonding strength with the Cu diffusion barrier layer is formed by itself when the source / drain electrode is formed.

1 to 20 are cross-sectional views illustrating a process of forming a thin film transistor structure according to an embodiment of the present invention.

Hereinafter, a method of forming a thin film transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages of the present invention and its advantages over the prior art will become apparent from the detailed description and claims that follow. In particular, the invention is well pointed out and distinctly claimed in the claims. The invention, however, may best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. Like reference numerals in the drawings denote like elements throughout the various figures

Hereinafter, a thin film transistor structure according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 to 20 are cross-sectional views illustrating a method of forming a thin film transistor structure according to an embodiment of the present invention.

Referring to FIG. 1, a substrate 110 may be prepared. The substrate 110 may include a transparent substrate. For example, the substrate 110 may include a glass substrate for producing a display element, plastic, or the like.

A gate electrode 120 and a wiring 122 may be formed on the substrate 110. [ The gate electrode 120 and the wiring 122 may be formed on the substrate through a deposition process such as sputtering. Forming the gate electrode 120 and the wiring 122 may include supplying a conductive material on the substrate 110. [ For example, the conductive material may include any one of aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (W), chromium (Cr), and platinum (Pt). The gate electrode 120 and the wiring 122 can be patterned by a photolithography process and an etching process.

Referring to FIG. 2, a gate insulating layer 130 may be formed on a substrate 110 having a gate electrode 120 formed thereon. The gate insulating layer 130 may be an aluminum insulating layer, a silicon nitride layer (SiNx), or a silicon oxide layer (SiOx). The aluminum insulator is deposited by atomic layer deposition (ALD) and can be formed by heat treatment at 600 ° C or less. The aluminum insulator film by ALD method has the most stable characteristics of the thin film transistor in the 300 ° C heat treatment process. Alternatively, the aluminum insulating film may be formed by a PECVD or MOCVD method. A silicon nitride film (SiNx) or a silicon oxide film (SiOx) can be formed by a PECVD method. PECVD method 450 o C or less.

Referring to FIG. 3, a first conductive layer 140 may be formed on the gate insulating layer 130.

The first conductive layer 140 may be formed through a deposition process such as sputtering. The first conductive layer 140 may include any one of ITO (Indium Tin Oxide), IZO (Indium Tin Oxide), ITZO (Indium Tin Zinc Oxide), AZO (Aluminum Zinc Oxide), and GZO .

Referring to FIG. 4, a second conductive layer 150 may be formed on the first conductive layer 140. The second conductive layer 150 may be formed through a deposition process such as sputtering. The second conductive layer 150 may be formed of any one of copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), aluminum-nickel alloy (Al-Ni), Cu alloy, Mo alloy, .

Referring to FIG. 5, a first photoresist 210 may be applied on the second conductive layer. The first photoresist 210 may be a positive type photoresist.

Referring to FIG. 6, the first photoresist 210 may be selectively irradiated with light through the halftone mask 310. The halftone mask 310 may include a first region S1, a second region S2, and a third region S3. The first area S1 may be a non-transmissive area, the second area S2 may be a semi-transmissive area, and the third area S3 may be a transmissive area. The first region S1 may overlap the source region on one side of the gate electrode 120. [ The second region S2 may overlap the drain region on the other side of the gate electrode 120 and the gate electrode 120. [

Referring to FIG. 7, a first photoresist 210 exposed through a halftone mask 310 is developed. A first pattern 210a having a first thickness and a second pattern 210b having a second thickness that is thinner than the first thickness may remain in the first region S1 and the second region S2. The first photoresist 210 may be completely removed to expose the surface of the second conductive layer 150 in the third region S3.

Referring to FIG. 8, the first conductive layer 140 and the second conductive layer 150 may be selectively etched using the first pattern 210a and the second pattern 210b as a mask. The etch may be wet etch, dry etch, or ion-milling.

Referring to FIG. 9, the ashing process may be performed to remove a portion of the first pattern 210a and the second pattern 210b. The ashing process may utilize an oxygen plasma. The second pattern 210b can be completely removed. The first pattern 210a may be the removed third pattern 210a 'by the thickness of the second pattern 210b. The third pattern 210a 'remains only in the first region S1.

Referring to FIG. 10, the second conductive layer 150 may be selectively etched using the third pattern 210 'as a mask. The etch may be wet etch, dry etch, or ion-milling. The data pad 152 remaining only under the third pattern 210 'may be formed. The data pad 152 may be formed of any one of copper, molybdenum, aluminum, titanium, aluminum-nickel alloy (Al-Ni), Cu alloy, The RC delay problem can be reduced.

Referring to FIG. 11, a second photoresist 215 may be applied to the entire surface of the substrate 110 by spin-coating or spin-coating. The second photoresist 215 may be a negative type photoresist.

Referring to FIGS. 12 and 13, a fourth pattern 215a may be formed in which the second photoresist 215 of the portion overlapping the gate electrode is removed by performing a back-side exposure process.

Referring to FIG. 14, the first conductive layer 140 may be selectively etched using the fourth pattern 215a as a mask. The etch may be wet etch, dry etch, or ion-milling. The first conductive layer 140 superimposed on the gate electrode 120 may be removed to form the source electrode 142 and the drain electrode 144 that are self-aligned. Since the source electrode 142 and the drain electrode 144 do not overlap with the bottom gate electrode 144, the RC delay problem can be reduced. The source electrode 142 and the drain electrode 144 may be formed of any one of ITO (Indium Tin Oxide), IZO (Indium Tin Oxide), ITZO (Indium Tin Zinc Oxide), AZO (Aluminum Zinc Oxide), and GZO It is possible to improve the uniformity of the thin film transistor and to improve the junction characteristics with the oxide semiconductor layer.

Referring to FIG. 15, the third pattern 210a 'and the fourth pattern 215a may be removed through a lift-off process. A data pad 152, a source electrode 142, a drain electrode 144 facing the source electrode, and a pixel electrode (not shown) extending from the drain electrode on the first region S1 may be connected. The pixel electrode, the source electrode 142, and the drain electrode 144 may be formed of the same material. The pixel electrode and the source electrode 142 and the drain electrode 144 can be formed of the same material, so that the process can be simplified. A pixel signal may be supplied to the source electrode 142 through the data pad 152. [

Referring to FIG. 16, an oxide semiconductor layer 160 may be formed on a substrate 110. The oxide semiconductor layer 160 may be deposited by a deposition process such as MOCVD or sputtering. As the oxide semiconductor layer 160, a zinc oxide based material may be used. For example, the oxide semiconductor layer 160 may include InZnO or GaInZnO. Here, the composition ratio of Ga, In, and Zn may be 1: 1: 1 or 2: 2: 1.

Referring to FIG. 17, a third photoresist may be applied on the substrate 110 through spin-less coating or spin-coating. The third photoresist may be a positive type photoresist. The third photoresist may be exposed and developed through a photolithography process to form a fifth pattern 220 on the gate electrode 120.

Referring to FIG. 18, the oxide semiconductor layer 160 may be selectively etched using the fifth pattern 220 as a mask. The etch may be wet etch, dry etch, or ion-milling. The etched oxide semiconductor layer 160 may overlap both sides of the source electrode 142 and the drain electrode 144. Since the oxide semiconductor layer 160 is overlapped with the source electrode 142 and the drain electrode 144, a self-aligned element having a short channel can be stably realized.

Referring to FIG. 19, a protective layer 170 may be formed on a substrate 110. The protective layer 170 may be formed of an insulating film such as aluminum oxide (AlOx), silicon nitride (SiNx), or silicon oxide (SiOx). The protective layer 170 may have a thickness of 10 to 400 nm. The protective layer 170 may be formed to protect the oxide semiconductor layer 160 from etching or the like.

Referring to FIG. 20, an interlayer insulating layer 200 is formed on a substrate 110. The interlayer insulating film 200 has contacts 230 in openings that expose the wiring 122 and the data pad 152.

It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

Claims (1)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate on which the gate electrode is formed;
Forming a first conductive layer on the gate insulating layer;
Forming a second conductive layer on the first conductive layer;
A first region having a first thickness at a source region on one side of the gate electrode on the second conductive layer, a second region having a second thickness thinner than the first thickness in the gate electrode and a drain region on the other side of the gate electrode, Forming a first photoresist pattern including the first photoresist pattern;
Etching the first conductive layer and the second conductive layer using the first photoresist pattern;
Removing the resist in the second region while leaving the resist in the first region to form a second photoresist pattern;
Etching the second conductive layer using the second photoresist pattern;
Applying a negative type resist on the substrate;
Removing the negative type resist on the gate electrode by back exposure;
Etching the first conductive layer on the gate electrode;
Forming an oxide semiconductor layer on the gate insulating film on the gate electrode;
Forming a protective layer on the substrate on which the oxide semiconductor layer is formed;
And forming a flat layer on the protective layer.
KR20130127995A 2013-05-16 2013-10-25 Thin film Transistor KR20140135588A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020130055882 2013-05-16
KR20130055882 2013-05-16

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KR20140135588A true KR20140135588A (en) 2014-11-26

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