KR20140135402A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

A semiconductor memory device and an operating method thereof according to an embodiment of the present invention stably maintain a cell current by performing the erase operation of pipe cells and prevent a disturbance phenomenon due to the degradation of the pipe cell by the repetition of a program operation.

Description

≪ Desc / Clms Page number 1 > Semiconductor memory device and operating method thereof &

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic apparatus, and more particularly, to a semiconductor memory device and a method of operating the semiconductor memory device.

Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

Volatile memory devices have fast write and read speeds, but stored data is lost when the power supply is interrupted. A non-volatile memory device maintains stored data even if the write and read rates are relatively slow, but the power supply is interrupted. Therefore, a nonvolatile memory device is used to store data to be maintained regardless of power supply. A nonvolatile memory device includes a ROM (Read Only Memory), an MROM (Mask ROM), a PROM (Programmable ROM), an EPROM (Erasable Programmable ROM), an EEPROM (Electrically Erasable Programmable ROM), a Flash memory, Random Access Memory (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). Flash memory is divided into NOR type and NOR type.

Flash memory has the advantages of RAM, which is free to program and erase data, and ROM, which can save stored data even when power supply is cut off. Flash memories are widely used as storage media for portable electronic devices such as digital cameras, PDAs (Personal Digital Assistants) and MP3 players.

In order to increase the degree of integration of the memory, the size of the memory device must be reduced. There are limitations in reducing the size of the memory device due to reasons such as semiconductor materials and process conditions. Recently, a method of manufacturing a memory element in a three-dimensional structure has been proposed. In a semiconductor memory device having a three-dimensional structure, since cell current is reduced, it is desirable to stably maintain the cell current.

An embodiment of the present invention provides a semiconductor memory device capable of stably maintaining a cell current and a method of operating the semiconductor memory device.

A semiconductor memory device according to an embodiment of the present invention includes a pipe cell and memory cells arranged in series between the bit line and the pipe cell in the vertical direction from the pipe cell and between the source line and the pipe cell, A memory string having a channel layer made of a two-dimensional structure, and a peripheral circuit configured to perform an erase operation of the pipe cell.

A method of operating a semiconductor memory device in accordance with an embodiment of the present invention includes a pipeline cell and memory cells arranged in series between the bit line and the pipeline cell in the vertical direction from the pipeline cell and between the source line and the pipeline cell, Providing a memory string having a channel layer of a three-dimensional structure that is shaped like a column, and performing an erase operation of the pipe cell.

The semiconductor memory device and the method of operating the semiconductor memory device according to the embodiment of the present invention can stably maintain the cell current by performing the erase operation of the pipe cells, The phenomenon can be solved. Therefore, data reliability can be improved.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
2 is a circuit diagram for explaining a memory string included in the memory block shown in FIG.
3 is a perspective view illustrating a structure of a memory block implementing the circuit of FIG.
4 is a cross-sectional view illustrating the operation of the memory string shown in FIG.
5 is a waveform diagram for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.
6 is a waveform diagram for explaining a method of operating a semiconductor memory device according to another embodiment of the present invention.
7 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.
8 is a block diagram briefly showing a fusion memory device or a fusion memory system that performs program operation in accordance with various embodiments described above.
9 is a block diagram briefly showing a computing system including a flash memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention. 2 is a circuit diagram for explaining a memory string included in the memory block shown in FIG.

The semiconductor memory device according to the embodiment of the present invention performs the erase operation and the erase verify operation of the memory array 110 including the plurality of memory blocks 110MB, the memory cells included in the selected page of the memory block, Gt; PERI < / RTI > The peripheral circuit PERI includes a control circuit 120, a voltage supply circuit 130, a page buffer group 140, a column selection circuit 150, and an input / output circuit 160.

The memory block includes memory strings. Each memory string has a channel layer comprising a U-shaped three-dimensional structure including memory cells arranged in series between the bit line and the pipe cell and between the source line and the pipe cell in the vertical direction from the pipe cell and the pipe cell.

2, a general memory string includes a drain select transistor DST having a drain connected to the bit line BL, a source select transistor SST having a source connected to the source line SL, And a plurality of memory cells (C1 to C8) connected in series between the source and the drain of the memory cell array. Here, the number of memory cells may be changed according to the design, and a case where eight memory cells are described below will be described as an example.

A pipe cell PC is connected between a pair of memory cells C4 and C5 located in the middle of the memory string of the three-dimensional structure. Accordingly, some memory cells (C1 to C4) of the memory cells (C1 to C8) included in the memory string are connected in series between the source select transistor (SST) and the pipe cell (PC) to constitute a first memory group, The remaining memory cells C5 to C8 are connected in series between the drain select transistor DST and the pipe cell PC to constitute a second memory group.

A pipe cell (PC) is formed on the substrate. The drain select transistor DST and the memory cells C1 to C4 of the first memory group are arranged in series between the bit line BL and the pipe cell PC in the vertical direction from the substrate. The source select transistor SST and the memory cells C5 to C8 of the second memory group are arranged in series between the source line SL and the pipe cell PC in the vertical direction from the substrate. The number of memory cells (C1 to C4) in the first memory group and the number of memory cells (C5 to C8) in the second memory group are preferably the same. As the memory cells C1 to C8 are arranged vertically, the channel direction of the memory cells C1 to C8 is perpendicular to the substrate. As the memory cells C1 to C8 of the memory string are divided into the first and second memory groups, one string includes two vertical channel layers vertical from the substrate.

The pipe cell PC has the same structure as the memory cells C1 to C8 and has a channel region of the memory cells C1 to C4 of the first memory group and a channel region of the memory cells C5 to C8 of the second memory group Thereby electrically connecting the regions.

The peripheral circuit PERI is configured to supply a hot hole to the channel layer to perform an erase operation of the memory cells and the pipe cells.

The control circuit 120 outputs a voltage control signal VCON for generating a voltage necessary for performing an erase operation and an erase verify operation in response to a command signal CMD input from the outside through the input / output circuit 160 And outputs a PB control signal PBCON for controlling the page buffers PB1 to PBk included in the page buffer group 140 according to the type of operation. The control circuit 120 also outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD input from the outside through the input / output circuit 160. [

The control circuit 120 includes a counter 122 to count the number of times the erase operation of the memory cells is performed. In one embodiment, the control circuit 120 outputs a voltage control signal VCON and a PB control signal PBCON to perform an erase operation of the pipe cells in the erase operation of the memory cells. Specifically, the control circuit 120 may output a voltage control signal VCON and a PB control signal PBCON to reduce the threshold voltage of the memory cells and decrease the threshold voltage of the pipe cells after a first time has elapsed . In another embodiment, the control circuit 120 outputs the voltage control signal VCON and the PB control signal PBCON to perform the erase operation of the pipe cells based on the number of times of performing the erase operation of the memory cells. Specifically, the control circuit 120 may output the voltage control signal VCON and the PB control signal PBCON so as to perform the erase operation of the pipe cells when the number of times of performing the erase operation of the memory cells reaches the preset number of times.

The voltage supply circuit 130 responds to the voltage control signal VCON of the control circuit 120 to supply the operating voltages Vop necessary for erasing the memory cells and the pipe cells to the drain select line DSL, To the local lines including the word lines WL1 to WL8, the pipe gate PG, the source select line SSL and the source line SL.

Specifically, the voltage supply circuit 130 applies a voltage to the source line SL in a state where the word lines WL1 to WL8 of the memory cells and the pipe gate PG of the pipe cell are floated to supply the hot holes to the channel layer, Supply voltage is applied. The voltage supply circuit 130 discharges the word lines WL1 to WL8 after applying the erase voltage to the source line SL when the hot holes are supplied to the channel layer, PG). In another embodiment, when the hot holes are supplied to the channel layer, the voltage supply circuit 130 discharges the pipe gate PG after applying the erase voltage to the source line SL. The voltage supply circuit 130 includes a voltage generation circuit and a row decoder.

The voltage generation circuit outputs the operating voltages required for the erase operation and the erase verify operation of the memory cells and the pipe cells to the global lines in response to the voltage control signal VCON of the control circuit 120.

The row decoder responds to the row address signals RADD of the control circuit 120 so that the operating voltages output to the global lines in the voltage generating circuit are applied to the local lines DSL, WL1 of the selected memory block in the memory array 110 WL1 to WL8, PG, SSL, and SL so that they can be transferred to the global lines WL1 to WL8, PG, SSL, and SL.

The page buffer group 140 includes a plurality of page buffers connected to the memory array 110 via the bit lines BL. The page buffers of the page buffer group 140 respond to the PB control signal PBCON of the control circuit 120 to store the bit lines BL in accordance with the data inputted to store the data in the memory cells C1 to C8. Selectively precharges or senses the voltage of the bit lines BL to read data from the memory cells C1 to C8. The page buffer group 140 transmits the number of times of performing the erase operation (CS) of the memory cells to the control circuit 120.

The column selection circuit 150 selects the page buffers included in the page buffer group 140 in response to the column address signal CADD output from the control circuit 120. That is, the column selection circuit 150 sequentially transfers the data to be stored in the memory cells to the page buffers in response to the column address signal CADD. In addition, page buffers are sequentially selected in response to a column address signal (CADD) so that data of memory cells latched in page buffers can be output to the outside by a read operation.

The input / output circuit 160 transmits data to the column selection circuit 150 under the control of the control circuit 120 in order to input data inputted from the outside into the page buffer group 140 for storage in memory cells during a program operation do. The column selection circuit 150 transfers the data transferred from the input / output circuit 160 to the page buffers of the page buffer group 140 according to the above-described method, and the page buffers store the input data in the internal latch circuits. In addition, during the read operation, the input / output circuit 160 outputs data transferred from the page buffers of the page buffer group 140 through the column selection circuit 150 to the outside.

The structure of the semiconductor device including the three-dimensional memory string will now be described in more detail.

3 is a perspective view illustrating a structure of a memory block implementing the circuit of FIG. 3 is a perspective view of a memory block included in the memory array of the semiconductor memory device. The memory block includes 6 * 2 respective memory strings (MS), a source select transistor (SST) and a drain select transistor (DST) .

Referring to FIG. 3, a plurality of memory strings (MS) are provided in a memory block. Each memory string MS includes a plurality of electrically rewritable memory cells C1 to C8, and the memory cells C1 to C8 are connected in series. The memory cells C1 to C8 constituting the memory string MS are formed by stacking a plurality of semiconductor layers. Each memory string MS includes a channel layer SC, word lines WL1-WL8, and a pipe gate PG. The channel layer SC may have a U-shaped three-dimensional structure and may be formed of a polysilicon layer doped with a pentavalent impurity.

The U-shaped channel layer SC is formed in a U shape when viewed in the row direction. The U-shaped channel layer SC has a pair of columnar portions extending in a substantially perpendicular direction to the semiconductor substrate Ba and a connecting portion JP formed to connect the lower ends of the columnar portions CLa and CLb . The columnar portions (CLa, CLb) may be cylindrical columns or each of the molds. The columnar portions CLa and CLb may be columnar. Here, the row direction is a direction perpendicular to the stacking direction, and the column direction described later is a direction perpendicular to the stacking direction and the row direction.

The U-shaped channel layer SC is arranged such that the lines connecting the central axes of the pair of columnar portions CLa and CLb are parallel to the column direction. In addition, the U-shaped channel layer SC is arranged to form a matrix in a plane formed in the row direction and the column direction.

The word lines WL1 to WL8 of each layer extend in parallel to the row direction. The word lines WL1 to WL8 of each layer are repeatedly formed with lines which are insulated and separated from each other and have a predetermined pitch in the column direction. The word line WL1 is formed on the same layer as the word line WL8. Similarly, the word line WL2 is formed in the same layer as the word line WL7, the word line WL3 is formed in the same layer as the word line WL6, and the word line WL4 is formed in the same layer as the word line WL5 do.

The gates of the memory cells C1 to C8 provided at the same position in the column direction and forming a line in the row direction are connected to the same word lines WL1 to WL8, respectively. Although not shown, the end portions in the row direction of each of the word lines WL1 to WL8 are formed in a stepped shape. Each of the word lines WL1 to WL8 is formed so as to surround a plurality of columnar portions arranged in a row in the row direction.

An oxide-nitride-oxide (ONO) layer (not shown) is formed between the word lines WL1 to WL8 and the columnar portions CLa and CLb. The ONO layer includes a tunnel insulating layer adjacent to the columnar portions CLa and CLb, a charge storage layer adjacent to the tunnel insulating layer, and a blocking insulating layer adjacent to the charge storage layer. The charge storage layer functions to accumulate charges like a conventional floating gate. In other words, the charge storage layer is formed so as to surround the entire surfaces of the columnar portions CLa and CLb and the connection portion JP, and the word lines WL1 to WL8 are formed to surround the charge storage layer .

The drain select transistor DST includes a pillar-form channel layer CLa and a drain select line DSL. The columnar channel layer CLa is formed so as to extend in the direction perpendicular to the substrate Ba.

The drain select line DSL is provided above the uppermost word line WL8 of the word lines. The drain select line DSL has a shape extending parallel to the row direction. The drain select line DSL may be repeatedly formed with lines having a predetermined pitch alternating in the column direction so as to sandwich the source select line SSL therebetween. The drain select line DSL is formed so as to surround each of a plurality of columnar channel layers CLa in a line in the row with a gap interposed therebetween.

The source select transistor SST includes a pillar-form channel layer SLb and a source select line SSL. The source select line SSL is provided above the most significant word line WL1 of the word lines. The source select line SSL has a shape extending in parallel to the row direction. The source select line SSL may be repeatedly formed with lines having a predetermined pitch in the column direction so as to sandwich the drain select line DSL therebetween. The source select line SSL is formed so as to surround each of the plurality of columnar channel layers CLb in a line in the row with a gap interposed therebetween.

The pipe gate PG is formed so as to extend two-dimensionally in the row direction and the column direction so as to cover the lower portion of the plurality of connection parts JP.

The columnar channel layers CLb are formed adjacent to each other in the column direction. The upper ends of the pair of columnar channel layers CLb are connected to the source line SL. The source line SL is connected in common to the pair of pillar channel layers CLb.

The bit lines BL may be formed at the upper end of the columnar channel layers CLa and may be connected to the columnar channel layers CLa via the plug PL. Each bit line BL is formed to be arranged above the source line SL. Each bit line BL is repeatedly formed in lines extending in the column direction and having a predetermined interval in the row direction.

In the memory string structure of the two-dimensional structure, when a high voltage of about 20 V is applied to the P well in the erase operation, electrons stored in the floating gate of the memory cells due to a high voltage difference between the P well and the floating gate are discharged to the P well, It was erased. However, in the memory string of the three-dimensional structure, an erasing operation is performed in another method.

4 is a cross-sectional view illustrating the operation of the memory string shown in FIG.

Referring to FIG. 4, a tunnel insulating layer Tox, a charge storage layer CT, and a block insulating layer Box are formed between the word lines WL1 to WL8 and the channel layer SC, An ONO layer is formed. The charge storage layer CT may be formed of a nitride film.

On the other hand, since there is not enough charge in the channel layer SC and high potential difference can not be generated, it is difficult to erase the memory cells by discharging electrons trapped in the charge storage layer CT. When a sufficient time has elapsed, a hole-pair may be formed and electrons of the charge storage layer (CT) may be emitted. However, the time required for several seconds or more is required,

In order to solve such a problem, when a gate induced drain leakage (GIDL) phenomenon is generated by regulating the voltage applied to the source line SL and the source select line SSL, a sufficient hot hole is introduced, And as a result, electrons of the charge storage layer CT may be emitted to erase the memory cells.

5 is a waveform diagram for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.

An operation method of a semiconductor memory device according to an embodiment of the present invention performs an erase operation of a pipe cell in an erase operation of memory cells.

Referring to FIG. 5, a hot hole supplying operation is performed in the sections T1 to T2. The voltage supply circuit sets the word lines WL to the floating state and applies the ground voltage to the source select line SSL. When the hot-hole supply voltage V1 is applied to the source line SL, the hot holes h are supplied to the channel layer SC by the GIDL current. The potential of the bit line BL rises by the hot holes h. The voltage supply circuit applies a ground voltage to the drain select line (DSL) and the pipe gate (PG).

When the hot holes h are injected into the channel layer SC, the threshold voltages of the memory cells and the pipe cells in the period T3 to T9 are reduced. In the period T3 to T4, the control circuit controls the voltage supply circuit such that the source select line SSL is in the floating state and the erase voltage V2 is applied to the source line SL. When the erase voltage V2 is applied, the voltages of the source select line SSL and the word lines WL1 to WL8 in the floating state rise due to the capacitor coupling phenomenon. The control circuit controls the voltage supply circuit such that the drain select line (DSL) and the pipe gate (PG) are in a floating state.

Subsequently, when the voltage supply circuit discharges (e.g., ground voltage) the word lines WL1 to WL8 during the period T5 to T6, the voltage difference between the word lines WL1 to WL8 and the channel layer SC becomes sufficiently large And the electrons trapped in the charge storage layer CT of the word lines WL1 to WL8 are emitted to the channel layer SC.

Subsequently, when the voltage supply circuit discharges the pipe gate PG (for example, ground voltage) during the period T7 to T8, the voltage difference between the pipe gate PG and the channel layer SC increases sufficiently so that the pipe gate Electrons trapped in the charge storage layer CT of the charge storage layer PG are emitted to the channel layer SC.

Thereafter, the supply of the erase voltage V2 is stopped in the period T9, and the erase operation is completed.

As described above, the pipe cell PC has the same structure as the memory cells. Therefore, as the number of times of performing the program operation of the memory cells increases, the number of electrons trapped in the charge storage layer CT of the pipe cell increases and the threshold voltage of the pipe cell rises. However, unlike the memory cells, since the erase operation is not performed on the pipe cell PC, there is a greater possibility that problems occur due to deterioration of the pipe cell PC as the number of program operation times is increased. Therefore, in the method of operating the semiconductor memory device according to an embodiment of the present invention, the erase operation of the pipe cell is performed during the erase operation of the memory cells to reduce the threshold voltage of the pipe cell, And the cell current can be sufficiently secured.

6 is a waveform diagram for explaining a method of operating a semiconductor memory device according to another embodiment of the present invention.

A method of operating a semiconductor memory device according to another embodiment of the present invention counts the number of times of performing an erase operation of memory cells and performs an erase operation of a pipe cell when the counted number of erase operations reaches a set number of times.

Referring to FIG. 6, a hot hole supplying operation is performed in the sections T1 to T2. The voltage supply circuit sets the word lines WL and the pipe gate PG to the floating state and applies the ground voltage to the source select line SSL. When the hot-hole supply voltage V1 is applied to the source line SL, the hot holes h are supplied to the channel layer SC by the GIDL current. The potential of the bit line BL rises by the hot holes h. The voltage supply circuit applies a ground voltage to the drain select line (DSL).

When the hot holes h are injected into the channel layer SC, the threshold voltage of the pipe cell decreases in the period T3 to T7. In the period T3 to T4, the control circuit controls the voltage supply circuit such that the source select line SSL is in the floating state and the erase voltage V2 is applied to the source line SL. When the erase voltage V2 is applied, the voltages of the source select line SSL, the word lines WL1 to WL8, and the pipe gate PG in the floating state rise due to the capacitor coupling phenomenon. The control circuit controls the voltage supply circuit so that the drain select line (DSL) becomes a floating state.

Subsequently, when the voltage supply circuit discharges the pipe gate PG (for example, ground voltage) during the period T5 to T6, the voltage difference between the pipe gate PG and the channel layer SC increases sufficiently so that the pipe gate Electrons trapped in the charge storage layer CT of the charge storage layer PG are emitted to the channel layer SC. Thereafter, the supply of the erase voltage V2 is stopped in the period T7, and the erase operation is completed.

The control circuit includes a counter for counting the number of times the erase operation of the memory cells is performed. The control circuit controls the voltage supply circuit so as to perform the erase operation of the pipe cell based on the number of times of performing the counted erase operation. Specifically, the control circuit can control the voltage supply circuit to perform the erase operation of the pipe cell when the number of times of performing the erase operation of the memory cells reaches a preset number of times.

As described above, in the method of operating the semiconductor memory device according to the embodiment of the present invention, the cell current can be stably maintained by performing the erase operation of the pipe cell based on the number of times of performing the erase operation of the memory cells, Which is caused by deterioration of the pipe cell.

7 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 7, a memory system 600 according to an embodiment of the present invention includes a non-volatile memory device 620 and a memory controller 610.

For compatibility with the memory controller 610, the nonvolatile memory device 620 may be constructed of the above-described semiconductor memory device and operated in the manner described above. The memory controller 610 will be configured to control the non-volatile memory device 620. [ May be provided as a memory card or a solid state disk (SSD) by the combination of the nonvolatile memory device 620 and the memory controller 610. The SRAM 611 is used as an operation memory of the processing unit 612. [ The host interface 613 has a data exchange protocol of a host connected to the memory system 600. The error correction block 614 detects and corrects errors included in data read from the nonvolatile memory device 620. The memory interface 615 interfaces with the nonvolatile memory device 620 of the present invention. The processing unit 612 performs all the control operations for exchanging data of the memory controller 610.

Although it is not shown in the drawing, the memory system 600 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned. The non-volatile memory device 620 may be provided in a multi-chip package comprising a plurality of flash memory chips. The memory system 600 of the present invention can be provided as a highly reliable storage medium with a low probability of occurrence of errors. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) which has been actively studied recently. In this case, the memory controller 610 is configured to communicate with an external (e.g., host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, will be.

8 is a block diagram briefly showing a fusion memory device or a fusion memory system that performs program operation in accordance with various embodiments described above. For example, the technical features of the present invention can be applied to a one-nAND flash memory device 700 as a fusion memory device.

The one-NAND flash memory device 700 includes a host interface 710 for exchanging various information with devices using different protocols, a buffer RAM 720 for embedding codes for driving the memory devices or temporarily storing data, A control unit 730 for controlling read, program and all states in response to control signals and commands issued from the outside, a command and address, and a configuration for defining a system operating environment in the memory device And a NAND flash cell array 750 composed of an operation circuit including a nonvolatile memory cell and a page buffer. In response to a write request from the host, the OneNAND flash memory device programs the data according to the manner described above.

9, a computing system including a flash memory device 812 according to the present invention is schematically illustrated.

A computing system 800 in accordance with the present invention includes a microprocessor 820 electrically coupled to a system bus 860, a RAM 830, a user interface 840, a modem 850 such as a baseband chipset, Memory system 810. When the computing system 800 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 800 will additionally be provided. Although it is not shown in the drawing, it is to be appreciated that the computing system 800 in accordance with the present invention may be further provided with application chipsets, camera image processors (CIS), mobile DRAMs, It is obvious to those who have acquired knowledge. The memory system 810 may comprise, for example, a solid state drive / disk (SSD) using nonvolatile memory to store data. Alternatively, the memory system 810 may be provided as a fusion flash memory (e.g., a one-nAND flash memory).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

110: memory 120: control circuit
130: voltage supply circuit 140: page buffer group
150: column selection circuit 160: input / output circuit

Claims (17)

A memory string having a pipe cell and a channel layer having a U-shaped three-dimensional structure including memory cells arranged in series between the bit line and the pipe cell and between the source line and the pipe cell in a vertical direction from the pipe cell; And
And a peripheral circuit configured to perform an erase operation of the pipe cell.
2. The integrated circuit of claim 1,
And to perform an erase operation of the pipe cell in an erasing operation of the memory cells.
3. The method of claim 2, wherein the peripheral circuitry
And to reduce the threshold voltage of the memory cells and to decrease the threshold voltage of the pipe cell after a first time has elapsed.
2. The integrated circuit of claim 1,
And perform an erase operation of the pipe cell based on the number of times of performing the erase operation of the memory cells.
5. The method of claim 4, wherein the peripheral circuitry
And a counter for counting the number of erase operations of the memory cells.
2. The integrated circuit of claim 1,
And a hot hole is supplied to the channel layer to perform an erase operation of the pipe cell.
7. The method of claim 6, wherein the peripheral circuitry
And to apply a hot-hole supply voltage to the source line while floating the word lines of the memory cells and the pipe gate of the pipe cell to supply hot holes to the channel layer.
8. The method of claim 7, wherein the peripheral circuitry
And when the hot hole is supplied to the channel layer, discharges the pipe gate after applying an erase voltage to the source line.
9. The method of claim 8,
And to discharge the word lines a first time before discharging the pipe gates.
A memory string having a pipe cell and a channel layer comprising a U-shaped three-dimensional structure including memory cells arranged in series between the bit line and the pipe cell and between the source line and the pipe cell in a vertical direction from the pipe cell, A provided step; And
And performing an erase operation of the pipe cell.
11. The method of claim 10, further comprising counting the number of times the erase operation is performed on the memory cells,
Wherein the erase operation of the pipe cell is performed when the number of times of performing the erase operation reaches a preset number of times.
11. The method of claim 10, wherein performing an erase operation of the pipe cell comprises:
Supplying a hot hole to a channel layer of the memory string; And
And reducing the threshold voltage of the pipe cell when the hot hole is supplied.
13. The method of claim 12, wherein supplying the hot holes comprises:
Applying a hot-hole supply voltage to the source line while floating the word lines of the memory cells and the pipe gate of the pipe cell.
13. The method of claim 12, wherein reducing the threshold voltage of the pipe cell comprises:
Applying an erase voltage to the source line; And
And discharging the pipe gate.
11. The method of claim 10, wherein the erasing operation of the pipe cell is performed during the erasing operation of the memory cells.
16. The method of claim 15, wherein performing an erase operation on the pipe cell during an erase operation of the memory cells comprises:
Supplying a hot hole to a channel layer of the memory string;
Reducing the threshold voltage of the memory cells when the hot holes are supplied; And
Reducing the threshold voltage of the memory cells and reducing the threshold voltage of the pipe cell after a first time.
16. The method of claim 15, wherein performing an erase operation on the pipe cell during an erase operation of the memory cells comprises:
Supplying a hot hole to a channel layer of the memory string;
Applying an erase voltage to the source line when the hot hole is supplied;
Discharging the word lines of the memory cells; And
Discharging the word line of the memory cells and discharging the pipe gate after a first time.

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