KR20140124713A - Clock synchronization circuit and semiconductor memory device comprising thereof - Google Patents

Abstract

A clock synchronization circuit including a delay locked loop and a semiconductor memory device comprising the same are disclosed. The clock synchronization circuit, according to an embodiment of the present invention, comprises: a delay locked loop for generating an output clock by delaying an input clock and locking the input clock and the output clock by performing the delay locking operation; and a delay lock controller for terminating the delay locking operation by determining whether the locking state of the delay locked loop is maintained.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization circuit and a semiconductor memory device including the same,

TECHNICAL FIELD The present invention relates to a semiconductor circuit, and more particularly, to a clock synchronization circuit including a delay locked loop and a semiconductor memory device having the same.

A semiconductor device that operates at a high frequency such as a semiconductor memory device requires a circuit for synchronizing the phase of the internal clock with the phase of the external clock in order to prevent deterioration of high frequency operation performance, and a delay locked loop circuit is generally used for this purpose. The delay locked loop generates an internal clock by delaying the external clock, feeds back the generated external clock, and adjusts the delay time to perform a delay fixing operation to narrow the phase difference from the internal clock.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock synchronization apparatus and a method thereof for reducing a consumption current of a delay locked loop.

According to an aspect of the present invention, there is provided a clock synchronization apparatus including: a delay unit that delays an input clock to generate an output clock, performs a delay fixing operation, and locks the input clock and the output clock, Fixed loop; And a delay fixing control unit for determining whether the locked state of the delay locked loop is maintained and terminating the delay locked operation.

In one embodiment, the delay locked control section generates a delay locked end signal when the locked state continues for a predetermined time or more, and in response to the delay locked end signal, The operation of the fixed control section can be terminated.

In one embodiment, the predetermined time may be internally set based on a setting signal applied from the outside or a phase difference between the input clock and the output clock in the locked state.

In one embodiment, the delay fixing control unit includes: a fixed detector for determining whether the delay locked loop is locked and outputting a delay locked signal; And a counter for counting a time during which the locking state is maintained based on the delay locked signal and outputting a delay locked state signal when the counted value is equal to or greater than a predetermined value.

In one embodiment, the counter counts the input clock if the delay locked signal is at a first logic level, and may be reset if the delay locked signal is at a second logical level.

In one embodiment, the delay locked loop includes: a phase detector for generating an up-down signal based on a phase difference between the input clock and the output clock; A delay control unit responsive to the up-down signal for outputting a delay control signal for adjusting a delay time of the output clock; And a delay line for generating the output clock by delaying the input clock in response to the delay control signal.

In one embodiment, the fixed detector may receive the up-down signal and determine whether it is locked based on the number of repetitions of the up signal or the down signal of the up-down signal.

In one embodiment, the fixed detector may determine whether or not to lock based on a phase difference between the input clock and the output clock.

In one embodiment, the fixed detector may determine whether or not to lock based on a change value of the delay control signal.

In one embodiment, the delay locked loop includes: a first clock buffer for buffering the input clock to generate a delay clock and a first clock provided as a base clock of the fixed detector; A second clock buffer for buffering the input clock to generate a second clock provided as a base clock of the delay line; A third clock buffer for buffering an output clock of the delay line to generate a third clock provided to the phase detector; And a fourth clock buffer for buffering the output clock of the delay line and generating the output clock having the same phase as the third clock, The operation of the third clock buffer may be interrupted.

In one embodiment, the delay locked loop includes: a first clock buffer for buffering an output clock of the delay line to generate a first clock provided as a base clock of the phase detector, the delay controller, and the fixed detector; And a second clock buffer for buffering the output clock of the delay line and generating a second clock provided by the output clock, wherein the operation of the first clock buffer is stopped in response to the delay lock end signal .

In one embodiment, the clock synchronization circuit is applied to a semiconductor device that inputs or outputs data in synchronization with an external device, and when the operation state of the semiconductor device changes, a delay locked operation of the delay locked loop is performed .

According to an aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory cells, the method comprising: delaying an input clock to generate an output clock; A delay locked loop for locking the receiver; A delay fixing control unit for determining whether the locked state of the delay locked loop is maintained or not and terminating the delay locked operation; And a data output unit for outputting data stored in the plurality of memory cell arrays based on the output clock.

In one embodiment, the delay fixing control unit includes: a fixed detector for determining whether the delay locked loop is locked and outputting a delay locked signal; And a counter for counting a time period during which the locking state is maintained based on the delay locked signal to generate a delay locked state signal.

In one embodiment, the delay locked loop and the delay locked controller can be reset and restarted when the operating state of the semiconductor memory device is changed.

In one embodiment, the plurality of memory cells may comprise DRAM cells.

In one embodiment, the output clock may be a data strobe signal.

According to the technical idea of the present invention, when the input clock and the output clock of the delay locked loop are maintained in the locked state for a predetermined time, the delay locked operation is terminated, thereby reducing the consumption current.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a block diagram schematically illustrating a clock synchronization circuit according to an embodiment of the present invention.
2 is a block diagram illustrating one implementation of the clock synchronization circuit of FIG.
3 is a timing diagram of an input clock and an output clock according to the operation of the clock synchronization circuit of FIG.
4 is a timing diagram of the delay locked control section of Fig.
5 is a flow chart illustrating the operation of the clock synchronization circuit of FIG.
6 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG.
7 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG.
8A and 8B are block diagrams illustrating another embodiment of the clock synchronization circuit of FIG.
9 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG.
10 is a flowchart for explaining the operation of the clock synchronization circuit of FIG.
11 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG.
12 is a block diagram schematically showing a semiconductor device according to an embodiment of the present invention.
13 is a timing chart showing the operation of the clock synchronization circuit in the semiconductor device of Fig.
14A is a block diagram showing a case where an output clock is a data strobe signal of a semiconductor memory device in a clock synchronization circuit according to an embodiment of the present invention.
14B is a timing diagram of the semiconductor memory device of FIG. 14A.
15A and 15B are block diagrams showing implementations in which a clock synchronization circuit according to an embodiment of the present invention is applied to a memory device.
16 is a block diagram schematically illustrating a memory device according to an embodiment of the present invention.
17 is a diagram showing an embodiment of a memory system to which the semiconductor memory device of FIG. 16 is applied.
18 is a block diagram illustrating a computing system incorporating a memory system in accordance with one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be construed to have meanings consistent with the contextual meanings of the related art and are not to be construed as ideal or overly formal meanings as are expressly defined in the present application .

1 is a block diagram schematically illustrating a clock synchronization circuit according to an embodiment of the present invention. 1, the clock synchronization circuit 100 generates and outputs an output clock CLK_OUT synchronized with an input clock CLK_IN based on an input clock CLK_IN. The clock synchronization circuit 100 includes a delay locked loop 110, And a delay fixing control unit 120.

The delay locked loop 110 delays the input clock CLK_IN to generate an output clock CLK_OUT. The delay locked loop (DLL) 110 may perform a delay locking operation such that the phase difference between the input clock CLK_IN and the output clock CLK_OUT becomes a predetermined value or less. The delay fixing operation is performed such that the phase difference between the input clock CLK_IN and the output clock CLK_OUT is within a predetermined value by comparing the generated output clock CLK_OUT with the input clock CLK_IN and adjusting the delay time, , And is sometimes referred to as DLL update. Hereinafter, the terms delay locked operation and DLL update will be used together.

The delay fixing control unit 120 determines the locking state of the delay locked loop 110 and terminates the delay locked operation of the delay locked loop 110 when the locked state continues for a predetermined time or more. Furthermore, the operation of the delay locked control section 120 may also be terminated. Since the delay fixing operation is completed, the delay fixing loop 110 maintains the delay time set before the end of the delay fixing operation. The predetermined time is a time in which the environment in which the output clock CLK_OUT is used is expected to be sufficiently stable is set based on an externally applied setting signal or an input clock CLK_IN and an output clock CLK_OUT in a locked state, May be internally set based on the phase difference of < RTI ID = 0.0 > The predetermined time may be set differently depending on a specific environment, for example, voltage and temperature, for stability of the operation of the delay locked loop. For example, the predetermined time may be set to a time tCLK of several tens to several hundred cycles of the input clock CLK_IN.

As described above, the clock synchronization circuit 100 according to the embodiment of the present invention terminates the delay fixing operation when the locked state of the delay locked loop 110 is maintained for a predetermined time or more. If the locked state is maintained for a sufficient time, the input clock CLK_IN or the output clock CLK_OUT is unlikely to change suddenly. In such a situation, if the delay fixing operation is continuously performed, the current is unnecessarily consumed. Therefore, by ending the delay fixing operation, the consumption current can be reduced. Hereinafter, a clock synchronization circuit according to an embodiment of the present invention will be described in detail.

FIG. 2 is a block diagram illustrating an embodiment of the clock synchronization circuit of FIG. 1, FIG. 3 is a timing diagram of an input clock and an output clock according to the operation of the clock synchronization circuit of FIG. 2, Fig.

Referring to FIG. 2, the clock synchronization circuit 100a includes a delay locked loop 110 and a delay locked controller 120a.

The delay locked loop 110 may include a phase detector 113, a delay controller 112, and a delay line 111. The phase detector 113 may detect the phase difference by comparing the input clock CLK_IN with the output clock CLK_OUT and provide the phase difference to the delay controller 112. [ The phase difference can be output as the up-down signal Up / Dn. For example, the phase difference may be the result of latching the input clock (CLK_IN) at the rising edge or the falling edge of the output clock (CLK_OUT). For example, when the result of latching the input clock CLK_IN at the rising edge of the output clock CLK_OUT is a first logic level, for example, logic high, the phase of the output clock CLK_OUT is lower than the phase of the input clock CLK_IN And can be output as a down signal Dn which means to advance the phase of the output clock CLK_OUT. When the result of latching the input clock CLK_IN at the rising edge of the output clock CLK_OUT is a second logic level, for example, a logic low, the phase of the output clock CLK_OUT is lower than the phase of the input clock CLK_IN And can be output as an up signal Up meaning that the phase of the output clock CLK_OUT is delayed.

The delay control unit 112 generates and outputs a delay control signal CON_dly for adjusting the delay time of the output clock CLK_OUT in response to the up / down signal Up / Dn from the phase detector 113. The delay control signal CON_dly may be an n-bit code signal. The value of the delay control signal CON_dly may be decreased when the value of the delay control signal CON_dly is increased and the down signal Dn is received when the up signal Up is received from the phase detector 113 have. For example, when the delay control signal CON_dly is a 4-bit delay control code, when the delay control signal CON_dly is '0 0 0 0', the input clock CLK_IN is output as the output clock CLK_OUT without any delay , The input clock (CLK_IN) may be delayed and output as the value increases from 0 to 0, 1 to 0, 0 to 1, and so on. In this case, the initial value may be an intermediate value such as '0 1 1 0'. Each time the up signal Up is received from the phase detector 113, the value increases in order and the down signal Up is received The value can be decremented each time.

The delay line 111 delays and outputs the input clock CLK_IN. The clock output from the delay line 111 may be an output clock CLK_OUT. At this time, the delay time can be adjusted according to the delay control signal CON_dly. For example, as the value of the delay control signal CON_dly changes, the delay time can be increased or decreased. As described above, the delay control signal CON_dly is an n-bit code signal. The delay time increases as the code value increases, and the delay time decreases as the code value decreases.

2, the phase detector 113, the delay controller 112, and the delay line 111 form a feedback circuit and feed back the output clock CLK_OUT to compare the result with the input clock CLK_IN By adjusting the delay time, the input clock CLK_IN and the output clock CLK_OUT can be locked. 3, the output clock CLK_OUT in the unlocked state is delayed with respect to the input clock CLK_IN, and the delay Dint is delayed by the clock synchronization circuit 100 or the clock synchronization circuit 100, May be generated by an internal component of an integrated circuit (not shown), such as a load on the output clock CLK_OUT. The delay locked loop 110 may perform a delay locked operation to lock the input clock CLK_IN and the output clock CLK_OUT. The delay locked loop 110 may further delay the output clock CLK_OUT to synchronize the output clock CLK_OUT with the input clock CLK_IN. At this time, the delay time Ddll generated by the delay locked loop 110 may be within one cycle (1 tCLK), and accordingly, the output clock CLK_OUT is delayed by one cycle (1 tCLK) with respect to the input clock CLK_IN ) So that the input clock CLK_IN and the output clock CLK_OUT can be synchronized.

2, the delay-fixed control unit 120a includes a fixed detection unit 122a and a counter 121. The delay-locked control unit 120a determines a locked state of the delay locked loop 110. If the locked state is maintained for a predetermined time or more, And ends the delay fixing operation of the fixed loop 110. [

The fixed detector 122a determines whether the delay locked loop is locked and outputs a delay locked signal DLS. The fixed detection unit 122a may receive the up-down signal and determine whether the up-down signal is locked based on the number of repetitions of the up signal Up or the down signal Dn of the up-down signal. For example, if the up signal Up or the down signal Up is not continuously repeated for a predetermined number of times or more, the fixed detector 122a determines that the signal is locked and outputs the delay locked signal DLS to the first logic level, If the up signal Up or the down signal Up is continuously repeated more than a predetermined number of times, it is determined that the signal is not locked, and the delay locked signal DLS can be output to the second logic level, for example, logic low .

The counter 121 counts a time period during which the locked state is maintained based on the delay locked signal DLS. If the counted value is greater than or equal to the predetermined value, that is, the locked state is maintained for a predetermined time, Output. For example, if the delay locked signal DLS is at the first logic level, the counter 121 counts the input clock CLK_IN and outputs a delay locked end signal Disable when the counted value is equal to or greater than a predetermined value have. At this time, if the delay locked signal DLS is at the second logic level, the counter 121 can be reset.

Referring to FIG. 4, a more detailed description will be given below. 4, when the input clock CLK_IN is applied and the delay locked signal DLS output from the fixed detector 122a is at the first logic level, e.g., logic high, the counter 121 counts the input clock CLK_IN ) Can be counted. As shown, the value can be counted for each rising edge (or falling edge) of the input clock CLK_IN. At this time, when the delay locked signal DLS becomes the second logic level, for example, logic low, the counter 121 is reset and stops the counting operation. When the delay locked signal DLS becomes logic high again, the counter 121 can resume counting. When the delay locked signal DLS holds a logic high and the count value becomes a predetermined value, for example, 300 or more, the counter 121 can output the delay locked end signal Disable as a first logic level. The delay lock termination signal (Disable) is provided to the delay lock loop 110 to terminate the DLL update. As shown in the figure, the DLL update is continuously performed when the delay fixing termination signal (Disable) is outputted, for example, when it is logic low, and when the delay fixing termination signal (Disable) occurs, . The phase detection unit 113 and the delay control unit 112 of the delay locked loop 110 stop operating and the delay time of the delay line 111 is controlled before the delay locked operation is completed, That is, the delay time before the DLL update is maintained is maintained. Further, when the delay fixing termination signal (Disable) is outputted, the fixed detection section 122a and the counter 121 of the delay control section 120 can also stop the operation. Accordingly, the operation of most of the configurations of the clock synchronization circuit except for the delay line 111 is stopped, so that the consumption current can be reduced.

5 is a flow chart illustrating the operation of the clock synchronization circuit of FIG.

Referring to FIG. 5, first, the delay locked loop 110 starts updating (S110). Next, it is determined whether the delay locked loop 110 is locked (S120). As described with reference to FIG. 2, the fixed detection unit 122a may determine whether or not it is locked, and output the delay locked signal DLS. At this time, if the delay locked loop 110 has not been locked, the process of updating the delay locked loop 110 and determining whether the locked state is locked is repeated.

When the delay locked loop 110 is locked, it is determined whether the locked state is maintained for a predetermined time (S130). For example, if the delay locked signal DLS output from the fixed detection unit 122a is at the first logic level, the counter 121 performs counting, and when the delay locked signal DLS reaches the second logical level, Is reset, it is possible to determine whether the locked state is maintained for a predetermined time. If the locked state is not maintained for a predetermined time, the process of determining whether the DLL is updated and locked is repeated. Thereafter, if it is determined that the locked state has been maintained for a predetermined time, the updating of the delay locked loop 110 is stopped. For example, when the count value of the counter 121 becomes equal to or greater than a predetermined value, the counter 121 outputs a delay lock end signal (Disable) , The delay fixing operation ends, and the delay fixing control unit 120a can also terminate the operation.

On the other hand, the overall operation of the above-described clock synchronization circuit, or the start of the DLL update (S110), can be performed each time the operation state (or operation mode) of the semiconductor device to which the clock synchronization circuit is applied is changed. For example, in the case of a DRAM memory device including a clock synchronization circuit, an operation state can be distinguished, such as an idle state, an active-precharge state, a power-down state, and the like. DLL update is required. Therefore, even after the DLL update is completed, the clock synchronization circuit can perform the DLL update again to lock the delay locked loop when the operation state of the DRAM memory device changes. Thereafter, it is determined whether the locking is continued for a predetermined time or longer (S120, S130), and the step of terminating the DLL update (S140) may be performed selectively or in accordance with the entire operation state according to the operation state of the semiconductor device.

6 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG. Figure 6 shows a modified embodiment of the clock synchronization circuit of Figure 2;

6, the clock synchronization circuit 100b includes a delay locked loop 110 and a delay locked controller 120b. The delay locked loop 110 includes a delay line 111, a delay control unit 112, And the delay fixing control unit 120b may include a fixed detection unit 122b and a counter 121. [ The clock synchronization circuit component of FIG. 6 and its operation are similar to the components and operation of the clock synchronization circuit of FIG. However, the operation of the fixed detection unit 122b differs from that of Fig. 2, the fixed detector 122a determines whether the delay locked loop 110 is locked based on the up / down signal Up / Dn output from the phase detector 113. [ However, the fixed detection unit 122b in the present embodiment can receive the input clock CLK_IN and the output clock CLK_OUT, and compare the two clocks CLK_IN and CLK_OUT to determine whether or not they are locked. When the phase difference between the input clock CLK_IN and the output clock CLK_OUT is equal to or less than a predetermined threshold value, the fixed detection unit 122b can determine that it is in the locked state. Operation of other components and operations of the clock synchronization circuit are the same as those described with reference to FIG. 2, and a duplicate description will be omitted.

7 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG. Figure 7 shows a modified embodiment of the clock synchronization circuit of Figure 2;

7, the clock synchronization circuit 100c includes a delay locked loop 110 and a delay locked controller 120c. The delay locked loop 110 includes a delay line 111, a delay control unit 112, And a delay fixing control unit 120c may include a fixed detection unit 122c and a counter 121. [ The clock synchronization circuit component of FIG. 7 and its operation are similar to those of the clock synchronization circuit of FIG. 2 and FIG. However, there is a difference in the operation of the fixed detection unit 122c. The fixed detection unit 122c in this embodiment can determine whether or not to be locked based on the delay control signal CON_dly generated by the delay control unit 112. [ The fixed detection unit 122c can determine whether or not the data is locked according to the direction of change of the data value of the delay control signal CON_dly. For example, if the data value of the delay control signal CON_dly increases or decreases, it is determined that the state is not the locked state because the state of the delay time is required to be continuously changed, and the data value of the delay control signal CON_dly repeats increase and decrease Or there is no change in the data value of the delay control signal CON_dly, it is judged that the state is the locked state because the phase difference between the input clock CLK_IN and the output clock CLK_OUT is small and a change in the delay time is not required. As described above, in this embodiment, the fixed detector 122c can determine whether or not to lock based on the delay control signal CON_dly. Operations of other components and operations of the clock synchronization circuit are the same as those described with reference to FIG. 2, and a duplicate description will be omitted.

8A and 8B are block diagrams illustrating another embodiment of the clock synchronization circuit of FIG. 1. Referring to FIGS. 8A and 8B, the clock buffers 114, 115, 116, 117, 118, , The operation of at least one of the clock buffers 114, 115, 116, 117, 118, and 119 used for the buffering is terminated when the locked state of the delay locked loop 110d or 110d ' , The delay fixing operation can be terminated.

First, referring to Fig. 8A, the clock synchronization circuit 100d includes a delay locked loop 110d and a delay locked controller 120d.

The delay locked loop 110d includes a delay line 111, a delay control unit 112, a phase detection unit 113, first to fourth clock buffers 114, 115, 116 and 117, and an input clock CLK_IN, To generate an output clock CLK_OUT and to perform a delay fixing operation to lock the input clock CLK_IN and the output clock CLK_OUT.

The operation of the delay locked loop 110d is similar to that of the delay locked loop 110 described above with reference to FIG. 2, the delay locked loop 110d delays the input clock CLK_IN to generate an output clock CLK_OUT and performs a delay fixing operation to generate an input clock CLK_IN and an output clock CLK_OUT ). When the delay fixing termination signal Disable is supplied from the delay fixing control section 120d, the delay fixing operation is terminated.

The delay locked loop 110d of the present embodiment includes a first clock buffer 114 and a second clock buffer 115 for buffering an input clock CLK_IN and an output of the delay line 111, that is, a delay clock CLK_dly, A third clock buffer 116 and a fourth clock buffer 117 for buffering the input clock CLK_IN and the first clock CLK1 task 2 clock CLK2 generated by buffering the input clock CLK_IN, And the third clock CLK3 generated by buffering the third clock CLK_dly. At this time, it can be assumed that the third clock buffer 116 and the fourth clock buffer 117 have the same phase delay characteristics. Accordingly, the third clock CLK3 and the output clock CLK_OUT buffered by the third clock buffer 116 and the fourth clock buffer 117 respectively buffer the output of the delay clock CLK_dly are substantially the same in phase can do. When the delay fixing termination signal (Disable) is received from the delay fixing control unit 120d, the first clock buffer 114 and the third clock buffer 116 terminate their operation, and accordingly, the first clock CLK1 and the third By not generating the clock CLK3, the delay fixing operation can be ended. Specifically, it is as follows.

The first clock buffer 114 generates the first clock CLK1 by buffering the input clock CLK_IN and the second clock buffer 115 buffers the input clock CLK_IN to generate the second clock CLK2 do.

The first clock CLK1 may be provided to the delay control section 112 and may also be provided to the counter 121d of the delay locked control section 120d. The first clock buffer 114 can end its operation in response to the delay fixing termination signal Disable. As a result, the first clock CLK1 is not generated.

The second clock CLK2 may be provided to the delay line 111. [ The delay line 111 can generate the delayed clock CLK_dly by delaying the second clock CLK2.

The third clock buffer 116 generates the third clock CLK3 by buffering the delayed clock CLK_dly output from the delay line 111 and the fourth clock buffer 114 also buffers the delayed clock CLK_dly And generates an output clock CLK_OUT. As described above, the third clock buffer 116 and the fourth clock buffer 117 may have the same phase characteristic or the same buffer. Accordingly, the third clock CLK3 and the output clock CLK_OUT can be substantially the same in phase.

The third clock CLK3 may be provided to the phase detector 113. [ The third clock buffer 116 may terminate its operation in response to the delay fixing termination signal Disable. Accordingly, the third clock CLK3 is not generated.

The phase detector 113 compares the phase difference between the third clock CLK1 and the input clock CLK_IN and generates the result as the up-down signal Up / Dn.

The delay control unit 112 generates a delay control signal CON_dly for adjusting the delay time of the delay line 111 according to the up-down signal Up / Dn. At this time, the delay control unit 112 may operate based on the first clock CLK1. For example, when the delay control signal CON_dly changes, the data value of the delay control signal CON_dly may be output at the rising edge or the falling edge of the first clock CLK1.

The delay line 111 generates the delayed clock CLK_dly by delaying the second clock CLK2 and the delay time can be adjusted in response to the delay control signal CON_dly.

  The delay fixing control unit 120d includes a fixed detection unit 122d and a counter 121d and determines the locking state of the delay locked loop 110d. When the locked state is maintained for a predetermined time or longer, The fixing operation is terminated.

The fixed detector 122d determines whether the delay locked loop 110d is locked and outputs a delay locked signal DLS. The fixed detection unit 122d receives the up-down signal Up / Dn from the phase detection unit 113 and detects the number of repetitions of the up signal Up or the down signal Dn of the up- It is possible to determine whether or not the lock is performed. For example, if the up signal Up or the down signal Up is not repeated more than a predetermined number of times, the fixed detector 122d determines that the signal has been locked and outputs the delay locked signal DLS at a first logic level, If the up signal Up or the down signal Up repeats more than a predetermined number of times, it is determined that the signal is not locked, and the delay locked signal DLS can be output to the second logic level, for example, logic low.

The counter 121d is supplied with the first clock CLK1 from the first clock buffer 114 and can operate in response to the delay locked signal DLS and the state start signal ST. The counter 121d outputs a delay fixing termination signal (Disable) when the locked state of the delay locked loop 110d is delayed by a predetermined time or more. The counter 121d may count the first clock CLK1 if the delay locked signal DLS is at the first logic level and determine the time during which the delay locked loop 110d maintains the locked state according to the count value. When the delay locked signal DLS is at the second logic level, the counter 121 is reset to stop the counting operation, and then, when the delay locked signal DLS becomes the first logical level, counting can be started again. The counter 121d outputs a delay lock end signal Disable when the count value is equal to or greater than a predetermined value, that is, when the locked state is maintained for a predetermined time.

 As described above, the operations of the first clock buffer 114 and the third clock buffer CLK3 are ended in response to the delay fixing termination signal (Disable). Therefore, when the delay fixing termination signal (Disable) occurs, the first clock (CLK1) and the third clock (CLK3) are not generated. The operations of the delay control unit 112 using the first clock CLK1 and the detection unit 122d of the counter 121d are stopped and the third clock signal CLK1 is not generated when the first clock CLK1 and the third clock CLK3 are not generated. The operation of the phase detecting unit 113 using the clock signal CLK3 is stopped and the current consumption can be reduced.

 Since the delay control signal CON_dly output from the delay control unit 112 is maintained at its value and applied to the delay line 111 and the delay line 111 operates based on the second clock CLK2, The output clock CLK_OUT is generated while maintaining the delay time of the output clock CLK_OUT.

On the other hand, when the status change signal ST is applied from an external device, for example, a system control unit (not shown), the counter 121d is reset. As the counter 121d is reset, generation of the delay fixing termination signal (Disable) is stopped. When the generation of the delay lock termination signal (Disable) is stopped, it means that the delay lock termination signal (Disable) is the second logic level, for example, logic low. Accordingly, the first clock buffer 114 operates to generate the first clock signal CLK1, the delay locked loop 110d performs the delay locked operation, and the delay locked detector 120d also operates.

Fig. 8B shows a modification of Fig. 8A. 8A, similarly to FIG. 8A, a clock buffer 118, 119 is provided, and when the locked state continues for a predetermined time, the operation of at least one of the clock buffers 118, 119 is terminated, Can be terminated.

Referring to FIG. 8B, the clock synchronization circuit 100d 'includes a delay locked loop 110d' and a delay locked controller 120d '.

The delay locked loop 110d 'includes a delay line 111, a delay control unit 112, a phase detection unit 113, first and second clock buffers 118 and 119, and delays the input clock CLK_IN Generates an output clock CLK_OUT, and performs a delay fixing operation to lock the input clock CLK_IN and the output clock CLK_OUT.

The delay fixing control unit 120d 'includes a fixed detection unit 122d and a counter 121d and determines the locking state of the delay locked loop 110d'. When the locked state is maintained for a predetermined time or longer, Ending the delay fixing operation of Fig.

The operations of the delay locked loop 110d 'and the delay locked controller 120d' are similar to those of the delay locked loop 110d and the delay locked controller 120d of FIG. 8a. In FIG. 8A, the input clock CLK_IN is buffered in the first and second clock buffers 114 and 115, and the output first clocks CLK1 and CLK2 are used for the operation of the clock synchronization circuit 100d '. However, in the delay locked loop 110d 'of FIG. 8B, the input clock CLK_IN is applied to the delay line 111 without buffering, and the delayed clock CLK_dly output from the delay line 111 is buffered . As shown in the figure, the first clock buffer 118 and the second clock buffer 119 each buffer the delay clock CLK_dly to output the first clock CLK1 and the output clock CLK_OUT. At this time, the first clock buffer 118 and the second clock buffer 119 may have the same phase characteristic or the same buffer. Accordingly, the first clock CLK1 and the output clock CLK_OUT may be substantially the same in phase.

The first clock CLK1 is applied to the phase detector 113, the delay controller 112 and the counter 121d. Accordingly, the first clock CLK1 is used for the phase detection operation and the delay control operation in the delay locked loop 110d ', and can be used for the locked state determination operation in the delay locked control section 120d'.

When the delay fixing termination signal (Disable) is received from the delay fixing control section 120d ', the first clock buffer 118 ends its operation and accordingly does not generate the first clock (CLK1). Therefore, the operation of the delayed phase detection unit 113, the control unit 112, the counter 121d 'and the fixed detection unit 122d using the first clock CLK1 is stopped and the phase detection unit using the third clock CLK3 113 can be stopped and the current consumption can be reduced. As described above, the clock synchronization circuit 100d of this embodiment separates the reference clock used for the delay line 111 and the other circuits 112, 113, 120d and 120d ', and when the delay end signal is generated, The generation of the reference clocks, for example, the first clocks CLK1 and the third clocks CLK3 used in the first and second clocks 112, 113, 120d and 120d 'can be stopped and the delay fixing operation can be stopped.

In this embodiment, the clock buffers 114, 115, 116, 117 and 118 (not shown) are used to separate the reference clocks used for the circuits 111, 112, 113, 121d and 122d and selectively terminate the generation of the reference clocks. , 119) were used. However, the technical idea of the present invention is not limited thereto. The clock buffers 114, 115, 116, 117, 118 and 119 may be replaced by other means capable of transmitting input signals such as switches, transmission gates, and the like, which can be turned on / off in response to control signals.

The fixed detectors 122d and 122d 'not only determine whether or not they are locked based on the up / down signals (Up / Dn) from the phase detector 113 as described above, It is possible to directly compare the clock to judge whether or not to lock it, or to judge whether or not to lock based on the delay control signal CON_dly.

9 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG.

Referring to FIG. 9, the clock synchronization circuit 100e includes a delay locked loop 110 and a delay locked control section 120e. The delay locked loop 110 is substantially the same as the operation of the delay locked loop 110 of FIG. 2, and redundant description will be omitted.

In this embodiment, the fixed control section 120e controls the delay locked loop 110 at a predetermined time after the clock synchronization circuit 100e starts to operate, that is, after the delay locked loop 110 starts to be updated It is judged whether or not it is locked and a delay fixed end signal (Disable) can be generated. To this end, the fixed controller 120e may include a counter 121e, a fixed detector 122e, and a logic gate 123. [

The fixed detector 122e determines whether or not it is locked and outputs a delay locked signal DLS. At this time, the fixed detection unit 122e can determine whether or not to lock based on the up / down signal Up / Dn provided by the phase detector 113 as shown in FIG. In addition, it is also possible to directly compare the input clock CLK_IN and the output clock CLK_OUT or judge whether or not the data is locked based on a change in the data value of the delay control signal CON_dly.

The counter 121e counts the input clock CLK_IN. When the count value becomes equal to or greater than a predetermined value, for example, it may generate the counting signal CNT when it is equal to or greater than a preset value.

The logic gate 123 generates a delay fixing termination signal (Disable) signal based on the counting signal CNT and the delay fixing signal DLS. For example, the counting signal CNT and the delay locked signal DLS may generate a first logic level, e.g., a logic high level, a delay locked end signal Disable of a first logic level. In this embodiment, the logic gate 128 is shown as being an AND gate, but it is not limited thereto. May be variously modified in consideration of the logic levels of the output signals CNT and DLS according to the operation of the counter 121e and the fixed detector 122e.

For example, the following will be described in more detail. If the counter 121e is set to generate the counting signal CNT after counting 300 cycles 300 tCLK of the input clock CLK_IN, the clock synchronization circuit 100e starts to operate, and after a period of 300 cycles, Depending on whether the fixed loop 110 is locked, a delay lock end signal Disable may be generated. If the delay locked loop 110 is locked after the lapse of 300 cycles, a delay locked end signal (Disable) occurs, and the delay locked operation, that is, the DLL update may be terminated. If the delay locked loop 110 has not been locked at the end of the time of 300 cycles, the delay locked loop 110 continues to perform the delay locked operation, and when the delay locked loop 110 is locked, Lt; / RTI >

As described above, the clock synchronization circuit 100e of FIG. 9 performs the delay fixing operation, that is, the DLL update until a predetermined time after the start of operation, and when the delay locked loop 110 is locked after the predetermined time, The delay locked operation can be stopped.

10 is a flowchart for explaining the operation of the clock synchronization circuit of FIG. Referring to FIG. 10, the delay locked loop 110 starts DLL update (S210). Thereafter, the DLL update is performed for a predetermined time (S220). The DLL update can be performed regardless of whether the count value of the counter 121e is equal to or greater than a predetermined value.

It is determined whether the delay locked loop 110 is locked after a predetermined time (S230). As described with reference to Fig. 10, it is possible to determine whether the fixed detector 122e is locked or not, and output the result as the delay locked signal DLS. At this time, if the delay locked loop 110 has not been locked, the process of updating the delay locked loop 110 and determining whether the locked state is locked is repeated.

When the delay locked loop 110 is locked, the update of the delay locked loop 110 is stopped (S240). For example, after a predetermined time, the counter 121e outputs the counting signal CNT of the first logic level, the delay locked loop 110 is locked, and the fixed detector 122e latches the delay locked When the signal DLS is outputted, the logic gate 123 can output a delay lock end signal (Disable) signal. The delay locked loop 110 may update, i.e., terminate the delay locked operation in response to the delay locked end signal (Disable) signal, and terminate the operation of the delayed fixed control part 120e.

On the other hand, the entire operation of the above-described clock synchronizing circuit, or the start of DLL update (S210), may be performed each time the operating state (or operating mode) of the semiconductor device to which the clock synchronizing circuit 100e is applied is changed. For example, in the case of a DRAM memory device including a clock synchronization circuit, an operation state can be distinguished, such as an idle state, an active-precharge state, a power-down state, and the like. DLL update is required. Therefore, after the DLL update is completed, the clock synchronization circuit can perform the DLL update again to lock the delay locked loop when the operation state of the DRAM memory device changes. Thereafter, the DLL update is performed for a predetermined period of time (S220). Thereafter, it is determined whether or not the lock is performed (S230) and the DLL update is terminated (S240), depending on the operation state of the semiconductor device, Lt; / RTI >

11 is a block diagram illustrating another embodiment of the clock synchronization circuit of FIG. Figure 11 shows a modified embodiment of the clock synchronization circuit of Figure 9;

The configuration of the clock synchronization circuit 100f in Fig. 11 is similar to the clock synchronization circuit 100e in Fig.

 The mode setting signal MS may be applied to the counter 121f of FIG. 11 to operate in the first mode or the second mode. The delay locked signal DLS of the fixed detector 122f may be applied to the logic gate 123, But also to the counter 121f.

The clock synchronization circuit 100f selectively operates in accordance with the mode setting signal MS applied to the counter 121f as in the clock synchronization circuit 100a of FIG. 2, or alternatively as in the clock synchronization circuit 100e of FIG. 9 Can operate.

The counter 121f counts the input clock CLK_IN and can generate the counting signal CNT when the counted value becomes a predetermined value or more. At this time, in response to the mode setting signal MS, when the counter 121f operates in the first mode, the counter 121f operates irrespective of the delay locked signal DLS and the counter 121f operates in the second mode The counter 121f may be reset in response to the delay locked signal DLS.

Accordingly, in the first mode, the delay fixing control unit 120f determines whether or not the delay locked loop 110 is locked after a predetermined time elapses after the clock synchronizing circuit 100f starts operating, and outputs a delay locked end signal Disable ). Since the counter 121f can be reset in response to the delay locked signal DLS even after the counter 121f starts counting in the second mode, (CNT), the delay fixing control unit 120f generates a delay locking end signal (Disable) signal after the locked state is maintained for a predetermined time.

The clock synchronization circuit 100f can operate in various environments. For example, it can operate in an environment where voltage and temperature changes are severe, and may operate in an environment where the voltage and temperature changes are not severe. It is less likely that the phase of the output clock CLK_OUT is changed after the delay locked loop 110 is locked in an environment where the voltage and the temperature are not significantly changed. Accordingly, the counter 121f is operated in the first mode to determine whether or not the delay locked loop 110 is locked after a predetermined time elapses after the clock synchronization circuit 100f starts to operate. Is locked, the delay locked operation can be terminated. Or when the clock synchronization circuit 100f operates in an environment with a severe change in voltage and temperature, the counter 121f is operated in the second mode and the locked state of the delay locked loop 110 is maintained for a predetermined time , It is possible to have enough time for the output clock CLK_OUT to be stabilized.

12 is a block diagram schematically showing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 12, the semiconductor device 1000 may include a clock synchronization circuit 100a and a data output circuit 1100. The semiconductor device 1000 may be a memory device, a timing controller of a display driver, or the like, which transmits and receives data in synchronization with an external device of a memory. In FIG. 12, the clock synchronizing circuit 100a of FIG. 2 is applied, but the present invention is not limited thereto. One of the embodiments of the present invention can be applied to the clock synchronization circuit included in the semiconductor device 1000.

The clock synchronization circuit 100a delays the input clock CLK_IN to output the output clock CLK_OUT and performs a delay fixing operation to lock the input clock CLK_IN and the output clock CLK_OUT. The data output circuit 1100 can output data DATA in the semiconductor device 1000 in synchronization with the output clock CLK_OUT.

As described with reference to FIG. 2, the clock synchronization apparatus 100a ends the delay fixing operation when the locked state continues for a predetermined time. Accordingly, the phase detector 113 and the delay controller 112 of the delay locked loop 110 do not operate, and the operation of the delay locked controller 120a may also be stopped.

On the other hand, the clock synchronizing apparatus 100a may receive a state start signal ST indicating a change in the operating state of the semiconductor device 1000 and reset in response to the state start signal ST. For example, the state start signal ST may be applied to the counter 121 to reset the counter. When the locked state of the delay locked loop 110 is maintained for a predetermined time, for example, the counter 121 generates a delay fixed end signal (Disable) to end the delay fixed operation. When the counter 121 is reset in response to the stop signal ST, the delay lock operation can be resumed.

Therefore, the clock synchronizing apparatus 100a can perform the delay fixing operation, that is, the DLL update again, when the operation state of the semiconductor device 1000 changes even after the delay fixing operation is finished.

13 is a timing chart showing the operation of the clock synchronization circuit in the semiconductor device of Fig.

Referring to FIG. 13, the state start signal ST is applied at time t1, and the DLL update of the clock synchronization circuit 100a can be performed. When the delay locked loop 110 is locked, the delay locked signal DLS is output from the fixed detector 121a to the first logic level. If the locked state continues for a predetermined time, for example, 300 tCLK, the delay locked fixed signal Disable is generated from the counter 121 (t2), and the delay locked operation can be terminated.

Thereafter, when the state start signal ST occurs at time t3, the DLL update can be performed. The state start signal ST is received when the operation state of the semiconductor device 1000 changes (at the time t3 and t5) even after the delay fixing operation is completed in the clock synchronizing apparatus 100a, Can be performed.

Since the semiconductor device such as the memory device repeatedly changes the operation state, the clock synchronization circuit 100a may have the same effect as periodically performing the DLL update.

14A is a block diagram showing a case where an output clock is a data strobe signal of a semiconductor memory device in a clock synchronization circuit according to an embodiment of the present invention, and FIG. 14B is a timing diagram of a semiconductor memory device.

Referring to FIG. 14A, the memory device 200 and the memory controller 300 may operate based on an external clock (ECLK) provided in a system such as an external device, such as a central processing unit. When the memory device 200 receives the data DQ from the memory controller 300 or transmits the data DQ to the memory controller 300, And can operate in synchronization with the data strobe signal DQS, which is a separate clock generated based on the clock ECLK. The data strobe signal DQS is an internal clock generated in the memory device 200 or the memory controller 300 on the basis of the external clock ECLK by the delay component D of the internal circuit, It may not be synchronized with the clock (ECLK). Accordingly, the memory device 200 includes the clock synchronization circuit 100 according to the embodiment of the present invention, and can synchronize the data strobe signal DQS with the external clock ECLK. At this time, the external clock ECLK may be the input clock CLK_IN of the clock synchronization circuit 100, and the data strobe signal DQS may be the output clock CLK_OUT. When the strobe signal DQS is synchronized to the external clock ECLK by the operation of the clock synchronization circuit 100, the data DQ can be outputted or received at the rising edge or the rising edge of the data strobe signal DQS.

15A and 15B are block diagrams schematically illustrating an example in which a clock synchronization circuit according to an embodiment of the present invention is applied to a memory device.

The clock synchronization circuit 100 may be mounted inside the memory device 200 as shown in FIG. 15A. The clock synchronization circuit 100 generates the data strobe signal DQS and the memory device 200 can exchange the data DQ with the memory controller 300 based on the data strobe signal DQS.

On the other hand, the clock synchronization circuit 100 may be mounted on the memory module 400 having the memory device 200 as shown in FIG. 15B. In FIG. 15B, the memory module 400 is shown as having one memory device 200, but it is not limited thereto. The memory module 400 may include a plurality of memory devices 200. The clock synchronization circuit 100 may generate a data strobe signal DQS for use in the memory device 200 provided in the memory module 400. [

16 is a block diagram schematically showing a semiconductor memory device according to an embodiment of the present invention.

16, a semiconductor memory device includes a clock synchronizing circuit 100, a memory array 510, a row decoder 520, a column decoder 530, an input / output circuit 540, an addressing circuit 540, (550), and a control circuit (560).

The memory array 510 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected between the plurality of word lines and the plurality of bit lines. Or a volatile memory cell such as DRAM (Dynamic Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory) of each of the plurality of memory cells.

Also, each of the plurality of memory cells may be implemented as a non-volatile memory cell. The nonvolatile memory cell may be a nonvolatile memory cell such as a PRAM (Phase Change RAM), a Nano Floating Gate Memory (NFGM), a Polymer RAM (PoRAM), a Magnetic RAM (MRAM), a Ferroelectric RAM (FeRAM), a Resistive RAM (RRAM), a Nanotube RRAM (RRAM), a holographic memory, a Molecular Electronics Memory Device, or an Insulator Resistance Change Memory. The non-volatile memory cell may store one bit or a plurality of bits.

The row decoder 520 may receive the row address output from the addressing circuit 550 and may decode the received row address to select any one of the plurality of word lines. The column decoder 530 receives the column address output from the addressing circuit 550 and decodes the received column address to select any one of the plurality of bit lines.

The input / output circuit 540 may write data to at least one memory cell selected by the row decoder 520 and the column decoder 530. [ The input / output circuit 540 may read data stored in at least one memory cell selected by the row decoder 520 and the column decoder 530.

The addressing circuit 550 can generate a row address and a column address under the control of the control circuit 560. The control circuit 560 may generate a plurality of operation control signals capable of controlling the operation of the addressing circuit 550 in response to a plurality of control signals required to perform a write operation or a read operation.

The clock synchronization circuit 100 may transmit the internal clock ICLK synchronized with the external clock ECLK to the output drivers OD1 and OD2. Accordingly, the first output driver OD1 can transfer the data signal DATA to the first pad DQ in response to the internal clock ICLK. Therefore, the data write or read operation can be performed in synchronization with the internal clock ICLK. In addition, the second output driver OD2 can transfer the internal clock ICLK to the second pad DQS. The first pad DQ and the second pad DQS may be arranged on the semiconductor chip in the form of a center pad or an edge pad as a pad of the semiconductor chip in which the semiconductor memory device is implemented.

17 is a diagram showing an embodiment of a memory system to which the semiconductor memory device of FIG. 16 is applied.

17, the memory system 2000 may include a memory module 2100 and a memory controller 2200. [ The memory module 2100 may mount at least one semiconductor memory device 2110 on a module board. The semiconductor memory device 2110 may be implemented as a DRAM chip, and each semiconductor memory device 2110 may include a plurality of semiconductor layers. The semiconductor layers may include one or more master chips 2111 and one or more slave chips 2112. The transfer of signals between the semiconductor layers can be performed through a through silicon via (TSV). The master chip 2111 and the slave chip 2112 may include a memory array, a storage unit, a refresh unit, and the like. The master chip 2111 and the slave chip 2112 also include a clock synchronization circuit 100. The clock synchronization circuit 100 may be a clock synchronization circuit according to one of the embodiments of the present invention described above.

Memory module 2100 may communicate with memory controller 2200 via a system bus. Data DQ, data strobe DQS, command / address CMD / ADD and clock signal CLK can be transmitted and received between the memory module 2100 and the memory controller 2200 through the system bus.

18 is a block diagram illustrating a computing system incorporating a memory system in accordance with one embodiment of the present invention.

Referring to FIG. 18, the semiconductor memory device of the present invention may be mounted as a RAM 3400 in a computing system 3000 such as a mobile device or a desktop computer. The semiconductor memory device mounted with the RAM 3200 can be applied to any of the above-described embodiments. For example, the RAM 3400 may be a semiconductor memory device of the above embodiments, or may be applied in the form of a memory module. The RAM 3200 may also be a concept that includes a semiconductor memory device and a memory controller.

A computing system 3000 according to one embodiment of the present invention includes a central processing unit 3100, a RAM 3200, a user interface 3300 and a non-volatile memory 3400, As shown in Fig. The nonvolatile memory 3400 may be a mass storage device such as an SSD or a HDD.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: clock synchronization circuit 110: delay locked loop
120: delay control unit 111: delay line
112: Delay controller 113: Phase detector
121: counter 122: fixed detector

Claims (10)

A delay locked loop for delaying an input clock to generate an output clock and performing a delay locked operation to lock the input clock and the output clock; And
And a delay locked controller for determining whether the locked state of the delay locked loop is maintained and terminating the delay locked operation. 2. The apparatus of claim 1,
When the locked state continues for a predetermined time or more, generates a delay lock end signal,
Wherein the delay locked operation of the delay locked loop and the operation of the delay locked control are ended in response to the delay locked end signal. 2. The apparatus of claim 1,
A fixed detector for determining whether the delay locked loop is locked and outputting a delay locked signal; And
And a counter for counting a time when the locked state is maintained based on the delay locked signal and outputting a delay locked state signal when the counted value is equal to or greater than a predetermined value. 4. The apparatus of claim 3,
Counts the input clock if the delay locked signal is at a first logic level,
And the reset signal is reset if the delay locked signal is at a second logic level. 4. The apparatus of claim 3, wherein the delay locked loop comprises:
A phase detector for generating an up-down signal based on a phase difference between the input clock and the output clock;
A delay control unit responsive to the up-down signal for outputting a delay control signal for adjusting a delay time of the output clock; And
And a delay line for generating the output clock by delaying the input clock in response to the delay control signal. 6. The apparatus according to claim 5,
Down signal and determines whether or not the signal is locked based on the number of repetitions of the up signal or the down signal of the up-down signal. 6. The apparatus according to claim 5,
And determines whether or not the clock signal is locked based on the change value of the delay control signal. 6. The apparatus of claim 5, wherein the delay locked loop comprises:
A first clock buffer for buffering the input clock to generate a delay clock and a first clock provided as a base clock of the fixed detector; And
Further comprising a second clock buffer for buffering the input clock to generate a second clock provided as a base clock of the delay line,
Further comprising a second clock buffer for buffering the input clock to generate a second clock provided as a base clock of the delay line,
Further comprising a third clock buffer for buffering the output clock of the delay line and generating a third clock to provide to the phase detector,
And a fourth clock buffer identical to the third clock buffer to have the same phase as the third clock,
And the operation of the first clock buffer and the third clock buffer is stopped in response to the delay lock end signal. 6. The apparatus of claim 5, wherein the delay locked loop comprises:
A first clock buffer for buffering the delay line clock to generate a first clock provided as a base clock of the phase detector, the delay controller, and the fixed detector; And
Further comprising a second clock buffer for buffering the delay line clock to generate a second clock provided as an output clock CLK_OUT,
And the operation of the first clock buffer is stopped in response to the delay lock end signal. 1. A semiconductor memory device comprising a plurality of memory cells,
A delay locked loop for delaying an input clock to generate an output clock and performing a delay locked operation to lock the input clock and the output clock;
A delay fixing control unit for determining whether the locked state of the delay locked loop is maintained or not and terminating the delay locked operation; And
And a data output unit for outputting data stored in the plurality of memory cell arrays based on the output clock,
Wherein the delay locked loop and the delay locked control unit are reset and restarted when the operation state of the semiconductor memory device is changed.

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