KR20140124684A - Apparatus and method for performing variably applicable fast fourier transform - Google Patents

Abstract

Disclosed are a fast Fourier transform (FFT) method, and a device thereof. The present statement includes determining an FFT size, the number of butterfly operations, and a memory size for the output of the butterfly operations based on variables applied to a system, and performing FFT by using the determined FFT size, the determined number of the butterfly operations, and the determined memory size.

Description

TECHNICAL FIELD [0001] The present invention relates to a fast Fourier transform apparatus and a method that can be applied to a variable Fourier transform,

The present invention relates to a fast Fourier transform apparatus and method, and more particularly, to a variable Fourier transform apparatus and method.

Fast Fourier Transform (FFT) is a technique for converting a time-varying signal into a frequency-change signal. Inverse Fast Fourier Transform (IFFT) is a technique for converting a frequency-change signal into a time-varying signal.

In order to perform an FFT operation of a high-speed digital signal in real time, a fast Fourier transform operation can be performed by a software implemented in a programmable DSP (Digital Signal Processor) or a dedicated FFT processor. Examples of the transmission technique using the FFT method include wireless LAN, asymmetric digital subscriber line (ADSL), digital audio broadcasting (DAB), and orthogonal frequency division multiplexing (OFDM).

Orthogonal frequency division multiplexing (OFDM) technology, which can be used as a transmission method for digital audio broadcasting, And can be applied to a modulator of a high-speed wireless data communication system due to advantages such as multipath fading.

The basic concept of the OFDM transmission scheme is to increase the data rate by converting serial data sequences into N parallel data sequences and transmitting them on separate subcarriers. At this time, the subcarriers must be properly selected to maintain the orthogonality, and the subcarriers can be generated using the FFT and the IFFT at the transmitting and receiving end.

Therefore, when the OFDM transmission scheme is used in a high-speed mobile environment, calculation using an FFT is indispensable, and an FFT suitable for a mobile channel environment requires a high-performance FFT calculation (e.g., FFT calculation of 1024 points or more).

In addition, FFT is an algorithm for performing DFT (Discrete Fourier Transform) more quickly.

In a wired or wireless communication system, OFDM (Orthogonal Frequency Division Multiplexing) is used. The OFDM scheme requires fast Fourier transform (FFT) of various sizes for signal transmission and reception according to the transmission rate of the system to be used.

Recently, a wireless communication (e.g., Long Term Evolution (LTE) scheme or wired communication (e.g., DVB-C2) scheme requires fast Fourier transform of a larger size.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a Fourier transform method and apparatus capable of actively adjusting a transmission scheme or a transmission efficiency.

Another aspect of the present invention is to control the number of butterfly operations applied to a fast Fourier transform method and the size of a memory associated with the output of each butterfly.

According to one aspect of the present invention, a Fast Fourier Transform (FFT) method determines the FFT size, determines the number of butterfly operations, and outputs the result of the butterfly operation Determining a size of a memory to be used, and performing a fast Fourier transform using the determined FFT size, the number of butterfly operations, and the size of the memory.

According to the present invention, fast Fourier transform can be applied actively and variably.

1 is a block diagram illustrating a fast Fourier transform operation according to an embodiment of the present invention.
2 is a block diagram showing an example of the internal configuration of the stage block.
3 is a flowchart showing an example of a fast Fourier transform method of a fast Fourier transform apparatus.
4 is a block diagram showing an example of a fast Fourier transform apparatus.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Also, in order to clearly illustrate the present invention in the drawings, portions not related to the present invention are omitted, and the same or similar reference numerals denote the same or similar components.

The objects and effects of the present invention can be understood or clarified naturally by the following description, and the purpose and effect of the present invention are not limited by the following description.

The objects, features and advantages of the present invention will become more apparent from the following detailed description. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The stage block of the fast Fourier transform apparatus can be implemented in a pipelining structure so as to perform an FFT operation using input data and precision bits and to modify the FFT operation.

1 is a block diagram illustrating a fast Fourier transform operation according to an embodiment of the present invention. For example, the fast Fourier transform method supports 4k-FFT. Here, the 4k-FFT means "4096-FFT ", and the size of the FFT processed (or the number of subcarriers used for FFT) is 4096.

Referring to FIG. 1, a fast Fourier transform apparatus 100 includes a total of 12 stage blocks 105 to 160 including a butterfly operation.

Here, the Butterfly operation is an operation that is basically used for the operation of the FFT, and the operation related to the real part and the imaginary part used for expressing the complex number is a butterfly operation.

In addition, the fast Fourier transform apparatus 100 includes a bit-reverse (170) block for transforming the bit position of the processed data with respect to the final output calculated through the entire stage block.

However, it is an example according to the present invention that a 12-stage block and a bit-reversed block are included, and the number of blocks is variable according to the butterfly method.

Hereinafter, the name denoted as 'clk / 1' means the number of bits for the signal name / signal mapped in the hardware implementation. That is, 'clk / 1' is input, which means that a 1-bit clk signal is input.

20 'and' in_i / 20 'are input to the FFT unit 100 when' input_en / l 'is input to the FFT unit 100, .

The detailed calculation process of the stage block will be described in detail in FIG.

'S2_re_in / 20' and 's2_im_in / 20', which are the outputs of the first stage 105, are input to the second stage 110.

'S3_re_in / 20' and 's3_im_in / 20', which are the outputs of the second stage 110, are input to the third stage 115.

The outputs of the third stage 115 's4_re_in / 20' and 's4_im_in / 20' are input to the fourth stage 120.

'S5_re_in / 20' and 's5_im_in / 20' which are the outputs of the fourth stage 120 are inputted to the fifth stage 125.

'S6_re_in / 20' and 's6_im_in / 20', which are the outputs of the fifth stage 125, are input to the sixth stage 130.

'S7_re_in / 20' and 's7_im_in / 20' which are the outputs of the sixth stage 130 are input to the seventh stage 135.

'S8_re_in / 20' and 's8_im_in / 20' which are the outputs of the seventh stage 135 are inputted to the eighth stage 140.

'S9_re_in / 20' and 's9_im_in / 20', which are the outputs of the eighth stage 140, are input to the ninth stage 145.

'S10_re_in / 20' and 's10_im_in / 20' which are the outputs of the ninth stage 145 are input to the fifteenth stage 150.

'S11_re_in / 20' and 's11_im_in / 20', which are the outputs of the tenth stage 150, are input to the eleventh stage 155.

'S12_re_in / 20' and 's12_im_in / 20', which are the outputs of the eleventh stage 155, are input to the twelfth stage 160.

'Br_re_in / 20' and 'br_im_in / 20' which are the outputs of the twelfth stage 160 are input to the bit reverse block 170.

'Fft_out_re / 20' and 'fft_out_im / 20' output from the bit reverse block 170 are outputted.

Also, the fast Fourier transform apparatus 100 outputs 'out_en / l' which is an FFT result value.

That is, the fast Fourier transform apparatus 100 receives a complex value in a time domain and outputs complex value data in a frequency domain, which is a result of Fourier transform in a time domain.

In addition, the present invention can easily program implementation specifications of various Fourier transform device systems required for wired / wireless communication and display calculations.

As described above, the present invention can automatically change the structure according to the input of system variables, thereby ensuring maximum performance. By enabling adaptive operation due to variable system variables, interoperability between systems and various signal analysis can be supported.

2 is a block diagram showing an example of the internal configuration of the stage block.

Referring to FIG. 2, each stage block includes a stage block for butterfly operation and blocks (mij_mul and tw_mul) for operation or a truncation block for adjusting the number of bits for hardware implementation.

The odd-numbered stage block outputs s_out_r / 21 and s_out_i / 21 when clk, clk_x, bmux_sel, wadr, radr, wen, s (crnt) _re_in, s (crnt) im_in are input.

The mij_mul block outputs re_out / 21 and im_out / 21 when jmul_sel, s_out_r / 21, and s_out_i / 21 are input.

When re_out / 21 and im_out / 21 are inputted, s (nxt) _re_in and s (nxt) _im_in are output to the truncation block.

On the other hand, s_out_r / 21 and s_out_i / 21 are outputted when clk, clk_x, bmux_sel, wadr, radr, wen, s (crnt) _re_in, s (crnt) im_in are inputted in the even stage block.

The tw_mul block outputs s_mul_re / 21 and s_mul_im / 21 when rom_en and rom_adr, s_out_r / 21 and s_out_i / 21 are input.

The truncation block outputs s (nxt) _re_in and s (nxt) _im_in when s_mul_re / 21 and s_mul_im / 21 are input.

Each of the parameters corresponds to the name and the number of bits of the clock and input / output signals used in the hardware implementation. 'Mij_mul' is a multiplication operation related to the real part and imaginary part in relation to the butterfly operation mentioned above, and 'tw_mul' is also a multiplication operation, but the 'twiddle factor' value is further multiplied.

The stage block 200 may further include a memory 250 for storing or outputting data to be processed in the butterfly operation process.

3 is a flowchart showing an example of a fast Fourier transform method of a fast Fourier transform apparatus.

Referring to FIG. 3, a fast Fourier transform apparatus determines an entire FFT size for a fast Fourier transform method based on a variable applied to a system, determines the total number of stages based on an input signal, The size of the memory is determined (S300).

That is, when the fast Fourier transform apparatus performs the fast Fourier transform operation, when the size of the FFT is changed by changing the data rate or the bandwidth, the number of all stage blocks applied to the fast Fourier transform and the size (size) may be changed, respectively.

Here, the variable applied to the system can be input from outside the system variably according to a request such as a change of the transmission rate or bandwidth to be provided by the system.

For example, the variables applied to the system are variables such as the size adjustment of the FFT. That is, when a service provided by '4096-FFT' receives a value for a bandwidth change as a variable, the size of the FFT may be reduced to '1024' or increased to '8192' as the bandwidth is expanded or contracted.

The fast Fourier transform apparatus performs fast Fourier transform by variably applying the determined FFT size, stage block, or memory (S305).

At this time, depending on the butterfly structure used in each stage, even the fast Fourier transform of the same size, the number of the entire stages to be applied and the memory included in each stage may be different.

With the input variable as a parameter, the fast Fourier transform device can adjust the number of stages or the internal memory size in each stage internally.

4 is a block diagram showing an example of a fast Fourier transform apparatus.

The fast Fourier transform apparatus 400 includes a processor 405 and a memory 410.

The processor 405 may include one or more stage blocks that perform a butterfly operation for fast Fourier transform, and may further include a memory 410 in each stage block.

The processor 405 determines the total FFT size for the fast Fourier transform method based on the parameters applied to the system (for example, the change in the transmission rate or bandwidth to be provided by the system), and calculates the total number of stages And determines the size of the memory used in each stage.

The processor 405 variably applies the determined FFT size, stage block, or memory to perform a fast Fourier transform.

The memory 410 may be located within the stage block and may be resized by the processor 405. [

The memory 410 may store or output the data processed in the butterfly operation in the stage block.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventive concept as defined by the appended claims. But is not limited thereto.

In the above-described exemplary system, the methods are described on the basis of a flowchart as a series of steps or blocks, but the present invention is not limited to the order of the steps, and some steps may occur in different orders or simultaneously . It will also be understood by those skilled in the art that the steps shown in the flowchart are not exclusive and that other steps may be included or that one or more steps in the flowchart may be deleted without affecting the scope of the invention.

Claims (1)

In a Fast Fourier Transform (FFT) method,
Determining an FFT size, determining a number of butterfly operations, and determining a size of a memory to be used for the output of the butterfly operation, based on a variable applied to the system;
And performing a fast Fourier transform using the determined FFT size, the number of butterfly operations, and the size of the memory,
Wherein the performing the fast Fourier transform includes receiving a complex value in a time domain, outputting a complex value in a frequency domain, which is a result of Fourier transform in a time domain,
Wherein the variable applied to the system is a change in the transmission rate or bandwidth to be provided by the system.

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