KR20140109237A - Method and apparatus for analyzing memory architecture - Google Patents

Abstract

A technique relating to a method and an apparatus to analyze the architecture of a multi-bank memory is disclosed. A method to analyze the architecture of a memory consisting of multi-banks comprises the steps of: accessing the memory in a cache line unit in accordance to at least one memory address; calculating operation processing time for data corresponding to at least one memory address by accessing the memory in the cache line unit; and determining the architecture of the memory based on the calculated operation processing time. Therefore, the architecture of the memory can easily be analyzed by sequentially accessing the multi-bank memory using a cache line as a unit, and analyze the pattern of operation processing time. This causes a low buffer drive to be minimized, thereby improving the performance of the overall system.

Description

[0001] METHOD AND APPARATUS FOR ANALYZING MEMORY ARCHITECTURE [0002]

The present invention relates to a memory structure, and more particularly, to a method and apparatus for analyzing the structure of a multi-bank memory.

Modern computer systems are evolving based on multicore and large memory.

For example, CPU manufacturers such as Intel, AMD, ARM, and NVIDIA are launching various processors in a multi-core environment. Intel offers an Xeon E7 processor with 10 cores, an AMD Opteron 6000 series processor with 12 cores, an ARM Cortex-A15 MPcore with 4 cores each for ARM and NVIDIA, and more than 512 cores Tesla is available.

In addition, along with the development of processors, the capacity of memories is also increasing, the speed of approaching, and the price of the memory are increasing. The importance of the level of system software considering characteristics of multi-core and large memory has been increased in accordance with this development direction.

In a multi-core system using a large memory, a multi-bank structure causes a plurality of cores to simultaneously access a memory, causing a low-buffer collision phenomenon, which degrades parallelism and causes interference between threads, It is becoming a factor.

In order to solve this problem at the OS level, it is necessary to accurately analyze the relationship between the bank structure of the physical memory and the page frame managed by the OS, but the research on this problem is insufficient.

According to an aspect of the present invention, there is provided a method of analyzing a structure of a multi-bank memory based on an operation execution time due to a row buffer conflict.

Another object of the present invention is to provide an apparatus for analyzing a structure of a multi-bank memory based on an operation execution time due to a row buffer collision.

According to another aspect of the present invention, there is provided a method of analyzing a structure of a memory including multi-banks, the method comprising the steps of: accessing a memory in units of cache lines according to at least one memory address; Calculating a calculation execution time for data corresponding to at least one memory address by accessing the memory in units of cache lines, and determining a structure of the memory based on the calculated execution execution time.

The step of accessing the memory accesses the memory by a preset number of times based on the first memory address and the second memory address and increases the address by a predetermined address size in the first memory address, You can decide.

Here, the step of accessing the memory may sequentially access the second memory address and the first memory address, and then access the first memory address and the second memory address in turn.

Here, the predetermined address size may be 64B.

Here, the operation execution time may be based on a time for reading data included in a row corresponding to the first memory address and the second memory address through a row buffer in a row unit.

Here, the step of determining the structure of the memory may determine a row buffer conflict based on a pattern in which an operation execution time varies.

Here, the step of determining the structure of the memory may determine that a row buffer conflict occurs in the first memory address and the second memory address corresponding to the point at which the operation execution time increases.

Here, the step of determining the structure of the memory may determine that the first memory address and the second memory address where the row buffer conflict occurs are mapped to different memory rows.

According to another aspect of the present invention, there is provided an apparatus for analyzing a memory structure, comprising: an access request unit for requesting access to a memory in units of cache lines according to at least one physical memory address; And a memory structure determining unit for determining a structure of a memory based on the computed computation time. The memory structure determining unit determines a structure of the memory based on the calculated computation time.

The method and apparatus for analyzing the memory structure according to the present invention can easily analyze the structure of the memory by sequentially accessing the multi-bank memory in units of cache lines and analyzing patterns of operation execution time.

Also, by analyzing the memory structure, it is possible to improve the overall system performance by minimizing the low buffer impulse.

1 is a conceptual diagram for explaining a structure of a memory to be analyzed according to an embodiment of the present invention.
2 is a conceptual diagram for explaining the operation of the memory according to the embodiment of the present invention.
3 is an exemplary diagram illustrating an algorithm for performing a method of analyzing a memory structure according to an embodiment of the present invention.
4 is a flowchart illustrating a method of analyzing a memory structure according to an embodiment of the present invention.
FIG. 5 is a block diagram illustrating an apparatus for analyzing a memory structure according to an embodiment of the present invention. Referring to FIG.
FIG. 6 is a diagram illustrating a simulation result through analysis of a memory structure according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

The term " bank memory " used in the present invention means a memory having a structure in which a plurality of replaceable physical memories are mapped in the same address space, and a 'bank' And the memory space of the microprocessor as eight banks can be extended to 500,000 bytes. Also, a channel is composed of a rank, and each rank is made up of banks.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram for explaining a structure of a memory to be analyzed according to an embodiment of the present invention.

Referring to FIG. 1, a plurality of physical memories are connected to a memory, which is a unit in which a memory controller 110 shares an address / command bus and a data bus. The physical memory is composed of a plurality of chips 120, and each memory chip 120 is composed of a plurality of banks 121. That is, according to FIG. 1, the physical memory is constituted by one dual in-line memory module (DIMM) directly connected to the substrate.

In addition, the banks 121 of each chip 120 are configured with ranks grouped into a group of chips in order to maximize the data bus size.

One bank 121 consists of a number of rows 123, which is the unit through which the processor accesses the memory. When the processor accesses the memory, the bank 121 is determined by the controller based on the memory address and looks for the row 123 of the bank. And transmits all the data of the determined row to the row buffer 125. [

The memory has an address register and an address counter for transferring addresses, a control logic for controlling the execution of a given operation, a bank controller for controlling the rows and columns of the banks, There are row / column latches and decoders that determine the row / column to read.

In this architecture, when the processor reads data in memory, the order of accessing the memory is as follows.

The processor requests data to the main memory using the memory address (S1).

Based on the memory address passed by the processor, the memory determines the bank to be requested by the memory controller 110 and transfers the memory address to the corresponding bank (S2).

In the bank, the corresponding row of the address is activated based on the received address (S3).

The data of the activated bit line is transmitted to the row buffer 125 (S4).

After receiving the data, the row buffer 125 confirms the bit line information of the memory address (S5).

The bank controller checks the column address and activates the corresponding column (S6).

The bank sends the data in the cell corresponding to the activated row and column address to the output pin through the low buffer, and the process reads the data after confirming the data output pin of the data bus (S7).

The bank ends the data output (S8).

When the processor repeatedly requests data in the memory, in the course of performing the above procedure, when a read / write operation is performed again on the row in which data was previously read, the corresponding row of the address is activated based on the address received from the bank, The process of S3 to S5 is not necessary. This is referred to as a low buffer hit, and the execution time can be saved by the time of S3 to S5.

However, when the operation is performed on a row other than the row in which the data was previously read, all the processes of S1 to S8 must be performed, thereby activating the row, and storing the data existing in the existing row buffer 125 in the cell An additional pre-charging cost is incurred. This is called a low buffer miss or a low buffer collision. A run time of 5 to 22 ns (nano second) for a low buffer hit, and 45 to 50 nano (second nano seconds) for a low buffer miss. Therefore, the performance of the overall system can be improved by minimizing the row buffer miss.

Therefore, in an environment where multiple tasks access simultaneously to a memory in a multi-core environment, tasks are accessed by other rows in the same bank, thereby reducing the memory bottleneck, thereby reducing the processor latency and memory access time Can improve the overall performance of the system.

2 is a conceptual diagram for explaining the operation of the memory according to the embodiment of the present invention.

The memory is transited to an idle state (S210) when the power is turned on. When the row address is determined, the memory transitions to a row activate state (S230). When the row address is a row buffer hit, (S240) and a write operation (S250).

In the case of a row buffer miss, precharging (S260) is performed and transition to the row activation state (S230) is performed, followed by reading (S240) and writing (S250).

After all operations are completed, transition is made to the standby state (S210) again through the precharged state (S260), and the auto refresh state (S220) and the standby state (S210 ).

3 is an exemplary diagram illustrating an algorithm for performing a method of analyzing a memory structure according to an embodiment of the present invention.

Line 1 shows the start address (start_addr) and size (size) of the memory for analyzing the memory structure.

Line 2 represents declaring a memory address variable that can access physical memory for analyzing the memory structure in units of cache line size. The memory address variable cl_1 is initialized with the start address (start_addr) of the memory, and the start address (start_addr) of the memory is maintained to analyze the memory structure.

Line 3 represents declaring another memory address variable that can access the physical memory for analyzing the memory structure in units of cache line size. Also, the memory address variable cl_2 is initialized to a memory address corresponding to a second cache line which is increased in a unit of the cache line size from the start address (start_addr) of the memory.

Line 4 performs an initialization operation to remove the area corresponding to the memory size (size) from the memory start address (start_addr), which is an area for analyzing the memory structure, to assure the memory structure analysis.

Lines 5 to 14 perform an operation that can calculate an operation execution time for analyzing the memory structure.

Line 5, line 13 and line 14 indicate that the memory structure for analysis is operated to access the physical memory in units of cache lines, in which the memory address variable cl_2 increases in units of cache lines, It is judged whether the value of the memory address variable cl_2 satisfies the condition that the value of the memory start address cl_1 is smaller than the sum of the memory size for analysis.

Line 6 indicates starting the timer to calculate the operation execution time.

Line 7, line 8 and line 11 allow the occurrence of noise such as bus contention or delay between instructions to access the physical memory repeatedly a certain number of times so as not to affect the analysis of the memory structure. In FIG. 3, .

Line 9 indicates that the value of the physical memory corresponding to the cl_2 memory address variable having a memory address different from that of the memory to be analyzed is allocated to the physical memory corresponding to the memory start address variable by increasing an arbitrary value. Therefore, the corresponding physical memory is accessed using the memory address variable cl_2 to obtain the data value, and the corresponding physical memory is accessed using the memory address variable cl_1 to store the new value.

Line 10 indicates that an arbitrary value is incremented to the value of the data of the physical memory corresponding to the memory address variable cl_1 and allocated to the physical memory corresponding to the memory address variable cl_2. Therefore, access to the physical memory corresponding to the memory address variable cl_1 occurs, and access to the physical memory corresponding to the memory address variable cl_2 occurs again.

By performing line 9 and line 10, it can be ensured in the central processing unit (CPU) to identify the row buffer in order to access the data in the memory corresponding to the memory address variable cl_1 and the memory address variable cl_2.

The line 11 confirms the conditions for repeatedly accessing the physical memory by the preset number of times. If the condition is satisfied, the process proceeds to the line 12 to stop the timer for measuring the operation execution time.

Line 13 may increment the memory address variable cl_2 by the size of the cache line and proceed to line 6 to analyze the structure of the memory.

In summary, the algorithm of FIG. 3 alternately accesses the physical memory corresponding to the memory address variable cl_1 for managing the start address of the memory to analyze the structure and the memory address variable cl_2 for each cache line, The structure of the memory can be analyzed on the basis that the operation execution time is changed according to the feature of transferring data to the row buffer in units of rows.

4 is a flowchart illustrating a method of analyzing a memory structure according to an embodiment of the present invention.

The memory is accessed in units of cache lines according to at least one memory address (S410).

A memory start address, a memory end address, or memory size information is required to access the memory according to a memory to be analyzed, and at least one memory address variable in a cache line unit can be set to access the memory in units of cache lines, Memory structure analysis can be performed by accessing the physical memory corresponding to the memory address variable by increasing the memory address variable in units of cache lines.

The memory address variable may be a first memory address variable for managing a memory start address to be analyzed, and a second memory address variable for increasing a cache line unit and analyzing a memory structure. That is, the second memory address can be determined by accessing the memory by a preset number of times based on the first memory address and the second memory address, and increasing the address by a predetermined address size in the first memory address. Here, the first memory address variable means the memory address variable cl_1 described above in FIG. 3, and the second memory address variable can mean the memory address variable cl_2 described in FIG. Also, the preset address size may be 64B.

The operation execution time for data corresponding to at least one memory address is calculated by accessing the memory in units of cache lines (S430).

In order to analyze the memory structure, a computation that can cause a row buffer collision is performed and the computation time is calculated accordingly.

And performs an operation of alternately accessing the physical memory corresponding to the first memory address variable and the second memory address variable so that a row buffer conflict may occur. Therefore, the operation execution time may be based on the time of reading the data included in the row corresponding to the first memory address and the second memory address through the row buffer in units of rows.

In order to ensure that the data in the physical memory corresponding to the first memory address variable and the second memory address variable is confirmed in the low buffer 125 in the central processing unit (CPU), the first memory address variable and the second memory address You can add operations to alternate accesses to the physical memory corresponding to the variable in a different order.

The structure of the memory is analyzed based on the computed execution time (S450).

That is, the calculated operation execution time is compared with the operation execution time calculated for the other memory address, and the structure of the memory can be analyzed by determining whether the low buffer conflict occurs for the corresponding memory address.

Specifically, the row buffer conflict can be determined based on a pattern in which an operation execution time varies. For example, it can be determined that a low buffer conflict occurs in the first memory address and the second memory address, and it can be determined that the first memory address and the second memory address in which the row buffer conflict occurs are mapped to different memory rows .

FIG. 5 is a block diagram illustrating an apparatus for analyzing a memory structure according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 5, an apparatus 500 for analyzing a memory structure according to an embodiment of the present invention includes an access request unit 510, a buffer conflict check unit 520, and a memory structure determination unit 530.

The access request unit 510 may request access to the memory in units of cache lines according to at least one physical memory address.

Specifically, the access request unit 510 accesses the memory by a preset number of times based on the first memory address and the second memory address, increases the first memory address by a preset address size, You can decide. Here, the preset address size may be 64B.

In addition, the access request unit 510 sequentially accesses the second memory address and the first memory address, and sequentially accesses the first memory address and the second memory address.

The buffer collision checking unit 520 may access the memory in units of cache lines to calculate an operation execution time for data corresponding to at least one physical memory address. Here, the operation execution time may be based on a time for reading data included in a row corresponding to the first memory address and the second memory address through the row buffer in a row unit.

The memory structure determination unit 530 may determine the structure of the memory based on the computed execution time. In detail, the memory structure determination unit 530 may determine a row buffer conflict based on a pattern in which an operation execution time varies. In addition, the memory structure determination unit 530 may determine that a row buffer conflict occurs in the first memory address and the second memory address corresponding to the point at which the operation execution time increases, And the second memory address are mapped to different memory rows.

Although each component of the apparatus 500 for analyzing a memory structure according to an embodiment of the present invention has been described as a component for convenience of description, at least two of the components may be combined into one component, May be divided into a plurality of constituent parts to perform the functions and the case of the integrated and separate embodiments of each constituent part is also included in the scope of the present invention unless the essence of the present invention is satisfied.

FIG. 6 is a diagram illustrating a simulation result through analysis of a memory structure according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a result of executing a memory analysis tool in an IBM X3650 M2 system with 16GB DDR3 memory using an Intel XEON x5570 processor and one node.

The system verified in the present invention is composed of a total of three channels, each channel having four ranks, one rank being composed of eight banks. Each bank has 32K rows, and each row has a size of 4KB.

The X-axis represents the number of repetitions, and the Y-axis represents the operation execution time result. The address of the memory can be found on the X axis, which corresponds to the initial value of the memory address variable cl_2 + 64 times the number of iterations (the number of memory address increments of cl_2). For example, assuming that the initial value of the memory address variable cl_2 is 100, if it is repeated 100 times (when the memory address of cl_2 is repeatedly increased 100 times), the address becomes 6500. Referring to FIG. 6 (d), the memory address variable cl_2 is repeatedly increased by 2 million times to increase the address of the memory address variable cl_2. If the execution time is 2150us or more, which indicates a larger execution time than the execution time of about 1950us, which occupies most of the Y axis, it can be seen that the address is the address where the low buffer conflict occurred.

Referring to FIG. 6 (a), it can be seen that the execution time of one of the three consecutive addresses is always high. It can be determined that a low buffer conflict has occurred. The system used for the analysis is composed of three channels, and based on the result of the execution time, it can be seen that the channel interleaving of the system used for the analysis is performed in units of cache lines have.

Referring to FIG. 6 (b), the result of the calculation of the execution time of the entire 128 KB memory area is shown in FIG. 6 (a) of FIG. 64. Accordingly, have.

6 (c) to 6 (b) are repeated in units of 96 KB, so that it can be determined that the bank interleaving is made up of eight banks, and the bank interleaving is configured in units of three rows . Also, rank interleaving is performed on the basis that the case of FIG. 6 (b) occurs 32 times in the total memory of 3 MB, and the case of FIG. 6 (d) It can be determined that the process is performed in units of 3 MB.

The method and apparatus for analyzing a memory structure according to an embodiment of the present invention can easily analyze a structure of a memory by sequentially accessing a multi-bank memory in units of cache lines and analyzing a pattern of operation execution time .

Also, by analyzing the memory structure, it is possible to improve the overall system performance by minimizing the low buffer impulse.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

110: memory controller 120: chip
121: bank 123: low
125: Low buffer
500: memory structure analysis apparatus 510: access request unit
520: buffer collision checking unit 530: memory structure judging unit

Claims (16)

1. A method for analyzing a structure of a multi-bank memory,
Accessing the memory in units of cache lines according to at least one memory address;
Accessing the memory in units of the cache lines to calculate an operation execution time for data corresponding to the at least one memory address;
And determining a structure of the memory based on the calculated operation execution time. The method according to claim 1,
The step of accessing the memory
Accessing the memory by a predetermined number of repetitions based on the first memory address and the second memory address,
Wherein the second memory address is determined by incrementing the first memory address by a predetermined address size. The method of claim 2,
The step of accessing the memory
Accessing the second memory address and the first memory address in turn, and then accessing the first memory address and the second memory address in turn. The method of claim 2,
Wherein the predetermined address size is 64B. The method according to claim 1,
The operation execution time is
Wherein the first memory address and the second memory address are based on a time that the data included in a row corresponding to the first memory address and the second memory address are read through the row buffer in a row unit basis. The method of claim 5,
Wherein the step of determining the structure of the memory comprises:
And determining a row buffer conflict based on a pattern in which the operation execution time varies. The method of claim 6,
Wherein the step of determining the structure of the memory comprises:
And determining that the row buffer conflict occurs at the first memory address and the second memory address corresponding to a point at which the operation execution time increases. The method of claim 7,
Wherein the step of determining the structure of the memory comprises:
And determining that the first memory address and the second memory address where the row buffer conflict occurs are mapped to different memory rows. 1. An apparatus for analyzing a structure of a multi-bank memory, comprising:
An access request unit for requesting access to the memory in units of cache lines according to at least one physical memory address;
A buffer conflict check unit accessing the memory in units of the cache lines and calculating an operation execution time for data corresponding to the at least one physical memory address;
And a memory structure determining unit for determining a structure of the memory based on the calculated operation execution time. The method of claim 9,
The access request unit,
Accessing the memory by a preset number of times based on a first memory address and a second memory address,
Wherein the second memory address is determined by incrementing the first memory address by a predetermined address size. The method of claim 9,
The access request unit,
Accesses the second memory address and the first memory address in turn, and then sequentially accesses the first memory address and the second memory address. The method of claim 10,
Wherein the predetermined address size is 64B. The method of claim 9,
The operation execution time may be,
Wherein the first memory address and the second memory address are based on a time of reading data included in a row corresponding to the first memory address and the second memory address through a row buffer in units of rows. 14. The method of claim 13,
The memory structure determination unit determines,
And determining a row buffer conflict based on a pattern in which the operation execution time varies. 15. The method of claim 14,
The memory structure determination unit determines,
And determines that the row buffer conflict has occurred in the first memory address and the second memory address corresponding to a point at which the operation execution time increases. 16. The method of claim 15,
The memory structure determination unit determines,
And determines that the first memory address and the second memory address in which the row buffer conflict occurs are mapped to different memory rows.

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