KR20140097762A - Thin film transistor substrate and method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate capable of adjusting permeability by forming the width of bent portions of R, G, and B sub pixels and a method for manufacturing the same. The thin film transistor substrate of the present invention comprises a plurality of R, G, and B sub pixels arranged in a matrix form on a substrate, wherein each of the sub pixels has a first slope for the upper portion and the lower portion to be symmetry relative to the central portion. Each sub pixel includes a bent portion protruding to have a second slope greater than the first slope at the central portion, wherein the width of the bent portion is different for each of the R, G, and B sub pixels.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate capable of reducing a difference in transmittance of each sub pixel and a method of manufacturing the same.

(PDP), Electro Luminescent Display (ELD), Vacuum Fluorescent (VFD), and the like have been developed in recent years in response to the demand for display devices. Display) have been studied, and some of them have already been used as display devices in various devices.

The liquid crystal display device includes a color filter substrate on which a color filter is formed, a thin film transistor substrate on which a thin film transistor is formed, and a liquid crystal layer formed between the color filter substrate and the thin film transistor substrate. Specifically, in the thin film transistor substrate, a gate wiring and a data wiring cross each other to define a sub pixel region, and a thin film transistor is formed in each sub pixel region. The color filter formed on the color filter substrate is formed so as to correspond to each sub pixel region, and the color light corresponding to each color filter is realized as the thin film transistor is driven.

In this case, since the light transmittance differs for each color filter, in the case of the liquid crystal display device of the fringe field mode, the width or the interval of the pixel electrode or the common electrode formed in the slit shape may be formed differently, have.

In this case, the area of the pixel electrode and the common electrode overlapping each other with the insulating film interposed therebetween is different for each sub-pixel, and Cst (storage capacitance) and Clc (liquid crystal capacitance) in the following equation (1) are different. Accordingly, the kickback voltage (? Vp) of the R, G, and B sub-pixels are different from each other.

Therefore, after-image and flicker occur, and a color shift occurs due to the luminance deviation of the sub-pixel.

SUMMARY OF THE INVENTION The present invention has been conceived in order to solve the above problems, and it is an object of the present invention to provide a liquid crystal display device capable of controlling the transmittance by forming the widths of the bent portions of the R, G, and B sub-pixels differently when the central region of the R, And a method of manufacturing the same.

According to an aspect of the present invention, there is provided a thin film transistor substrate including a plurality of R, G, and B sub-pixels arranged in a matrix on a substrate, And a bent portion protruding from the central portion to have a second inclination larger than the first inclination, wherein the width of the bent portion is different for each of the R, G, and B sub-pixels.

In order to accomplish the same object, a method of manufacturing a thin film transistor substrate according to the present invention includes forming R, G and B sub-pixels so as to be arranged in a matrix on a substrate, And the widths of the bent portions are formed to be different from one another for each of the R, G, and B sub-pixels.

And the width of the bent portion of the G sub-pixel is wider than the width of the bent portion of the R sub-pixel and the width of the bent portion of the B sub-pixel.

The width of the bent portion of the R sub-pixel is formed to be wider than the width of the bent portion of the B sub-pixel.

Forming the sub-pixel includes: forming a thin film transistor on the substrate; Forming first and second protective films in order on the substrate so as to cover the thin film transistors; Forming a common electrode on the second protective film; Forming a third protective film on the common electrode; And forming a pixel electrode that overlaps the common electrode with the third protective film interposed therebetween, and selectively removes the first, second, and third protective films to connect to the exposed thin film transistor.

The thin film transistor substrate of the present invention and the method of fabricating the same according to the present invention have different bend widths for R, G and B sub-pixels. Particularly, the width of the bent portion of the G sub-pixel having the widest transmittance and the width of the bent portion of the B sub-pixel having the widest width and the lowest transmittance are formed to be the narrowest, and the display quality deterioration due to the difference in transmittance between the R, .

1 is a plan view of a thin film transistor substrate of the present invention.
2 is a cross-sectional view taken along the line I-I 'in Fig.
3A to 3E are plan views showing a method for manufacturing a thin film transistor substrate according to the present invention.
4A to 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the present invention.

Hereinafter, a thin film transistor substrate and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a thin film transistor substrate according to the present invention, and Fig. 2 is a cross-sectional view taken along line I-I 'of Fig.

As shown in FIGS. 1 and 2, the thin film transistor substrate of the present invention includes a plurality of R, G, and B sub-pixels arranged in a matrix on a substrate 100. In this case, the R, G, and B sub-pixels include a pixel electrode 190 and a common electrode 170 that are overlapped with each other with the third protective film 180 therebetween to generate a fringe electric field. The light transmittance through the color filter formed on the color filter substrate (not shown) is changed corresponding to each sub-pixel by the fringe electric field to realize an image.

However, since the light transmittance differs for each color filter in general, there arises a problem that the display quality is lowered due to the difference in transmittance of the sub-pixels. Therefore, the thin film transistor substrate of the present invention can reduce the difference in transmittance of the R, G, and B sub-pixels by forming the widths W2, W3, and W1 of the bent portions of the central regions of the R, G, .

Specifically, in the thin film transistor substrate of the present invention, a thin film transistor is formed on a substrate 100 in a sub pixel region defined by intersecting a gate line GL and a data line DL with a gate insulating film 120 interposed therebetween . In the thin film transistor, a pixel signal supplied to the data line DL is charged and held in the pixel electrode 190 in response to a scan signal supplied to the gate line GL. To this end, the thin film transistor includes a gate electrode 110a, a source electrode 140a, a drain electrode 140b, and a semiconductor layer 130.

The gate electrode 110a may protrude from the gate line GL to be supplied with a scan signal from the gate line GL and be defined as a part of the gate line GL. The gate electrode 110a and the gate wiring GL may be formed of Al / Cr, Al / Mo, Al / Nd / Cr, Mo / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, , Al alloy / Mo alloy, Mo alloy / Al alloy, Mo / Al alloy, or the like, or a structure in which a layer of Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Layer structure of the same metal material.

The semiconductor layer 130 includes an active layer 130a and an ohmic contact layer 130b stacked in this order on the gate electrode 110a with the gate insulating layer 120 interposed therebetween. The ohmic contact layer 130b serves to reduce electrical contact resistance between the source and drain electrodes 140a and 140b and the active layer 130a.

The source electrode 140a is connected to the data line DL and receives the pixel signal of the data line DL. The drain electrode 140b is formed to face the source electrode 140a with the channel of the semiconductor layer 130a interposed therebetween to supply the pixel electrode 190 with a pixel signal from the data line DL.

At this time, the data line DL is formed in a bent shape such that the sub-pixel has two domains, the upper and lower portions having a first slope and being symmetrical with respect to the central portion. Particularly, a bent portion protruding to have a second inclination larger than the first inclination is further formed at the central portion, thereby preventing light spots and white spots.

The first and second protective films 150 and 160 are sequentially formed to cover the thin film transistor. The first passivation layer 150 may be formed of an inorganic insulating material and the second passivation layer 160 may be formed of an organic insulating material.

A common electrode 170 in the form of a tubular electrode is formed on the second protective film 160. A third protective layer 180 is formed to cover the common electrode 170 and a slit-shaped pixel electrode 190 is formed on the protective layer 180. The pixel electrode 190 is connected to the drain electrode 140b through a drain contact hole 180a formed by selectively removing the first, second, and third protective layers 150, 160, and 180. The common electrode 170 and the pixel electrode 190 overlapping the third protective film 180 form a fringe electric field.

In this case, the pixel electrode 190 may be formed in the form of a tubular electrode on the second protective film 160, and the common electrode 170 may be formed in the form of a slit on the third protective film 180. In this case, the pixel electrode 190 is connected to the drain electrode 140b through a drain contact hole formed by selectively removing only the first and second protective films 150 and 160.

The common electrode 170 and the pixel electrode 190 may be formed of at least one selected from the group consisting of tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (Indium Tin Zinc Oxide: ITZO) or the like. In particular, the common electrode 170 and the pixel electrode 190 have a first inclination such that the upper and lower portions are symmetrical with respect to the central portion as the data line DL, and a second inclination Respectively.

That is, the R, G, and B subpixels of the present invention are also formed by the data line DL, the common electrode 170, and the pixel electrode 190 so that the first and second slopes are symmetrical with respect to the center, And a bent portion protruded from the center portion to have a second inclination larger than the first inclination. The widths W2, W3 and W1 of the bent portions of the R, G and B sub-pixels are different from each other.

Generally, the liquid crystal molecules corresponding to the bent portions are rotated unstably due to electric fields in different directions, and an electric field distortion occurs. Therefore, as the width of the bent portions is wider, the transmittance of the sub-pixels is lowered. Therefore, in the thin film transistor substrate of the present invention, the width W3 of the bent portion of the G sub-pixel having the highest transmittance among the R, G, and B sub-pixels is wider than the width W2, W1 of the bent portion of the R and B sub-pixels. Since the transmittance of the R sub-pixel is higher than that of the B sub-pixel, the width W2 of the bent portion of the G sub-pixel is wider than the width W1 of the bent portion of the B sub-pixel.

The thin film transistor substrate according to the present invention can prevent the deterioration of display quality due to the difference in transmittance of the R, G, and B sub-pixels by controlling the width of the bent portion. Particularly, when the width of the bent portion is adjusted as described above, the area where the electric field distortion phenomenon of the sub-pixel is generated without fluctuation of Cst (storage capacitance) and Clc (liquid crystal capacitance) Can be reduced.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are plan views showing a method for manufacturing a thin film transistor substrate according to the present invention. 4A to 4E are cross-sectional views showing a method of manufacturing the thin film transistor substrate of the present invention, and FIGS. 3A to 3E show I-I '.

First, as shown in FIGS. 3A and 4A, a thin film transistor is formed on a substrate 100. The thin film transistor is formed in each sub pixel region defined by the gate line GL and the data line DL intersecting each other with the gate insulating film 120 interposed therebetween.

Specifically, a gate metal layer is formed on a substrate 100 by a deposition method such as a sputtering method, and then a gate metal layer is patterned to form a gate electrode 110a and a gate wiring GL. A gate insulating layer 120 is formed on the entire surface of the substrate 100 including the gate electrode 110a and the gate line GL by using a material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like.

In this case, the gate metal layer may be formed of Al / Cr, Al / Mo, Al (Nd) / Al, Al / Nd / Cr, Mo / Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, , A Mo alloy / Al alloy, a Mo / Al alloy, or the like, or a single layer structure of Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy or Al alloy .

Next, a semiconductor layer 130 having a structure in which an active layer 130a and an ohmic contact layer 130b are sequentially stacked on the gate insulating layer 120 is formed, and a front surface of the gate insulating layer 120 including the semiconductor layer 130 A data metal layer is formed. Then, the source and drain electrodes 140a and 140b and the data line DL are formed by patterning the data metal layer.

The data metal layer is made of Al / Cr, Al / Mo, Al (Nd) / Al, Al / Nd / Cr, Mo / Al , Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy, Mo alloy / Al alloy, Mo / Al alloy, etc., or may have a single layer structure of Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, .

In particular, the data line DL is formed in a bent shape such that the sub-pixel has two domains, the upper and lower portions having a first slope and being symmetrical with respect to the central portion. Further, a bent portion protruding to have a second inclination larger than the first inclination is further formed at the central portion, thereby preventing light spots and white spots.

The source electrode 140a protrudes from the data line DL and the drain electrode 140b is formed apart from the source electrode 140a. The ohmic contact layer 130b corresponding to the spacing between the source and drain electrodes 140a and 140b is removed to form a channel.

Next, as shown in FIGS. 3B and 4B, first and second protective films 150 and 160 are formed on the entire surface of the gate insulating film 120 so as to cover the TFT. At this time, it is preferable that the first protective film 150 is formed of an inorganic insulating material and the second protective film 160 is formed of an organic insulating material. Then, the first and second protective films 150 and 160 are selectively removed to form a drain contact hole pattern (not shown) exposing the drain electrode 140b of the thin film transistor.

As shown in FIGS. 3C and 4C, on the entire surface of the second passivation layer 160, a layer of tin oxide (ITO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc A transparent conductive material such as indium tin oxide (ITO) is deposited and patterned to form a common electrode 170 in the form of a tubular electrode.

3D and 4D, a third protective film 180 is formed to cover the common electrode 170, and then the third protective film 180 is selectively removed to correspond to a drain contact hole pattern (not shown) The drain contact hole 180a is formed in the region where the drain contact hole 180a is formed. 3E and 4E, the transparent conductive material is deposited on the entire surface of the third passivation layer 180 including the drain contact hole 180a and patterned to form the slit-shaped pixel electrode 190. Next, as shown in FIG.

The pixel electrode 190 is connected to the drain electrode 140b through the drain contact hole 180a and overlaps the common electrode 170 with the third protective film 180 therebetween to form a fringe electric field. In this case, the common electrode 170 and the pixel electrode 190 may have a first slope such that the upper and lower portions are symmetrical with respect to the center portion as the data line DL, and a second slope larger than the first slope at the central portion And has a protruding bent portion.

That is, the R, G, and B subpixels of the present invention are also formed by the data line DL, the common electrode 170, and the pixel electrode 190 so that the first and second slopes are symmetrical with respect to the center, And a bent portion protruded from the center portion to have a second inclination larger than the first inclination. The widths W2, W3 and W1 of the bent portions of the R, G and B sub-pixels are different from each other.

Generally, the liquid crystal molecules corresponding to the bent portions are rotated unstably due to electric fields in different directions, and an electric field distortion occurs. Therefore, as the width of the bent portions is wider, the transmittance of the sub-pixels is lowered. Therefore, in the thin film transistor substrate of the present invention, the width W3 of the bent portion of the G sub-pixel having the highest transmittance among the R, G, and B sub-pixels is wider than the width W2, W1 of the bent portion of the R and B sub-pixels. Since the transmittance of the R sub-pixel is higher than that of the B sub-pixel, the width W2 of the bent portion of the G sub-pixel is wider than the width W1 of the bent portion of the B sub-pixel.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

100: substrate 110a: gate electrode
120: gate insulating film 130: semiconductor layer
130a: active layer 130b: ohmic contact layer
140a: source electrode 140b: drain electrode
150: first protective film 160: second protective film
170: common electrode 180: third protective film
180a: drain contact hole 190: pixel electrode

Claims (8)

A plurality of R, G, and B sub-pixels arranged in a matrix on a substrate,
Each of the sub-pixels has a first slope such that the upper and lower portions are symmetrical with respect to a center portion,
And a bent portion protruding from the central portion to have a second inclination larger than the first inclination,
Wherein the width of the bent portion is different for each of the R, G, and B sub-pixels. The method according to claim 1,
And the width of the bent portion of the G sub-pixel is wider than the width of the bent portion of the R sub-pixel and the width of the bent portion of the B sub-pixel. 3. The method of claim 2,
And the width of the bent portion of the R sub-pixel is wider than the width of the bent portion of the B sub-pixel. The method according to claim 1,
Wherein the sub-pixel includes a thin film transistor formed on a sub-pixel region defined by a gate wiring and a data wiring crossing over the substrate with a gate insulating film interposed therebetween;
First and second protective films sequentially formed on the substrate to cover the thin film transistor;
A common electrode formed on the second protective film;
A third protective layer formed on the common electrode; And
And a pixel electrode overlapping the common electrode with the third protective film interposed therebetween and connected to the exposed thin film transistor by selectively removing the first, second, and third protective films. . Forming R, G, and B sub-pixels to be arranged in a matrix on the substrate,
The R, G, and B sub-pixels have bends in the central region,
Wherein the width of the bent portion is different for each of the R, G, and B sub-pixels. 6. The method of claim 5,
Wherein the width of the bent portion of the G sub-pixel is greater than the width of the bent portion of the R sub-pixel and the width of the bent portion of the B sub-pixel. The method according to claim 6,
And the width of the bent portion of the R sub-pixel is larger than the width of the bent portion of the B sub-pixel. 6. The method of claim 5,
Forming the sub-pixel includes: forming a thin film transistor on the substrate;
Forming first and second protective films in order on the substrate so as to cover the thin film transistors;
Forming a common electrode on the second protective film;
Forming a third protective film on the common electrode; And
And forming a pixel electrode overlapping the common electrode with the third protective film therebetween and selectively removing the first, second, and third protective films to connect to the exposed thin film transistor. Wherein said method comprises the steps of:

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