KR20140081954A - Data storage device and processing method for error correction code thereof - Google Patents

Data storage device and processing method for error correction code thereof Download PDF

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Publication number
KR20140081954A
KR20140081954A KR1020120150167A KR20120150167A KR20140081954A KR 20140081954 A KR20140081954 A KR 20140081954A KR 1020120150167 A KR1020120150167 A KR 1020120150167A KR 20120150167 A KR20120150167 A KR 20120150167A KR 20140081954 A KR20140081954 A KR 20140081954A
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South Korea
Prior art keywords
data
memory device
code
error correction
correction code
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KR1020120150167A
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Korean (ko)
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엄기표
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에스케이하이닉스 주식회사
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Priority to KR1020120150167A priority Critical patent/KR20140081954A/en
Publication of KR20140081954A publication Critical patent/KR20140081954A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The present invention relates to a data storage apparatus, and more particularly, to a method of processing an error correction code in a data storage apparatus. A method of processing an error correction code of a data storage device according to an embodiment of the present invention includes: receiving data from a host device; Performing an error correcting code encoding operation on the received data; And storing parity data generated as a result of the error correction code encoding and the received data in a buffer memory device.

Description

[0001] DESCRIPTION [0002] DATA STORAGE DEVICE AND PROCESSING METHOD FOR ERROR CORRECTION CODE THEREOF [

The present invention relates to a data storage device, and more particularly, to a method of processing an error correction code in a data storage device.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use a data storage device that utilizes a memory device. The data storage device is used as a main storage device or an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because it has no mechanical driving part, has very high access speed of information and low power consumption. A data storage device having such advantages includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, and a solid state drive (SSD).

In general, the path through which information is transmitted can be defined as a channel. When information is transmitted using wireless communication, a channel is an air through which electromagnetic waves pass, and when information is transmitted using wired communication, a channel is a transmission line through which information is transmitted.

The process of storing data by the data storage device and reading the stored data from the data storage device may also be defined as a channel. In this case, the channel may be a time lapse from the moment the data storage device stores the data until the stored data is read from the data storage device. Also, the channel in this case may be a physical path where the data storage device stores data and reads the stored data from the data storage device.

Data may be corrupted while data is being transmitted through the channel. That is, an error may occur in the data while the data is transmitted through the channel. Researches on an apparatus and a method for detecting an error generated in data and recovering the original data by eliminating the detected error are progressing steadily.

The process of generating transmission data by adding an error correction code (ECC) to the data before transmitting the data is called error correction code encoding. The process of separating the error correction code and data added from the received transmission data after receiving the transmission data and restoring the original data is referred to as error correction code decoding.

Depending on the error correction code, the time consumed in the error correcting code encoding operation and the error correcting code decoding operation may vary. However, even if any error correction code is used, the data processing speed of the data storage device is inevitably slowed down due to the time consumed to process the error correction code.

An embodiment of the present invention is to provide a data storage device and its error correction code processing method capable of reducing the time consumed in an error correcting code encoding operation.

A method of processing an error correction code of a data storage device according to an embodiment of the present invention includes: receiving data from a host device; Performing an error correcting code encoding operation on the received data; And storing parity data generated as a result of the error correction code encoding and the received data in a buffer memory device.

In an embodiment, an error correcting code encoding operation is performed on the received data immediately after receiving the data from the host apparatus.

A data storage device according to an embodiment of the present invention includes a nonvolatile memory device; A buffer memory device configured to buffer data to be stored in the nonvolatile memory device; And an error correction code unit configured to error-correct code the data to be stored in the non-volatile memory device immediately after the data to be stored in the non-volatile memory device is transmitted from the host device, Data is buffered in the buffer memory device, and the encoded data buffered in the buffer memory device is stored in the nonvolatile memory device.

According to the embodiment of the present invention, the operation speed of the data storage device can be increased.

1 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention.
2 is a flowchart illustrating an exemplary method of processing an error correction code of a data storage apparatus according to an embodiment of the present invention.
3 is a data flow chart for explaining an error correction code processing method according to an embodiment of the present invention.
4 is a block diagram illustrating an exemplary data processing system in accordance with another embodiment of the present invention.
5 is a block diagram illustrating an example of a solid state drive (SSD) according to an embodiment of the present invention.
6 is a block diagram illustrating the SSD controller shown in FIG.
Figure 7 is a block diagram illustrating an exemplary computer system in which a data storage device is mounted, in accordance with an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein, It is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation of the scope of the appended claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / coupled " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention. Referring to FIG. 1, a data processing system 100 includes a host device 110 and a data storage device 120.

The host device 110 includes, for example, portable electronic devices such as mobile phones, MP3 players or the like or electronic devices such as laptop computers, desktop computers, game machines, TVs, beam projectors and the like.

The data storage device 120 is configured to operate in response to a request from the host device 110. [ The data storage device 120 is configured to store data accessed by the host device 110. That is, the data storage device 120 may be used as the main storage device or the auxiliary storage device of the host device 110. [

The data storage device 120 includes a controller 130, a non-volatile memory device 140 and a buffer memory device 150. The controller 130, the non-volatile memory device 140, and the buffer memory device 150 may be configured as memory devices connected to the host device 110 through various interfaces. Or the controller 130, the non-volatile memory device 140 and the buffer memory device 150 may be configured as a solid state drive (SSD).

Controller 130 is configured to control non-volatile memory device 140 and buffer memory device 150 in response to a request from host device 110. [ For example, the controller 130 is configured to provide data read from the non-volatile memory device 140 to the host device 110. [ As another example, the controller 130 is configured to store data provided from the host device 110 in the non-volatile memory device 140. For this operation, the controller 130 is configured to control the read, program (or write) and erase operations of the data storage medium 140.

In order to improve the data processing speed of the data storage device 120, the controller 120 processes the data through the buffer memory device 150. For example, the controller 130 is configured to buffer the data read from the non-volatile memory device 140 into the buffer memory device 150 and provide the buffered data to the host device 110. [ As another example, the controller 130 is configured to buffer the data provided from the host device 110 in the buffer memory device 150 and store the buffered data in the non-volatile memory device 140.

Illustratively, the non-volatile memory device 140 may include a flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) And various types of nonvolatile memory devices such as a phase change memory device (PRAM) using chalcogenide alloys, a resistive memory device (RERAM) using a transition metal oxide, And may be configured as any one of the memory devices.

The controller 130 includes an error correction code unit 131. The error correction code unit 131 is configured to perform an error correction code encoding operation on data provided from the host apparatus 110. [ For example, the error correction code unit 131 is configured to generate parity data based on data provided from the host apparatus 110. [ Both the data provided from the host device 110 and the generated parity data are stored in the nonvolatile memory device 140. [

The error correction code unit 131 is configured to perform an error correction code decoding operation on data read from the nonvolatile memory device 140. [ For example, the error correction code unit 131 is configured to detect errors in data read from the nonvolatile memory device 140 using the parity data. The error correction code unit 131 is configured to correct the detected error when an error of a correctable size is detected.

One of various encoding methods classified according to the encoding performance or the encoding method can be used as an encoding method of the error correction code unit 131. [ For example, the error correction code unit 131 may be a Bose, Chaudhuri, Hocquenghem (BSC) code, a Reed-Solomon (RS) code, a Low Density Parity Check (LDPC) Code, and a cyclic redundancy check (CRC) code. As another example, the error correcting code unit 131 can perform an encoding operation using a combination of a BCH code, an RS code, an LDPC code, a convolutional code, and a CRC code.

According to the embodiment of the present invention, data provided from the host apparatus 110 is preferentially provided to the error correction code unit 131. [ The error correction code unit 131 is configured to encode data provided as soon as data is provided from the host device 110. [ The data encoded through the error correction code unit 131 is buffered in the buffer memory device 150. The data buffered in the buffer memory device 150 is finally stored in the nonvolatile memory device 140. This error correction code encoding process will be described in detail with reference to FIGS. 2 and 3. FIG.

2 is a flowchart illustrating an exemplary method of processing an error correction code of a data storage apparatus according to an embodiment of the present invention. And FIG. 3 is a data flow chart for explaining an error correction code processing method according to an embodiment of the present invention. Referring to Figs. 1 to 3, a method of encoding an error correction code of the data storage device 120 of Fig. 1 will be described.

In step S110, data to be stored in the nonvolatile memory device 140 is received from the host device 110. [ Data received from the host apparatus 110 is preferentially provided to the error correction code unit 131. [ The data received from the host device 110 may be continuous data, i.e., sequential data. The data received from the host device 110 may be discontinuous data, i.e., random data.

In step S120, the error correcting code unit 131 encodes the received data for error correction upon receiving the data. In step S130, the encoded data is stored in the buffer memory device. According to this procedure, data received from the host device 110 is not preferentially stored in the buffer memory device 150. [ That is, after the error correction code encoding is performed on the data received from the host device 110, it is stored in the buffer memory device 150.

With reference to FIG. 3, for example, data D2 received from the host apparatus 110 is preferentially provided to the error correction code unit 131. FIG. The error correction code unit 131 encodes the received data D2 and generates parity data PD2 according to the encoding result. As a result of the error correction code encoding, encoded data ED2 to which the parity data PD2 is added to the received data D2 is generated. The encoded data ED2 is stored in the buffer memory device 150. [ The encoded data ED1 is stored in the buffer memory device 150 through this process before the encoded data ED2 is generated.

Referring again to FIG. 2, in step S140, the encoded data is stored in the nonvolatile memory device 140 from the buffer memory device 150. FIG. That is, the data buffered in the buffer memory device 150 is finally stored in the nonvolatile memory device 140. Although not shown, the time at which the encoded data is transferred from the buffer memory device 150 to the nonvolatile memory device 140 may be determined according to the storage capacity of the buffer memory device 150. [ For example, the larger the storage capacity of the buffer memory device 150, the slower the time at which the encoded data is transferred from the buffer memory device 150 to the nonvolatile memory device 140. As another example, the time at which the encoded data is transferred from the buffer memory device 150 to the nonvolatile memory device 140 may be determined according to the performance policy of the firmware that the controller 130 drives.

According to an embodiment of the present invention, an error correcting code encoding operation is performed as soon as data is received from the host device 110. [ The encoded data is then stored in the buffer memory device 150. Therefore, compared with the case where the received data is preferentially stored in the buffer memory device 150 and the stored data is transferred and stored in the nonvolatile memory device 140, the error correcting code encoding operation is performed Can be reduced.

4 is a block diagram illustrating an exemplary data processing system in accordance with another embodiment of the present invention. Referring to FIG. 4, a data processing system 1000 includes a host device 1100 and a data storage device 1200. The data storage device 1200 includes a controller 1210 and non-volatile memory devices 1220. The data storage device 1200 may be connected to and used by a host device 1100 such as a desktop computer, a notebook computer, a digital camera, a mobile phone, an MP3 player, a game machine, and the like. Data storage device 1200 is also referred to as a memory system.

Controller 1210 is configured to access non-volatile memory devices 1220 in response to a request from host device 1100. [ For example, the controller 1210 is configured to control the read, program, or erase operations of the non-volatile memory devices 1220. The controller 1210 is configured to drive firmware for controlling the non-volatile memory devices 1220.

The controller 1210 may include well known components such as a host interface 1211, a micro control unit 1212, a memory interface 1213, a RAM 1214 and an error correction code unit 1215.

The micro control unit 1212 is configured to control all operations of the controller 1210 in response to a request from the host device. The RAM 1214 may be used as a working memory of the micro control unit 1212. Optionally, the RAM 1214 may temporarily store data read from the non-volatile memory devices 1220 or data provided from the host device 1100. That is, the RAM 1214 may perform the function of the buffer memory device 150 of FIG.

The error correction code unit 1215 is configured to encode data provided from the host apparatus 1100. [ And an error correction code unit 1215 is configured to detect errors in the data read from the non-volatile memory devices 1220. [ And the error correction code unit 1215 is configured to correct the detected error if the detected error is within the correction range. On the other hand, the error correction code unit 1215 may be provided in the controller 1210 or may be provided outside according to the memory system 1000.

The micro control unit 1212 can control the error correcting code encoding operation according to the embodiment of the present invention. In other words, the micro control unit 1212 will preferentially provide the data received from the host device 1100 to the error correction code unit 1215, and store the encoded data in the RAM 1214. And the microcontroller unit 1212 will store the encoded data stored in the RAM 1214 in the nonvolatile memory devices 1220 according to the storage capacity of the RAM 1214. [ Or micro control unit 1212 may store the encoded data stored in RAM 1214 in non-volatile memory devices 1220 in accordance with the performance policy of the firmware.

The host interface 1211 is configured to interface the host device 1100 and the controller 1210. For example, the host interface 1211 may include a USB (Universal Serial Bus) protocol, an MMC (Multimedia Card) protocol, a PCI (Peripheral Component Interconnection) protocol, a PCI- To communicate with the host device 1100 through one of a variety of interface protocols such as protocol, Serial ATA protocol, Small Computer System Interface (SCSI) protocol, Serial SCSI (SAS), and Integrated Drive Electronics Lt; / RTI >

The memory interface 1213 is configured to interface the controller 1210 and the non-volatile memory devices 1220. The memory interface 1213 is configured to provide commands and addresses to the non-volatile memory devices 1220. And the memory interface 1213 is configured to exchange data with the non-volatile memory devices 1220.

The controller 1210 and the non-volatile memory devices 1220 may be integrated into one semiconductor device and configured as a memory card or a memory device. For example, the controller 1210 and the non-volatile memory devices 1220 may be integrated into a single semiconductor device and may be a personal computer memory card (PCMCIA) card, a compact flash (CF) card, a smart media card , Memory stick, multi media card (MMC, RS-MMC, MMC-micro), SD (secure digital) card (SD, Mini SD, Micro SD), UFS And the like.

As another example, controller 1210 or data storage medium 1220 may be implemented in various types of packages. For example, the controller 1200 or the data storage medium 1900 may include a package on package (POP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP) outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system in package (SIP), multi chip package (MCP) WFP), a wafer-level processed stack package (WSP), and the like.

5 is a block diagram illustrating an example of a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 5, the data processing system 3000 includes a host device 3100 and a solid state drive (SSD) 3200.

The SSD 3200 includes an SSD controller 3210, a buffer memory device 3220, nonvolatile memory devices 3231-323n, a power supply 3240, a signal connector 3250, and a power connector 3260.

The SSD 3200 operates in response to a request from the host device 3100. That is, the SSD controller 3210 is configured to access the non-volatile memory devices 3231 to 323n in response to a request from the host device 3100. [ For example, the SSD controller 3210 is configured to control the read, program and erase operations of the non-volatile memory devices 3231 through 323n.

The buffer memory device 3220 is configured to temporarily store data to be stored in the nonvolatile memory devices 3231 to 323n. In addition, the buffer memory device 3220 is configured to temporarily store data read from the non-volatile memory devices 3231 to 323n. The data temporarily stored in the buffer memory device 3220 is transferred to the host device 3100 or the nonvolatile memory devices 3231 to 323n under the control of the SSD controller 3210. [

The nonvolatile memory devices 3231 to 323n are used as a storage medium of the SSD 3200. Each of the nonvolatile memory devices 3231 to 323n is connected to the SSD controller 3210 through a plurality of channels CH1 to CHn. One channel may be coupled to one or more non-volatile memory devices. Non-volatile memory devices connected to one channel will be connected to the same signal bus and data bus.

The power supply 3240 is configured to provide the power supply PWR input through the power supply connector 3260 into the SSD 3200. The power supply 3240 includes an auxiliary power supply 3241. The auxiliary power supply 3241 is configured to supply power so that the SSD 3200 can be normally shut down when a sudden power off occurs. The auxiliary power supply 3241 may include super capacitors capable of charging the power supply PWR.

The SSD controller 3210 exchanges signals SGL with the host device 3100 through the signal connector 3250. Here, the signal SGL will include a command, an address, data, and the like. The signal connector 3250 may be a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a serial SCSI (SAS) And the like.

6 is a block diagram illustrating the SSD controller shown in FIG. 6, the SSD controller 3210 includes a memory interface 3211, a host interface 3212, an error correction code unit 3213, a micro control unit 3214, and a RAM 3215.

The memory interface 3211 is configured to provide commands and addresses to the non-volatile memory devices 3231-323n. The memory interface 3211 is configured to exchange data with the nonvolatile memory devices 3231 to 323n. The memory interface 3211 can scatter data transferred from the buffer memory device 3220 to the respective channels CH1 to CHn under the control of the micro control unit 3214. [ The memory interface 3211 transfers data read from the nonvolatile memory devices 3231 to 323n to the buffer memory device 3220 under the control of the microcontroller 3214. [

The host interface 3212 is configured to provide interfacing with the SSD 3200 in correspondence with the protocol of the host device 3100. For example, the host interface 3212 may be coupled to the host device 3100 through any one of Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI) ). ≪ / RTI > The host interface 3212 may perform a disk emulation function to support the host device 3100 to recognize the SSD 3200 as a hard disk drive (HDD).

The ECC unit 3213 is configured to generate parity bits based on data transmitted to the non-volatile memory devices 3231 to 323n. The generated parity bits may be stored in the nonvolatile memories 3231 to 323n. ECC unit 3213 is configured to detect errors in the data read from non-volatile memory devices 3231-323n. If the detected error is within the correction range, it is configured to correct the detected error.

The micro control unit 3214 is configured to analyze and process the signal SGL input from the host device 3100. The micro control unit 3214 controls all operations of the SSD controller 3210 in response to a request from the host apparatus 3100. [ The micro control unit 3214 controls the operation of the buffer memory device 3220 and the nonvolatile memory devices 3231 to 323n in accordance with the firmware for driving the SSD 3200. RAM 3215 is used as a working memory device to drive such firmware.

The micro control unit 3214 can control the error correcting code encoding operation according to the embodiment of the present invention. In other words, the micro control unit 3214 preferentially provides the data received from the host device (3100 in Fig. 5) to the error correction code unit 3213, and stores the encoded data in the buffer memory device (3220 in Fig. 5) will be. And the microcontroller unit 3214 will store the encoded data stored in the buffer memory device 3220 in the nonvolatile memory devices 3231 to 323n according to the storage capacity of the buffer memory device 3220. [ Or micro control unit 3214 may store the encoded data stored in buffer memory device 3220 in non-volatile memory devices 32331 through 323n in accordance with the performance policy of the firmware.

Figure 7 is a block diagram illustrating an exemplary computer system in which a data storage device is mounted, in accordance with an embodiment of the present invention. 7, a computer system 4000 includes a network adapter 4100, a central processing unit 4200, a data storage unit 4300, a RAM 4400, a ROM 4500, And a user interface 4600. Here, the data storage device 4300 may be composed of the data storage device 120 shown in FIG. 1, the data storage device 1200 shown in FIG. 4, or the SSD 3200 shown in FIG.

The network adapter 4100 provides interfacing between the computer system 4000 and external networks. The central processing unit 4200 performs various operation processes for driving an operating system or an application program residing in the RAM 4400. [

The data storage device 4300 stores necessary data in the computer system 4000. For example, an operating system, an application program, various program modules, program data, and user data for driving the computer system 4000 Is stored in the data storage device 4300.

The RAM 4400 may be used as an operating memory device of the computer system 4000. At the time of booting, the RAM 4400 stores an operating system, an application program, various program modules read from the data storage device 4300, and program data required for driving programs, Is loaded. ROM 4500 stores a basic input / output system (BIOS) which is a basic input / output system activated before the operating system is operated. Information is exchanged between the computer system 2000 and the user via the user interface 4600. [

Although not shown in the drawings, it will be appreciated that the computer system 4000 may further include devices such as a Battery, an Application chipset, a Camera Image Processor (CIS), and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. It will be appreciated that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention.

100: Data processing system
110: Host device
120: Data storage device
130: controller
140: Nonvolatile memory device
150: buffer memory device

Claims (15)

A method for processing an error correction code in a data storage device, comprising:
Receiving data from a host device;
Performing an error correcting code encoding operation on the received data; And
And storing parity data generated as a result of the error correction code encoding and the received data in a buffer memory device. The method according to claim 1,
Wherein an error correcting code encoding operation for the received data is performed immediately after receiving data from the host device. The method according to claim 1,
And storing the parity data and the received data stored in the buffer memory device in a nonvolatile memory device. The method of claim 3,
Wherein a time at which the parity data stored in the buffer memory device and the received data are stored in the nonvolatile memory device is determined according to a storage capacity of the buffer memory device. The method according to claim 1,
Wherein the error correction code encoding operation is performed using any one of a BCH code, an RS code, a low density parity check (LDPC) code, a convolutional code, and a CRC code. The method according to claim 1,
Wherein the error correction code encoding operation is performed by using a combination of a BCH code, an RS code, a low density parity check (LDPC) code, a convolutional code, and a CRC code. A nonvolatile memory device;
A buffer memory device configured to buffer data to be stored in the nonvolatile memory device; And
And an error correction code unit configured to error-correct code the data to be stored in the nonvolatile memory device immediately after the data to be stored in the nonvolatile memory device is transmitted from the host device,
Wherein the data encoded through the error correction code unit is buffered in the buffer memory device and the encoded data buffered in the buffer memory device is stored in the non-volatile memory device. 8. The method of claim 7,
Wherein the error correction code unit is configured to encode data to be stored in the nonvolatile memory device using any one of a BCH code, an RS code, a low density parity check (LDPC) code, a convolutional code, and a CRC code. 8. The method of claim 7,
Wherein the error correction code unit is configured to encode data to be stored in the nonvolatile memory device using a combination of a BCH code, an RS code, a low density parity check (LDPC) code, a convolutional code, and a CRC code. 8. The method of claim 7,
Wherein the error correction code unit generates the encoded data composed of parity data generated by encoding data transmitted from the host apparatus and data transmitted from the host apparatus. 11. The method of claim 10,
And the error correction code unit is configured to error-correct code-decode data read from the nonvolatile memory device based on the parity data. 8. The method of claim 7,
And the buffer memory device is configured to buffer data read from the nonvolatile memory device. 8. The method of claim 7,
Further comprising a controller configured to control the non-volatile memory device and the buffer memory device, the controller including the error correction code unit. 14. The method of claim 13,
Wherein the controller, the nonvolatile memory device, and the buffer memory device are constituted by a memory card. 14. The method of claim 13,
Wherein the controller, the nonvolatile memory device, and the buffer memory device are comprised of a solid state drive (SSD).
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US11043666B2 (en) 2016-01-19 2021-06-22 Seoul National University R&Db Foundation Composite materials for cathode materials in secondary battery, method of manufacturing the same, and lithium secondary battery including the same
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