KR20140080295A - Core circuit, memory and memory system icluding the same - Google Patents

Abstract

The present technology stores information of counting the number of activations of each word line at memory cells connected to each word line and counts the number of the activations of each word line while repairing defects in the memory cells which store the number of the activations of the word line if the defects occur. A memory according to the present invention comprises: a first cell array including a plurality of first memory cells connected to each of a first to an N^th word line; a bit line selecting part for selecting one or more among a first to an M^th bit line in response to repair information; a second cell array including a plurality of second memory cells connected to each of the first to the N^the word line, connected to each of the first and the M^th bit line and storing the number of activations of a word line connected to itself among the first to N^th word line in a case that a bit line connected to itself is selected; and a part for updating the number of activations for updating a value stored at the second memory cell connected to one or more bit lines selected among the second memory cells connected to an activated word line among the first to the N^th word line.

Description

TECHNICAL FIELD [0001] The present invention relates to a core circuit, a memory, and a memory system including the core circuit,

The present invention relates to a core circuit, a memory, and a memory system including the core circuit for repairing a defective cell array that counts and stores the number of activations of each word line.

As the degree of integration of the memory increases, the spacing between the plurality of word lines included in the memory is decreasing. The spacing between the word lines is reduced, and the coupling effect between adjacent word lines is increasing.

Each time data is input / output to / from a memory cell, the word line is toggled between an active (active) state and an inactive state. As described above, the coupling effect between adjacent word lines is increased, The data of the memory cell connected to the memory cell is damaged. This phenomenon is also referred to as a word line disturbance. However, the word line disturbance causes a problem that data in the memory cell is damaged before the memory cell is refreshed.

FIG. 1 is a view for explaining a word line disturbance phenomenon and shows a part of a cell array included in a memory.

In FIG. 1, 'WLL' corresponds to a word line having a large number of activations and 'WLL-1' and 'WLL + 1' correspond to word lines disposed adjacent to 'WLL' . 'CL' represents a memory cell connected to 'WLL', 'CL-1' represents a memory cell connected to 'WLL-1', and 'CL + 1' represents a memory cell connected to WLL + 1. Each memory cell includes cell transistors (TL, TL-1, TL + 1) and cell capacitors (CAPL, CAPL-1, CAPL + 1).

In FIG. 1, when 'WLL' is activated or deactivated, the voltages of 'WLL-1' and 'WLL + 1' rise due to a coupling phenomenon occurring between WLL and WLL-1 and WLL + The charge amount of the cell capacitors CL-1 and CL + 1 is also influenced. Therefore, when 'WLL' is frequently activated and 'WLL' toggles between the active and inactive states, the cell capacitors (CAPL-1 and CAPL + 1) included in 'CL-1' and 'CL + A change in the amount of stored charges increases and data in the memory cell can be deteriorated.

Further, electromagnetic waves generated while the word lines are toggled between the active state and the inactive state impair the data by introducing electrons into the cell capacitors of the memory cells connected to the adjacent word lines or by discharging electrons from the cell capacitors.

There is a need for a method for detecting a word line having a large number of activations and preventing data deterioration of a plurality of memory cells connected to a word line adjacent to the detected word line in order to prevent deterioration of data due to the word line disturbance. In addition, if a configuration for detecting a word line having a large number of activations is added, such a configuration may also be defective.

The present invention stores information in which the number of activations of each word line is counted in memory cells connected to each word line, counts the number of activations of each word line, and when a failure occurs in the memory cells storing the number of activations of the word line And provides a core circuit, memory, and memory system that can repair it.

A memory according to the present invention includes: a first cell array including a plurality of first memory cells connected to first to Nth word lines, respectively; A bit line selector for selecting one or more bit lines of the first through M th bit lines in response to the repair information; And a word line connected to each of the first to Nth word lines and connected to each of the first to Mth bit lines and connected to the first to the N < th > A second cell array including a plurality of second memory cells for storing the number of times the first memory cell is turned on; And an activation number updating unit for updating a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines .

Also, a memory according to the present invention includes: a first cell array including a plurality of first memory cells connected to first to Nth word lines; A bit line selector for selecting one or more bit lines of the first through M th bit lines in response to the repair information; The first to the N-th word lines are connected to the first to M-th bit lines, respectively, and when the bit line is connected to the first to the N-th word lines, A second cell array including a plurality of second memory cells storing a count; A transfer signal generator activating a first transfer signal in response to an active command and activating a second transfer signal after the first transfer signal is activated and a predetermined time elapses; And a second memory cell coupled to the selected one or more bit lines of the plurality of second memory cells coupled to a word line corresponding to an address of the first through N th word lines in response to the first transfer signal, And responsive to the second transfer signal for transferring the increased value to a second memory cell coupled to the selected one or more bit lines of the plurality of second memory cells coupled to the word line corresponding to the address, And a value update unit.

The memory system according to the present invention further includes a first cell array including a plurality of first memory cells connected to the first to Nth word lines and a second cell array connected to each of the first to Nth word lines, And a plurality of second memory cells connected to the M bit lines and storing the number of activated word lines of the first to Nth word lines, when the bit line to which the first bit line is connected is selected, A memory for generating an alarm signal when the number of activations of the first to Nth word lines is equal to or greater than a reference number; And a memory controller for applying to the memory at least one of the first to Nth word lines with an excess address corresponding to a word line whose activation count is equal to or greater than the reference number and a value adjacent to the excess address, .

The core circuit according to the present invention further includes: a first region including a plurality of first memory cells connected to the first to Nth word lines; A bit line selector for selecting one or more bit lines of the first through M th bit lines in response to the repair information; And a word line connected to each of the first to Nth word lines and connected to each of the first to Mth bit lines and connected to one of the first to Nth word lines, And a second cell array including a plurality of second memory cells storing the number of activations.

In this technique, the number of activations of each word line is counted by storing the number of activations of each word line in the memory cells connected to each word line. When a failure occurs in the memory cell storing the number of activation of the word line, It is possible to prevent a problem from occurring in counting the number of activations of the line.

FIG. 1 is a view for explaining a word line disturbance phenomenon, showing a part of a cell array included in a memory,
FIG. 2 is a diagram for explaining a special refresh operation used to prevent data of a memory cell connected to a word line adjacent to a word line whose activation count is equal to or greater than a reference number from deteriorating due to a word line disturbance phenomenon;
3 is a configuration diagram of a memory system according to an embodiment of the present invention;
4 is a block diagram of a memory 310 according to an embodiment of the present invention.
FIG. 5 is a block diagram of the bit line selector BS of FIG. 4,
6 is a configuration diagram of the stored value updating unit 412 of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

Hereinafter, a word line adjacent to a specific word line may mean a word line disposed closer to a specific word line than a predetermined distance. At this time, the number of word lines disposed between a specific word line and adjacent word lines may be less than a predetermined number. The range of word lines adjacent to a particular word line may vary depending on the design. Hereinafter, the adjacent word lines will be described as being a word line disposed immediately next to a specific word line (i.e., the number of word lines arranged between a specific word line and a neighboring word line is zero).

2 is a diagram for explaining a special refresh operation used to prevent the data of a memory cell connected to a word line adjacent to a word line whose activation count is equal to or greater than a reference number from deteriorating due to a word line disturbance phenomenon.

2) includes a command signal CMD, an address ADD < 0: A >, and data (also shown in FIG. 2) 2) to control the memory. Hereinafter, a value of an address corresponding to a word line of L (L is a natural number, 1? L? N) word line among the first to Nth word lines is represented by 'L'.

The number of times the first to Nth word lines are activated is the same as the number of times the addresses corresponding to the first to Nth word lines are input from the memory controller to the memory together with the active command. For example, if the memory controller inputs an address of '15' with an active command ten times, the fifteenth word line is activated ten times. Therefore, the memory or the memory controller determines whether there are more word lines than the reference number of times that the activated number is greater than the set reference number, by using the result of counting the number of times the addresses corresponding to the first to Nth word lines are input to the memory together with the active command. In this case, the reference frequency may be a value determined internally in the memory system or a value input from the outside of the memory system.

When a specific address combination is input together with the MRS command (MRS) in the memory controller, the memory enters the special refresh mode by setting the MRS (Mode Resistor Set) ('start' setting). When a specific address combination is input together with the MRS command (MRS), the memory exits the special refresh mode ('end' setting). Compensating for data degradation by entering a special refresh mode with a combination of an MRS command and a specific address is an example and it is possible to control the memory to perform the compensation operation described above using a newly defined signal or a combination of existing signals have.

In the special refresh mode, the memory controller includes an operation of inputting an address (hereinafter referred to as excess address) whose number of times inputted with the active command is equal to or greater than the reference number, and activating a word line adjacent to the word line corresponding to the excess address. Compensation cycle '. Hereinafter, the case where the address of 'L' corresponding to the Lth word line is an excess address will be described.

The excess address L is input to the memory together with the first active command ACT in each ' compensation cycle '. After a predetermined time elapses, the precharge command PRE is input to the memory. The memory activates the Lth word line in response to the active command ACT and an address of L and deactivates the activated Lth word line in response to the precharge command PRE.

Addresses (L + 1, L-1) corresponding to the word line adjacent to the L-th word line are sequentially inputted together with the active command ACT after the first. In FIG. 2, an address of 'L + 1' is input together with a second active command ACT, and an address of 'L-1' is input together with a third active command ACT. Thus, the (L + 1) th word line and the (L-1) th word line of the memory are activated in order. For reference, the order of inputting the address of 'L + 1' and the address of 'L-1' may be changed.

When the operation of activating the word lines adjacent to the Lth word line is completed, the memory exits the special refresh mode by the combination of the MRS command and the address input from the memory controller.

When a certain word line is activated, the data of the memory cells connected to the word line are refreshed. Therefore, by activating the word line adjacent to the word line corresponding to the excess address in the special refresh mode, it is possible to prevent data deterioration occurring in the word line disturbance.

In order to perform the above-described special refresh operation, it is necessary to detect the excess address. A description will now be made of a core circuit, a memory and a memory system capable of repairing an occurrence of a failure in a memory cell storing a number of activations of the word line while storing the number of activation of each word line in a memory cell for detecting an excess address .

3 is a block diagram of a memory system according to an embodiment of the present invention.

As shown in FIG. 3, the memory system includes a memory 310 and a memory controller 320. The memory 310 includes a first cell array CA1 including a plurality of first memory cells (shown in FIG. 4) connected to the first through Nth word lines WL1 through WLN, WL1 to WLN and connected to each of the first to Mth bit lines BL1 to BLM, and when the bit line to which the bit line is connected is selected, one of the first to Nth word lines WL1 to WLN, And a second cell array (CA2) including a plurality of second memory cells (shown in FIG. 4) storing the number of times the associated word lines are activated, wherein the first to Nth word lines (WL1 to WLN) And generates a warning signal (ALERT) when the number of activations is equal to or greater than the reference number of times. The memory 310 also includes a bit line selector (BS) for selecting one or more bit lines of the first through M th bit lines BL1 - BLM in response to repair information REPAIR <0: B>. In the special refresh mode, the memory controller 320 supplies to the memory 310 at least one of the first to Nth word lines with the excess address corresponding to the word line whose number of activations is equal to or greater than the reference number and the value adjacent to the excess address do. For example, an address having a value of '4' or '6' when the excess address corresponding to the word line whose activation count is equal to or greater than the reference number is '5'.

The memory controller 320 outputs a chip select signal CSB, an active control signal ACTB, a row address strobe signal RASB, a column address strobe signal CASB and a write enable signal WEB to the memory 310, And the memory controller 310 applies a specific command to the memory 320 because the combination of the command signals CSB, ACTB, RASB, CASB, and WEB corresponds to a specific command. For example, the fact that the memory controller 320 applies the active command to the memory 310 means that the combination of the command signals CSB, ACTB, RASB, CASB, WEB that the memory controller 320 applies to the memory 310 is active Command. The command decoder (not shown in FIG. 3) included in the memory 310 decodes the command signals CSB, ACTB, RASB, CASB, and WEB to generate commands internally in the memory 310. The memory controller 320 includes an address ADD <0: A> and an address ADD <0: A> in addition to a plurality of command signals CSB, ACTB, RASB, CASB, and WEB in the memory 310, ) Is applied.

Hereinafter, the special refresh mode refers to a mode of refreshing data of a plurality of memory cells connected to a word line adjacent to a word line whose activation frequency is equal to or greater than a reference frequency by activating a word line adjacent to the word line whose activation frequency is equal to or greater than a reference frequency .

The memory system will be described with reference to Fig.

The first cell array CA1 includes a plurality of first memory cells connected to the first to Nth word lines WL1 to WLN, respectively. The first memory cell is a memory cell for storing general data input to and output from the memory 310. The second cell array CA2 is connected to the first to Nth word lines WL1 to WLN in the row direction and to the first to Mth bit lines BL1 to BLM in the column direction And a second memory cell. The number of activations of the word lines connected to the first to Nth word lines WL1 to WLN is stored in the memory cell connected to the selected bit line among the plurality of second memory cells. For example, when the first to the Lth (1? L? M) bit lines BL1 to BLL of the first to Mth bit lines BL1 to BLM are selected, The number of activations of the Kth word line (WLK) is stored in a second memory cell connected to the first to Lth bit lines (BL1 to BLL) of the second memory cells.

Where the bit line may be selected by repair information (REPAIR < 0: B >) stored within memory 310. The repair information REPAIR <0: B> is information indicating which one of the first to Mth bit lines BL1 to BLM is defective, and the defective one of the first to Mth bit lines BL1 to BLM May be information for selecting a bit line that has not occurred. In order to generate the repair information REPAIR <0: B>, the memory 310 may detect the bit line in which the defective one of the first to Mth bit lines BL1 to BLM is tested. (REPAIR < 0: B >) indicating information indicating a bit line on which a defect has been detected through a bit line selection (BS) test included in the memory 310, B>) is used to select one or more bit lines of the first to Mth bit lines BL1 to BLM that have not failed and store the number of activations of the word line in the second memory cell connected to the selected bit line .

 The occurrence of a defect in the bit line means that a failure occurs in the second memory cell connected to the bit line or a failure occurs in the bit line itself or a peripheral circuit of the bit line to write data to the second memory cell connected to the bit line, It means that the operation of reading data from two memory cells can not be normally performed.

Hereinafter, how the memory 310 stores the number of activations of the first to Nth word lines WL1 to WLN in the second cell array CA2 and updates the values stored in the second cell array CA2 Explain.

The memory 310 includes an active command for decoding a plurality of command signals CSB, ACTB, RASB, CASB, and WEB applied from the memory controller 320 to activate a word line, A refresh command for performing a refresh operation of the memory cell, a read command for reading data of the memory cell, a write command for writing data in the memory cell, a precharge command for precharging the memory cell, a write commnode, an MRS command (Mode Resister Set command) for setting a mode register set, and the like.

The memory 310 updates the value stored in the second memory cell connected to the selected one or more bit lines of the plurality of second memory cells connected to the activated word line. In more detail, the memory 310 may be configured to (1) selectively activate a word line corresponding to an address ADD < 0: A > in response to an active command, A second memory cell coupled to the selected one of the plurality of second memory cells connected to the activated word line when performing a refresh operation or a special refresh operation, Initialize the value stored in the memory cell. Initialization refers to making the value stored in the second memory cell connected to the selected one or more bit lines (i.e., the number of times of activation of the stored word line) a value corresponding to zero.

(1) increasing the value stored in the second memory cell connected to one or more selected bit lines

In order to perform the above-described special refresh operation in the description of FIG. 2, an excess address must be detected. Therefore, it is necessary to count the number of times each word line is activated in response to the active command. Thus, the memory 310 is responsive to the active command to activate a second memory coupled to the selected one or more bit lines of the plurality of second memory cells coupled to the word line when the word line corresponding to the address ADD < 0: A & Increase the value stored in the cell.

In more detail, since a plurality of first memory cells and a plurality of second memory cells connected to the activated word line are electrically connected to the corresponding bit lines, data is transferred between the memory cells connected to the activated word lines and the bit lines do. The value stored in the second memory cells connected to the selected one or more bit lines of the plurality of second memory cells corresponds to a value obtained by converting the number of activated word lines to the binary number. Thus, in response to the active command, the memory 310 increases the binary value output from the second memory cells connected to the selected one or more bit lines of the plurality of second memory cells connected to the activated word line by '1' Value is stored again in the second memory cells. Thus, each time the word line is activated in response to the active command, the binary value stored in the second memory cells connected to the selected one or more bit lines of the plurality of second memory cells connected to the activated word line is increased by '1'.

The memory 310 also activates an alert signal ALERT indicating that a special refresh operation is required when the value stored in the plurality of second memory cells connected to the activated word line is equal to or greater than the reference number. The memory 310 may also store the address ADD < 0: A > applied to the memory 310 when the alert signal ALERT is activated.

The memory controller 320 can control the memory 310 to perform the special refresh operation described above with reference to FIG. 2 when the alert signal ALERT is activated. The memory controller 320 may immediately enter the memory 310 in the special refresh mode when the alert signal ALERT is activated and the memory 310 after the predetermined time has elapsed after the alert signal ALERT is activated, Mode. The memory 310 operates in a special refresh mode from the time of entering the special refresh mode to the time of exiting the special refresh mode.

(2) initializing a value stored in a second memory cell connected to one or more selected bit lines

When the memory 310 refreshes data of a plurality of first memory cells connected to the activated word line among the first to Nth word lines WL1 to WLN included in the memory 310 during the refresh operation, The number of times is counted from the beginning again to detect the activated word line more than the reference number. In addition, when a specific word line is activated more than the reference number and a special refresh operation is performed on the adjacent word line in a specific word line, the number of activation of the specific word line is counted from the beginning to detect the activated word line more than the reference number.

Accordingly, the memory 310 is connected to the selected one or more bit lines of the plurality of second memory cells connected to the word line activated when the data of the plurality of first memory cells connected to the word line activated in the refresh operation or the special refresh operation is refreshed And initializes the value stored in the connected second memory cells.

The reason for initializing the values stored in the second memory cells connected to the selected one or more bit lines of the plurality of second memory cells connected to the activated word line in the refresh operation is that the word lines are activated in sequence in the refresh operation, The word line adjacent to the word line is also activated so that the data of a plurality of first memory cells connected to the adjacent word line are refreshed, so that the word line disturbance does not occur and it is not necessary to perform the special refresh operation immediately.

In more detail, the memory 310 initializes the value output from the second memory cells connected to the selected one or more bit lines of the plurality of second memory cells connected to the activated word line to '0' during the refresh operation, In the second memory cells. The memory 310 also includes a second memory cell coupled to the selected one or more bit lines of the plurality of second memory cells coupled to the first activated word line (the word line corresponding to the excess address) in the 'compensation cycle' Initializes the value output from the memory cells to '0', and stores the initialized value in the second memory cells.

The operation in the special refresh mode of the memory system will be described with reference to FIG.

When the warning signal ALERT is activated, the memory controller 320 causes the memory 310 to perform a special refresh operation by a combination of a plurality of command signals CSB, ACTB, RASB, CASB, and WEB and addresses ADD < Mode. When the memory 310 enters the special refresh mode, the memory controller 320 outputs the excess address L together with the active command ACT, the address L + 1 corresponding to the word line corresponding to the excess address and the word line adjacent thereto, L-1). In response to the active command ACT, the memory 310 receives the Lth word line WLL corresponding to the address 'L', 'L + 1', and L-1, the (L + 1) 1) and the (L-1) th word line WLL-1. When the special refresh operation is completed, the memory controller 320 sets the memory 310 in the special refresh mode by a combination of a plurality of command signals CSB, ACTB, RASB, CASB, and WEB and addresses ADD < Leave it out. The memory 310 does not always exit from the special refresh mode by a combination of a plurality of command signals CSB, ACTB, RASB, CASB and WEB and addresses ADD <0: A> You can automatically exit without any external input.

The memory system according to the present invention uses the memory cells connected to each word line to store the number of activations in the corresponding word line. At this time, if a memory cell storing the number of times of activation of the word line or a bit line connected to the memory cell is defective, the special refresh operation can not be performed properly. Therefore, the memory system according to the present invention detects a defective bit line (or memory cell) through a test with an extra memory cell for storing the number of activations of the word line and a bit line to which the memory cell is connected, The special refresh operation can be smoothly performed by storing the number of activations of the word line in the memory cells connected to the bit lines except for the bit line.

4 is a block diagram of a memory 310 according to an embodiment of the present invention.

4, the memory 310 includes a first cell array CA1 including a plurality of first memory cells C1 connected to first through Nth word lines WL1 through WLN, (BS) for selecting one or more bit lines of the first to M th bit lines BL1 to BLM in response to the first to Nth word lines WL1 to WLN (REPAIR <0: B>), And connected to each of the first to Mth bit lines BL1 to BLM. When the bit line to which the bit line is connected is selected, the word line WL1 to WLN, to which the first to Nth word lines WL1 to WLN are connected, A second cell array CA2 including a plurality of second memory cells C2 for storing an activated number of times and a plurality of second memory cells C2 connected to activated word lines among first to Nth word lines An activation number updating unit 410 for updating a value stored in a second memory cell C2 connected to the selected one or more bit lines, an address ADD <0: A> The number of activation of the word line corresponding to the address ADD < 0: A > stored in the second memory cell C2 connected to the selected one or more bit lines of the plurality of second memory cells C2 connected to the corresponding word line is An alarm signal generator 420 for activating a warning signal ALERT if the number of times of alarm signal ALERT is greater than a reference number of times and an address storage 430 for storing an address ADD <0: A> when an alarm signal ALERT is activated.

The memory 310 may include a storage unit 470 for storing repair information (REPAIR < 0: B >). The storage unit 470 storing the repair information (REPAIR < 0: B >) may include a plurality of fuses.

The memory 310 also decodes the command signals CSB, ACTB, RASB, CASB, and WEB input from the memory controller 320 and outputs an active command ACT, a precharge command (not shown in FIG. 2), a refresh command (Not shown in FIG. 2), a write command REF, a read command (not shown in FIG. 2), a write command (not shown in FIG. 2), an MRS command A row controller 450 for controlling the row operation of the connected bit lines BL1 to BLM and cell arrays CA1 and CA2 and a column controller 460 for controlling the column operation of the first cell array CA1.

The memory 310 will be described with reference to FIG.

Data input to and output from the memory 310 is stored in the first cell array CA1 and the number of activations of the first to Nth word lines WL1 to WLN is stored in the second cell array CA2. The row controller 440 activates one or more word lines of the first to Nth word lines WL1 to WLN when the active command ACT and the refresh command REF are applied and the column controller 440 Performs operations necessary to read data from a plurality of first memory cells connected to the activated word line or to write data to a plurality of first memory cells connected to the activated word line. The operation of reading or writing data in the first cell array CA1 is well known and is not directly related to the present invention, and thus will not be described.

The bit line selection unit BS selects the value SEL_OUT < 0: C > from the one or more bit lines selected from among the first to Mth bit lines BL1 to BLM in response to the repair information REPAIR < , 1? C? M) to the activation frequency updating unit 410 and transfers the value SEL_IN <0: C> output from the activation frequency updating unit 410 to the selected one or more bit lines.

The activation count updating unit 410 updates the value stored in the second memory cell connected to the selected one or more bit lines of the plurality of second memory cells connected to the activated word line. (1) Activation frequency update unit 410 responds to an active command and activates a word line corresponding to an address ADD <0: A>. When a selected one or more of a plurality of second memory cells connected to the activated word line And increases the value stored in the second memory cells connected to the bit line. (2) When the word line is activated while performing the refresh operation or the special refresh operation, the activation number update unit 410 may be configured to select the second memory cells connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line And initializes the stored value. Initialization refers to making the number of activations of the word lines stored in the second memory cells connected to the selected one or more bit lines to '0'.

(1) increasing the value stored in the second memory cells (C2) connected to the selected one or more bit lines

The activation frequency updating unit 410 may be configured to store a plurality of second memory cells C2 connected to the activated word line in response to the active command ACT after a predetermined time (first time) after the active command ACT is applied, Is read. The bit line selection unit BS transfers the value stored in the second memory cells C2 connected to one or more selected bit lines among the read values to the activation frequency update unit 410. [ The activation count update unit 410 increments the delivered value SEL_OUT <0: C> by '1' and transfers the incremented value SEL_IN <0: C> to the bit line selector BS. The increased value (SEL_IN <0: C>) delivered to the bit line selector (BS) is transferred to a second memory cell (C2) connected to the selected one or more bit lines of the plurality of second memory cells C2).

(2) initializing the values stored in the second memory cells C2 connected to the selected one or more bit lines

The activation count updating unit 410 reads the value stored in the plurality of second memory cells C2 connected to the activated word line in response to the refresh command REF when the memory 310 performs the refresh operation. The bit line selection unit BS transfers the value stored in the second memory cells C2 connected to one or more selected bit lines among the read values to the activation frequency update unit 410. [ The activation count update unit 410 initializes the transferred value SEL_OUT <0: C> to an initial value (for example, '0') and outputs the initialized value SEL_IN <0: C> (BS). The initialized value SEL_IN <0: C> transferred to the bit line selector BS is transferred to a second memory cell connected to the selected one or more bit lines of the plurality of second memory cells C2 connected to the activated word line C2).

When the memory 310 performs a special repress operation, the activation count updating unit 410 updates the value stored in the plurality of second memory cells C2 connected to the activated word line in response to the active command ACT, do. The bit line selection unit BS transfers the value stored in the second memory cells C2 connected to one or more selected bit lines among the read values to the activation frequency update unit 410. [ The activation count update unit 410 initializes the transferred value SEL_OUT <0: C> to an initial value (for example, '0') and outputs the initialized value SEL_IN <0: C> (BS). The initialized value SEL_IN <0: C> transferred to the bit line selector BS is transferred to a second memory cell connected to the selected one or more bit lines of the plurality of second memory cells C2 connected to the activated word line C2).

For the above operation, the activation frequency update unit 410 includes a transfer signal generation unit 411 and a storage value update unit 412.

The transfer signal generating unit 411 activates the first transfer signal SELF_RD in response to the active command ACT or the refresh command REF and outputs the transfer signal SELF_RD after the predetermined time elapses after the first transfer signal SELF_RD is activated 2 transfer signal SELF_WT.

The transmission signal generation unit 411 activates the first transmission signal SELF_RD after the first time from when the active command ACT or the refresh command REF is applied from the command decoder 440. Here, the first time may be a time tRCD (Ras to Cas Delay, a time at which the charge of the bit line BL is sufficiently distributed after the RAS signal is activated to amplify the bit line sense amplifier data of the bit line). Next, the transfer signal generation unit 411 activates the second transfer signal SELF_WT after a second time from the activation of the first transfer signal SELF_RD. Here, the second time is a time when the value output from the second memory cell C2 connected to the selected one or more bit lines of the plurality of second memory cells C2 connected to the activated word line is updated by the stored value updating unit 412 May be the time it takes to complete.

For this operation, the transmission signal generation unit 411 includes a first transmission signal generation unit 411A for generating the first transmission signal SELF_RD by delaying the active command ACT or the refresh command REF by a first time, And a second transmission signal generator 411B for generating a second transmission signal SELF_WT by delaying the first transmission signal SELF_RD by a second time. The first transmission signal generation unit 411A and the second transmission signal generation unit 411B may delay their input in synchronization with a clock signal or may delay their input without being synchronized with a clock signal It is possible.

The bit line selection unit BS selects one or more bit lines of the first to Mth bit lines BL1 to BLM in response to the repair information REPAIR <0: B> (SEL_OUT <0: C>) output from the second memory cell C2 connected to one or more selected bit lines of the second memory cell C2 to the stored value updating unit 412. The stored value update unit 412 receives and updates the value (SEL_OUT <0: C>) transmitted from the bit line selection unit BS in response to the first transfer signal SELF_RD, and updates the updated value SEL_IN < : C >) to the bit line selector BS in response to the second transmission signal SELF_WT. The bit line selection unit BS selects a value (SEL_IN <0: C>) updated in response to the repair information REPAIR <0: B> Line. Thus, the updated value SEL_IN <0: C> is written to the second memory cell C2 connected to the selected one or more bit lines of the plurality of second memory cells C2 connected to the activated word line.

For reference, 'SEL_OUT <0: C>' is a value output from one or more selected bit lines among the first to Mth bit lines BL1 to BLM, and the bit line selector (BS) Indicates the value passed. The SEL_IN <0: C> 'is a value input to one or more selected bit lines of the first to Mth bit lines BL1 to BLM, and is transmitted from the stored value updating unit 411 to the bit line selector BS Value.

In more detail, (1) when a word line corresponding to an address ADD <0: A> is activated in response to an active command ACT, a plurality of second memory cells C2 Value is transmitted to the bit line selection unit BS. The bit line selection unit BS transfers the values transferred through the selected one or more bit lines among the first to Mth bit lines BL1 to BLM to the storage value updating unit 412. [ The stored value update unit 412 receives the value transmitted from the bit line selection unit BS when the first transfer signal SELF_RD is activated and internally increases it by '1'. When the second transmission signal SELF_WT is activated, the increased value is transmitted to the bit line selector BS. The bit line selection unit BS transfers the value delivered from the stored value update unit 412 to one or more selected bit lines among the first to Mth bit lines BL1 to BLM, To the second memory cell C2 connected to the selected one or more bit lines among the plurality of second memory cells C2 connected to the second memory cell C2.

(2) The stored value updating unit 412 initializes the value transferred from the bit line selecting unit BS during the refresh operation or the special refresh operation, and transfers the value to the bit line selecting unit BS. The method by which the bit line selection unit (BS) transfers the signal is the same as described above.

When the first transfer signal SELF_RD is activated after a predetermined time after the refresh command REF is activated in the refresh operation, the value transmitted from the bit line selector BS is input. At this time, the value transferred in response to the refresh signal REFPW activated during the refresh time tRFC for one cycle (1-cycle) is initialized to an initial value. When the second transmission signal SELF_WT is activated, the initial value is transmitted to the bit line selector BS.

When the word line corresponding to the address ADD <0: A> is activated in response to the active command ACT in the special refresh operation, the first transfer signal SELF_RD) is activated, the value transmitted from the bit line selector BS is input. At this time, the value transferred in response to the special refresh signal (TRREN) activated in the special refresh operation is initialized to the initial value. When the second transmission signal SELF_WT is activated, the initial value is transmitted to the bit line selector BS.

When the value increased or updated by the stored value updating unit 412 is stored in the selected one or more second memory cells C2 among the plurality of second memory cells C2 connected to the activated word line, Is completed.

The warning signal generator 420 compares the updated value (UP_OUT <0: C>, shown in FIG. 6) with the stored value updating unit 412 and the information REF <0: C> And generates a warning signal ALERT according to the comparison result. The contents of the above values will be described later in the description of FIG. If UP_OUT <0: C> 'has a value greater than' REF <0: C> '(or' UP_OUT <0: C> 'is greater than' REF <0: C> ') Is greater than or equal to the reference number, the alarm signal ALERT is activated. Disable the alert signal (ALERT) if 'UP_OUT <0: C>' is less than 'REF <0: C>'. The reference frequency information REF &lt; 0: C &gt; may be a preset value in the memory 310 or a value stored in the memory 310 from outside. This value can be set differently depending on the operating environment of the memory, the performance of the memory, and the like.

The alarm signal ALERT may be transmitted to the memory controller 320 and the memory controller 320 may control the memory 310 to immediately perform a special refresh operation when the alarm signal ALERT is activated or when the alarm signal ALERT is activated And may control the memory 310 to perform a special refresh operation immediately after a predetermined time elapses.

The address storage unit 430 stores the address ADD <0: A> when the alert signal ALERT is activated. That is, when the alert signal ALERT is activated, the address ADD < 0: A > corresponding to the currently activated word line is stored. Activation of the warning signal ALERT means that the address ADD < 0: A > corresponding to the currently activated word line corresponds to the above-mentioned excess address. In performing a special repress operation, the memory controller 320 needs an excess address, so it may store the excess address in the memory 310 in the address storage 430 and forward it to the memory controller 320 as needed .

The memory according to the present invention uses the memory cells connected to each word line to store the number of activations in the corresponding word line. At this time, if a memory cell storing the number of times of activation of the word line or a bit line connected to the memory cell is defective, the special refresh operation can not be performed properly. Therefore, the memory according to the present invention detects a bit line (or a memory cell) in which a defective bit line (or a memory cell) is tested through an extra bit in a memory cell for storing the number of activations of the word line and a bit line to which the memory cell is connected, The special refresh operation can be smoothly performed by storing the number of activations of the word line in the memory cells connected to the bit lines except for the line.

5 is a configuration diagram of the bit line selection unit (BS) of FIG.

And includes a first selector 510 and a second selector 520, as shown in FIG. The first selector 510 selects one or more bit lines of the first through M th bit lines BL1 through BLM in response to the repair information REPAIR <0: B> To the output information (SEL_OUT < 0: C >). The second selector 520 selects one or more bit lines of the first through M th bit lines BL1 through BLM in response to the repair information REPAIR <0: B>, and outputs the input information SEL_IN <0: C &Gt;) to the selected one or more bit lines. The output information SEL_OUT <0: C> is a value transmitted from the bit line selection unit BS to the stored value updating unit 412. The input information SEL_IN <0: C> To the bit line selector BS.

Repair information (REPAIR < 0: B &gt;) includes information on the address of the bit line where a failure occurs. The first selector 510 selects one or more bit lines in which defects have not occurred in the first to Mth bit lines BL1 to BLM in response to the repair information REPAIR <0: B> The unit 520 selects the same bit line as the first selector 510.

FIG. 6 is a configuration diagram of the stored value updating unit 412 of FIG.

6, the stored value updating unit 412 includes an adder 620 for incrementing a value input to the input terminal IN by a predetermined value and outputting the value to the output terminal OUT, a first transmission signal SELF_RD A first transfer unit 610 for transferring the value SEL_OUT <0: C> output from the bit line selection unit BS to the input terminal IN of the adder 620, A second transfer unit 630 for transferring the value output to the output terminal OUT of the adder 520 to the bit line selector BS when the first transfer signal SELF_WT is activated, And a transfer control unit 640 for controlling the first transfer unit 610 and the second transfer unit 630 in response to the control signal SELF_WT.

The stored value updating unit 412 will be described with reference to FIG.

The transfer control unit 640 generates the interval signal SELF_WTS and the strobe signal SELF_YI in response to the first transfer signal SELF_RD and the second transfer signal SELF_WT. The interval signal SELF_WTS is a signal indicating whether the value stored in the second memory cell C2 connected to the currently activated word line is outputted or the interval storing the updated value in the second memory cell C2.

(Low) when the interval signal SELF_WTS is inactive (high), and the second (second) memory cell C2 connected to the activated word line when the interval signal SELF_WTS is inactive And indicates a period for outputting the value stored in the memory cell C2. The transfer control unit 640 deactivates the segment signal SELF_WTS when the first transfer signal SELF_RD is activated and activates the segment signal SELF_WTS when the second transfer signal SELF_WT is activated. The transfer control unit 640 activates the strobe signal SELF_YI for a predetermined period when the first transfer signal SELF_RD or the second transfer signal SELF_WT is activated.

When the first transmission signal SELF_RD is activated, the first transmission unit 610 transmits a value (SEL_OUT <0: C>) transmitted from the bit line selection unit BS to the input unit of the adder 620, <0: C> '. In more detail, the first transfer unit 610 selects one of the values output from the plurality of second memory cells C2 connected to the activated word line in response to the interval signal SELF_WTS and the strobe signal SELF_YI, 0: C> ', which is the input signal of the adder 620, to the selected value SEL_OUT <0: C> The first transfer unit 610 transfers the value SEL_OUT <0: C> from the bit line selector BS to the UP_IN <0: C> when the strobe signal SELF_YI is activated when the interval signal SELF_WTS is inactivated, C>.

The adder 620 generates a value obtained by adding a predetermined value to the value of the signal UP_IN <0: C> input to the input terminal IN of its own and outputs this value UP_OUT <0: C> (OUT). The adder 620 may be a general adder for generating a value obtained by adding '1' to the input value.

When the second transmission signal SELF_WT is activated, the second transfer unit 630 transfers a value UP_OUT <0: C> to a value SEL_IN <0: C> to be transmitted to the bit line selector BS, Initialize SEL_IN <0: C>'. In more detail, the second transfer unit 630 activates the strobe signal SELF_YI when the interval signal SELF_WTS is activated when both of the signals 'REFPW' and 'TRREN' are deactivated 'UP_OUT <0: C>' to 'SEL_IN <0: C>'. On the other hand, when the strobe signal SELF_YI is activated when the period signal SELF_WTS is activated when one of the signals' REFPW 'and' TRREN 'is activated, the second transmission unit 630 outputs' SEL_IN < .

Referring again to FIG. 4, the core circuit according to one embodiment of the present invention will be described.

4, the core circuit includes a first cell array CA1 including a plurality of first memory cells C1 connected to first through Nth word lines WL1 through WLN, a first cell array CA1 including repair information REPAIR A bit line selector BS and first to Nth word lines WL1 to WLN for selecting one or more bit lines of the first to Mth bit lines BL1 to BLM in response to the first to Nth bit lines BL0 to BLn And connected to each of the first to Mth bit lines BL1 to BLM. When the bit line to which the first bit line WL1 is connected is selected, the first to Nth word lines WL1 to WLN, And a second cell array (CA2) including a plurality of second memory cells (C2) storing the number of times.

The method of storing and updating the number of times the word line is activated in the second cell array CA2 of the core circuit is the same as described above in the description of FIG. 3 and FIG.

The core circuit includes a memory cell for storing the number of activations of the word line and an extra bit line to which the memory cell is connected to detect a defective bit line (or memory cell) The special refresh operation can be smoothly performed by storing the number of activations of the word line in the memory cells connected to the lines.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (26)

A first cell array including a plurality of first memory cells connected to respective ones of the first to Nth word lines;
A bit line selector for selecting one or more bit lines of the first through M th bit lines in response to the repair information;
And a word line connected to each of the first to Nth word lines and connected to each of the first to Mth bit lines and connected to the first to the N &lt; th &gt; A second cell array including a plurality of second memory cells for storing the number of times the first memory cell is turned on; And
An activation time updating unit for updating a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines,
&Lt; / RTI &gt;
The method according to claim 1,
The bit line selector
And transfers the value output from the selected one or more bit lines to the activation number updating unit in response to the repair information, and transfers the value output from the activation number updating unit to the selected one or more bit lines.
The method according to claim 1,
The activation frequency updating unit
In response to an active command, increases the value stored in the second memory cells connected to the selected one or more bit lines of the plurality of second memory cells connected to the word line corresponding to the address.
The method according to claim 1,
The activation frequency updating unit
And a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines when the memory performs the refresh operation Memory to initialize.
The method according to claim 1,
The activation frequency updating unit
When the memory operates in the special refresh mode, a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines is initialized Memory.
The method according to claim 1,
And activating a warning signal if the number of activation of the word line corresponding to the address stored in the second memory cell connected to the selected one or more bit lines of the plurality of second memory cells connected to the word line corresponding to the address is equal to or greater than a reference number, The warning-
&Lt; / RTI &gt;
The method according to claim 6,
When the warning signal is activated,
&Lt; / RTI &gt;
A first cell array including a plurality of first memory cells connected to respective ones of the first to Nth word lines;
A bit line selector for selecting one or more bit lines of the first through M th bit lines in response to the repair information;
The first to the N-th word lines are connected to the first to M-th bit lines, respectively, and when the bit line to which the first to N-th word lines are connected is connected, A second cell array including a plurality of second memory cells storing a count;
A transfer signal generator activating a first transfer signal in response to an active command and activating a second transfer signal after the first transfer signal is activated and a predetermined time elapses; And
A second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the word line corresponding to the address of the first to Nth word lines in response to the first transfer signal, And responsive to the second transfer signal for transferring the increased value to a second memory cell coupled to the selected one or more bit lines of the plurality of second memory cells coupled to the word line corresponding to the address, Updating unit
&Lt; / RTI &gt;
9. The method of claim 8,
The bit line selector
And transfers the value output from the selected one or more bit lines to the stored value updating unit in response to the repair information and transfers the value output from the stored value updating unit to the selected one or more bit lines.
10. The method of claim 9,
The stored value update unit
Wherein when the memory performs a refresh operation, an initial value is applied to a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines Memory to pass.
10. The method of claim 9,
The stored value update unit
When the memory operates in the special refresh mode, transfers an initial value to a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines Memory.
9. The method of claim 8,
The transmission signal generator
Activating the first transfer signal in response to a refresh command and activating a second transfer signal after the first transfer signal is activated and a predetermined time elapses.
10. The method of claim 9,
The stored value update unit
An adder for increasing a value input to an input terminal and outputting the increased value to an output terminal;
A first transmission unit for transmitting the value output from the bit line selection unit to the input of the adder when the first transmission signal is activated; And
And a second transfer unit for transferring a value output to the output terminal of the adder to the bit line selector when the second transfer signal is activated,
&Lt; / RTI &gt;
10. The method of claim 9,
The transmission signal generator
Activating the first transfer signal after a first time when the active command or the refresh command is applied and activating the second transfer signal after a second time when the first transfer signal is activated. A first cell array including a plurality of first memory cells connected to the first to Nth word lines, and a second cell array connected to each of the first to Nth word lines and connected to each of the first to Mth bit lines, And a second cell array including a plurality of second memory cells for storing the number of activated word lines of the first to Nth word lines when a connected bit line is selected, wherein the first to N &lt; th &gt; A memory for generating a warning signal when the number of activated word lines is equal to or greater than a reference number; And
In a special refresh mode, applies to the memory one or more adjacent addresses having an excess address corresponding to a word line whose activation count is equal to or greater than the reference number and a value adjacent to the excess address,
&Lt; / RTI &gt;
16. The method of claim 15,
The memory
A bit line selection unit for selecting one or more bit lines of the first to M th bit lines in response to the repair information,
&Lt; / RTI &gt;
16. The method of claim 15,
The memory controller
And to cause the memory to enter the special refresh mode when the warning signal is activated.
16. The method of claim 15,
The memory
An activation frequency update unit for updating a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines;
Generating a warning signal for activating a warning signal if the number of activations of the word line corresponding to the address stored in the second memory connected to the selected bit line among the plurality of second memory cells connected to the word line corresponding to the address is equal to or greater than a reference number part; And
When the warning signal is activated,
&Lt; / RTI &gt;
19. The method of claim 18,
The activation frequency updating unit
In response to the active command, a value stored in a second memory cell coupled to the selected one or more bit lines of the plurality of second memory cells coupled to the word line corresponding to the address.
19. The method of claim 18,
The activation frequency updating unit
And initializing a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines when the memory performs the refresh operation Memory system.
19. The method of claim 18,
The activation frequency updating unit
A memory for initializing a value stored in a second memory cell connected to the selected bit line among the plurality of second memory cells connected to the activated word line among the first to Nth word lines when the memory operates in a special refresh mode, system.
16. The method of claim 15,
The memory
And a plurality of word lines, which are activated in the first to Nth word lines in response to part or all of the active command, the excess address, and the selected one or more adjacent addresses in operation in the special refresh mode, And activating the adjacent word lines.
A first region including a plurality of first memory cells connected to each of the first to Nth word lines;
A bit line selector for selecting one or more bit lines of the first through M th bit lines in response to the repair information; And
And a word line connected to each of the first to Nth word lines and connected to each of the first to Mth bit lines and connected to the first to the N &lt; th &gt;Lt; RTI ID = 0.0 &gt; cell array &lt; / RTI &gt; comprising a plurality of second memory cells
&Lt; / RTI &gt;
24. The method of claim 23,
A plurality of second memory cells connected to the selected one of the plurality of second memory cells connected to the activated word line among the first to Nth word lines when the active command is applied, Circuit.
24. The method of claim 23,
And initializes a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines when performing the refresh operation.
24. The method of claim 23,
A core circuit for initializing a value stored in a second memory cell connected to the selected one or more bit lines among the plurality of second memory cells connected to the activated word line among the first to Nth word lines when the special refresh operation is performed, .

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