KR20140078301A - data input/output apparatus - Google Patents

data input/output apparatus Download PDF

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Publication number
KR20140078301A
KR20140078301A KR1020120147521A KR20120147521A KR20140078301A KR 20140078301 A KR20140078301 A KR 20140078301A KR 1020120147521 A KR1020120147521 A KR 1020120147521A KR 20120147521 A KR20120147521 A KR 20120147521A KR 20140078301 A KR20140078301 A KR 20140078301A
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South Korea
Prior art keywords
control signal
data
signal
activated
gio
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KR1020120147521A
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Korean (ko)
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양선석
권기창
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에스케이하이닉스 주식회사
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Priority to KR1020120147521A priority Critical patent/KR20140078301A/en
Publication of KR20140078301A publication Critical patent/KR20140078301A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

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Abstract

The present invention relates to a data input / output device for a stand-by operation and includes a plurality of drivers capable of performing a stand-by operation; And a plurality of control signals for controlling input and output timings of data for each of a plurality of drivers and a pulse control for generating a common enable signal which is commonly connected to a plurality of drivers to control a desk operation according to a desk mode signal And a signal generator.

Description

[0001] DATA INPUT / OUTPUT APPARATUS [0002]

The present invention relates to semiconductor circuits, and more particularly to data input / output techniques.

A serial to diserial (SERDES) scheme is used to reduce the number of global lines, which are signal lines for transferring data from a semiconductor device, particularly a semiconductor memory device, to a data output pad in half. A typical SERDES method is a method in which the number of bits of data input / output simultaneously is sequentially transferred to a global line. For example, in the case of outputting 8-bit data at the same time, the number of global lines can be reduced by dividing by 4 bits and sequentially transmitting to 4 global lines.

In a conventional semiconductor memory device, a burst length (BL) fixed by a mode register set (MRS) is 8, or a burst length (BL) is 8 or On the fly BL8 OTF) is activated, two signals are required to perform two data accesses to one global line. Generally, one access pulse control signal is generated by an external command, and the second access pulse control signal is generated by delaying the first access pulse control signal so that data is transferred to each access pulse control signal Sync twice. That is, two access pulse control signals must be generated by one external command. On the other hand, when the burst length BL is 4 or On the fly BL8 (OTF) is inactivated, one access pulse control signal is generated by one external command.

Hereinafter, a conventional data input / output device will be described with reference to the accompanying drawings.

1 is a block diagram of a data input / output device in a conventional semiconductor memory device.

1, a data input / output device in a conventional semiconductor memory device includes a bank A 10, a GIO driver A 15 of a bank A, a bank B 20, a GIO driver B 25 of a bank B, And a generating unit 30.

The bank A 10 and the bank B 20 are memory cell arrays of a constant size of the semiconductor memory device, and the desde operation can be performed on a bank-by-bank basis. Therefore, the bank A 10 and the bank B 20 have a first GIO driver 15 and a second GIO driver 25, respectively, which can perform the stand-by operation mode.

The control signal generation unit 30 outputs two control signals required for the SERDES output for each bank in response to an external command. The bank A 10 and the first GIO driver 15 generate a control signal The first and second pulse control signals CASP_BKA and ICASP_BKA and supplies the third and fourth pulse control signals CASP_BKA and ICASP_BKA to the bank B 20 and the second GIO driver 25, respectively.

2 is a timing diagram of a data input / output device in a read operation in the conventional semiconductor memory device of FIG.

Referring to FIG. 2 and FIG. 1, in the case of the first section (1) of BL = 8 operation for the bank A 10, the control signal generator 30 responds to an external command for reading When the first and second pulse control signals CASP_BKA and ICASP_BKA are generated and supplied to the first GIO driver 15, the first GIO driver 15 generates a first driver signal (CASP_BKA) synchronized with the first pulse control signal CASP_BKA GIODRVA_1ST, not shown in FIG. 1), sends a first data bit to the GIO line GIO and a second driver signal GIODRVA_2ND (not shown in FIG. 1) synchronized to the second pulse control signal ICASP_BKA, And transmits a second data bit to the GIO line GIO in response to the GIO line GIO to sequentially transmit the two data bits to the GIO line GIO.

Only the third pulse control signal CASP_BKB for the bank B 20 is activated in response to an external command for read because the second section (2) is for the operation of BL = 4 for the bank B 20 And the second GIO driver 25 responds to the third driver signal GIODRVB_1ST (not shown in FIG. 1) synchronized with the third pulse control signal CASP_BKB to send the data bit to the GIO line GIO do. The third section (3) corresponds to a BL = 4 operation for the bank A (10), and the fourth section (4) corresponds to a BL = 8 operation for the bank B (20) .

As described above, the data input / output device of the prior art requires pulse control signals of two different timings for controlling the GIO driver in each bank of the semiconductor memory device, which is a unit in which the deserial operation is performed. Therefore, There is a problem that wiring for a pulse control signal necessary for the desk operation increases and becomes complicated.

Embodiments of the present invention provide a data input / output device capable of reducing the wiring for the pulse control signal used in the write operation, simplifying the wiring complexity, and increasing the net die.

A data input / output device according to an embodiment of the present invention includes a first driver capable of performing a despread operation in response to a first control signal and a common enable signal; A second driver capable of performing a desk operation in response to a second control signal and a common enable signal; And a pulse control signal generator for outputting first and second control signals for controlling the input and output timings of the respective data of the first and second drivers and a common enable signal for controlling whether or not the desk operation is performed in accordance with the secondary mode signal can do.

According to another aspect of the present invention, there is provided a data input / output apparatus comprising: a plurality of drivers capable of performing a desdeath operation; And a plurality of control signals for controlling input and output timings of data for each of a plurality of drivers and a pulse control for generating a common enable signal which is commonly connected to a plurality of drivers and which controls whether or not a desk operation is performed in accordance with the desk mode signal And a signal generator.

The embodiment according to the present invention based on the solution of the above-mentioned problem can increase the net die by reducing the area of the wiring occupied by the pulse control signal used for the desde operation and simplifying it.

1 is a block diagram of a data input / output circuit in a conventional semiconductor memory device.
2 is a timing chart of a data input / output circuit in a read operation in the conventional semiconductor memory device of FIG. 1
3 is a block diagram of a data input / output circuit in a semiconductor memory device according to an embodiment of the present invention.
4 is a circuit diagram showing one embodiment of the first and second strobe signal generators 170 and 270 of FIG.
5 is a diagram illustrating an embodiment of the pulse control signal generator (FIG. 3, 300) of FIG.
6 is a timing chart of a data input / output circuit in a read operation in the semiconductor memory device according to the embodiment of the present invention shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

3 is a block diagram of a data input / output circuit in a semiconductor memory device according to an embodiment of the present invention.

The conventional data input / output device independently supplies two pulse control signals having different timings for each GIO driver in order to perform data access twice. However, in the embodiment of the present invention, one pulse control signal is independently supplied for each GIO driver, and the other one pulse control signal is shared by the GIO drivers so that they can be controlled.

3, a data input / output circuit according to an embodiment of the present invention includes a bank A 100, a first GIO driver 150, a bank B 200, a second GIO driver 250, (300).

In the following description, when the first GIO driver 150 and the second GIO driver 250 are in the normal operation mode, the first data (in the case of the bank A, in the case of the data / bank B of BIO_A1, the data of the BIO_B1 (Two clocks) on the basis of the operation clock CLK, and the difference in timing when the second data (in the case of the bank A, the data of the BIO_A2 and the data of the BIO_B2 in the case of the bank B) 0 > is activated to a high level when the bank A is activated, and when the bank B is activated (for example, when the bank B is activated), the bank selection signal BK < 0: 1 & , BK < 1 > is activated to a high level). It is also assumed that a column address strobe pulse CASP having one cycle width of the operation clock CLK is generated in response to an external read command.

The bank A (100) and the bank B (200) are memory cell arrays of a fixed size of the semiconductor memory device, and the desde operation can be performed on a bank basis. And a first GIO driver 150 and a second GIO driver 250 capable of performing the stand-by operation mode for each of the bank A 100 and the bank B 200. Here, the data of the bank A 100 is divided into two data lines (BIO_A1, BIO_A2 (BIO_A1), BIO_A2 (BIO_A1), BIO_A2 ) At the same time. The data of the bank B 200 is simultaneously output to the two data lines (BIO_B1 and BIO_B2) in the same manner when the desk operation is performed in the bank B (200).

The first GIO driver 150 performs a write operation on the two data output lines BIO_A1 and BIO_A2 in the bank A 100. The first GIO driver 150 includes a first strobe generator 151 and a first switching driver 152 . For reference, the first GIO driver 150 is a general driver for sequentially driving a parallel signal and a serial signal according to a general SERDES operation.

The first strobe generating unit 151 outputs the first and second strobe signals DRVA_1 and DRVA_2 for the desk operation in response to the first control signal NEW_CASP_BKA and the common enable ICASP_EN. For example, when the first control signal NEW_CASP_BKA is activated and the common enable ICASP_EN is inactive, the first strobe signal DRVA_1 is activated and the first control signal NEW_CASP_BKA is activated and the common enable (ICASP_EN) is activated, the second strobe signal DRVA_2 can be activated.

The first switching driver 152 sequentially outputs the data stored in the two data output lines BIO_A1 and BIO_A2 to the GIO line GIO in response to the first and second strobe signals DRVA_1 and DRVA_2. When the first strobe signal DRVA_1 is activated, the first data of the data output line GIO_A1 is output to the GIO line GIO. When the second strobe signal DRVA_2 is activated, the second data of the data output line GIO_A2 To the GIO line GIO.

The second GIO driver 250 performs a write operation with respect to the first and second data output lines BIO_B1 and BIO_B2 of the bank B 200. The second GIO driver 250 includes a second strobe generator 251 and a second switching driver 252 ). For reference, the second GIO driver 250 is a general driver for sequentially driving a parallel signal and a serial signal according to a general SERDES operation.

The second strobe generating unit 251 outputs the third and fourth strobe signals DRVB_1 and DRVB_2 for the desk operation in response to the second control signal NEW_CASP_BKB and the common enable ICASP_EN. For example, when the second control signal NEW_CASP_BKB is activated and the common enable ICASP_EN is inactive, the third strobe signal DRVB_1 is activated, the second control signal NEW_CASP_BKB is activated and the common enable (ICASP_EN) is activated, the fourth strobe signal DRVB_2 may be activated.

The second switching driver 252 sequentially outputs the data stored in the two data output lines BIO_B1 and BIO_B2 to the GIO line GIO in response to the third and fourth strobe signals DRVB_1 and DRVB_2. When the third strobe signal DRVB_1 is activated, the first data of the data output line GIO_B1 is output to the GIO line GIO. When the fourth strobe signal DRVB_2 is activated, the second data of the data output line GIO_B2 To the GIO line GIO.

In the first and second GIO drivers (FIGS. 3, 150 and 250), the first and second strobe generators (FIGS. 3, 151 and 251) may be designed with the following circuit diagram. For reference, the first and second switching drivers 152 and 252 are conventionally used circuits, and a detailed description thereof will be omitted.

4 is a circuit diagram showing one embodiment of the first and second strobe generating units 151 and 251 of FIG.

4, the first and second control signals NEW_CASP_BKA and NEW_CASP_BKB, the common enable ICASP_EN, and the first to fourth strobe signals DRVA_1, DRVA_2, DRVB_1 and DRVB_2 are all at a high level It is assumed that it is activated.

Referring to FIG. 4A, the circuit for generating the first and third strobe signals DRVA_1 and DRVB_1 includes a first inverter INV1 receiving the first or second control signals NEW_CASP_BKA and NEW_CASP_BKB, A second inverter INV2 receiving the output of the first NAND gate NAND1 and a second inverter INV2 receiving one of the two control signals NEW_CASP_BKA and NEW_CASP_BKB and a common enable ICASP_EN, And a NOR gate NOR1 receiving the outputs of the first and second inverters INV1 and INV2 and outputting the first or third strobe signals DRVA_1 and DRVB_1.

Referring again to FIG. 4 (b), the circuit for generating the second and fourth strobe signals DRVA_2 and DRVB_2 generates one of the first or second control signals NEW_CASP_BKA and NEW_CASP_BKB and a common enable ICASP_EN And a third inverter INV3 receiving the outputs of the second NAND gate NAND2 and the second NAND gate NAND2 receiving the inputs and outputting the second or fourth strobe signals DRVA_2 and DRVB_2.

Here, the signals for the bank A 100 have two clock differences between the first control signal NEW_CASP_BKA and the common enable ICASP_EN based on the operation clock CLK, and the first strobe generator The difference between the first strobe signal DRVA_1 and the second strobe signal DRVA_2 supplied by the first strobe signal 151 must be two clocks difference based on the operation clock CLK. Therefore, the delay time passing through the circuit of Fig. 4 (a) and the delay time passing through Fig. 4 (b) must be the same or very small compared with one cycle of the operation clock (CLK).

Referring again to FIG. 3, the pulse control signal generator 300 generates a pulse control signal CLK, a column address strobe pulse CASP generated according to an external read command, a bank selection signal BK <0: 1> (NEW_CASP_BKA, NEW_CASP_BKB) and a common enable (ICASP_EN) in response to the first mode signal (BL8) and the second mode signal (BL8). The first GIO driver 150 of the bank A 100 independently supplies the corresponding first control signal NEW_CASP_BKA and the second GIO driver 250 of the bank B 200 supplies the corresponding second control And supplies the signal NEW_CASP_BKB independently. Also, one common enable (ICASP_EN) is commonly supplied to the first and second GIO drivers 150 and 250.

Here, the first control signal NEW_CASP_BKA is input to the first GIO driver 150 to control the timing of data input / output of the first GIO driver 150, and the second control signal NEW_CASP_BKB is input to the second GIO driver 150 250 to control the timing of data input / output of the second GIO driver 250. [ For example, the first GIO driver 150 inputs and outputs data in synchronization with the timing at which the first control signal NEW_CASP_BKA is activated, and synchronizes with the timing at which the second control signal NEW_CASP_BKB is activated, (250) can input and output data.

The pulse control signal generator (FIG. 3, 300) may be designed in the following circuit diagram.

5 is a diagram illustrating an embodiment of the pulse control signal generator (FIG. 3, 300) of FIG.

5, the first and second control signals NEW_CASP_BKA and NEW_CASP_BKB, the common enable ICASP_EN, the bank selection signals BK <0: 1>, and the sustained mode signals BL8 and the like All signals are assumed to be activated at a high level unless otherwise noted.

5, the internal signal generators 310 and 320 shown in FIG. 5A are provided with an operation clock (CLK), a column address strobe pulse (CASP), and a read operation (for example, (ICASEN10, ICASEN20, ICASPEN_IB) in response to the undermode mode signal BL8 which is activated in the first mode (when BL = 8). Finally, as shown in FIG. 5 (b), internal column address strobe pulses (CLK) delayed by two cycles of the operation clock (CLK) from the column address strobe pulse (CASP) by using the internal signals ICASEN10, ICASEN20 and ICASPEN_IB (ICASPEN_I) delayed by 1.5 cycles of the operation clock (CLK) while the pulse width is twice wider than the column address strobe pulse (ICASP) and the column address strobe pulse (CASP). For example, when the undesired mode signal BL8 is inactivated (for example, when a dead-time operation with a burst level of BL = 4 is not necessary), the internal signal generators 310 and 320 generate internal column address strobe pulses (ICASP) and internal common enable (ICASPEN_I).

5 (c), the internal column address strobe pulse ICASP, the internal common enable ICASPEN_I, the column address strobe pulse CASP, and the bank select signal (NEW_CASP_BKA, NEW_CASP_BKB) and a common enable (ICASP_EN) in response to the first and second control signals BK <0: 1>.

More specifically, when the first bank select signal (BK < 0 &gt;), which is the address signal of the bank A, is activated to a high level, the OR gate (BK <0>) to the other end of the first AND gate (AND1) and outputs the first control signal (BK <0>) to the other end of the first AND gate NEW_CASP_BKA). The OR gate OR receiving the column address strobe pulse CASP and the internal column address strobe pulse ICASP when the second bank selection signal BK <1>, which is the address signal of the bank B, And outputs the second control signal NEW_CASP_BKB to the other end of the second AND gate AND2 by receiving the second bank selection signal BK <1> to the other end of the second AND gate AND2 do. The common enable ICASP_EN delays the internal common enable ICASPEN_I and its delay value is most preferably the delay value of the OR gate OR and the first AND gate AND1 ) And the delay value of the second AND gate (AND2)).

Hereinafter, the overall operation of the data input / output circuit (FIG. 3) according to the embodiment of the present invention will be described.

FIG. 6 is a timing chart of a data input / output circuit in a read operation in the semiconductor memory device according to the embodiment of the present invention shown in FIG. 3; FIG.

Referring to FIGS. 6 and 3, when the first mode in which the bank A (Figures 3 and 100) requires a stand-by operation (for example, when the burst mode is 8 and the des-mode signal BL8 is activated The pulse control signal generator (FIG. 3, 300) supplies the first control signal NEW_CASP_BKA activated twice and the activated common enable ICASP_EN in the first section (1). The first GIO driver 150 outputs the first data (data of BIO_A1) to the GIO line GIO in response to the activation state of the first strobe signal DRVA_1 synchronized with the first activation timing of the first control signal NEW_CASP_BKA, (Data of BIO_A2) to the GIO line GIO in response to the activation state of the second strobe signal DRV_2 synchronized with the second activation timing of the first control signal NEW_CASP_BKA Output. Preferably, the period in which the common enable ICASP_EN is activated includes a second active period of the first control signal NEW_CASP_BKA, and a common enable signal is simultaneously applied to the second active period of the first control signal NEW_CASP_BKA The first strobe generator 151 of the first GIO driver 150 activates the second strobe signal DRVA_2 when the first strobe signal ICASP_EN is activated.

The second period (2) is a case of the second mode in which the bank B 20 is not required to perform the stand-by operation (for example, when the burst mode is 4 and the desk mode signal BL8 is deactivated) . In the second period (2), the pulse control signal generator (Fig. 3, 300) supplies the once activated second control signal NEW_CASP_BKB and the inactivated common enable ICASP_EN. The second GIO driver 250 outputs the first data (data of BIO_B1) to the GIO line GIO in response to the activation state of the third strobe signal DRVB_1 synchronized with the first activation timing of the second control signal NEW_CASP_BKB, . Here, since the common enable ICASP_EN is inactivated, the second GIO driver 250 deactivates the fourth strobe signal DRVB_2.

The third section (3) is a second mode in which the bank A (100) is not required to perform a stand-by operation, and the fourth section (4) Mode, it is the same as the above-described description, and a detailed description thereof will be omitted.

As described above, the data input / output circuit according to the embodiment of the present invention independently uses one control signal for each GIO driver for the desert operation, and by commonly using another control signal, It is possible to reduce the area occupied by the wiring and simplify the wiring complexity, thereby increasing the net die.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

100: Bank A
150: 1st GIO driver
200: bank B
250: Second GIO driver
300: Pulse control signal generator

Claims (6)

A first driver capable of performing a desk operation in response to a first control signal and a common enable signal;
A second driver capable of performing a desk operation in response to a second control signal and the common enable signal; And
A pulse control signal generation unit for outputting the first and second control signals for controlling the input and output timings of the respective data of the first and second drivers and the common enable signal activated in the stand-
A data input / output device

The method according to claim 1,
The input / output timing of each data of the first or second control signal is
Is synchronized with a timing at which the first or second control signal is activated.

3. The method of claim 2,
The first or second control signal
The data input / output device is activated once when it is not in the stand-by operation mode, and is activated twice when it is in the stand-by operation mode.
The method of claim 3,
The common enable signal
And a period during which the first or second control signal is activated during a second dead time operation mode includes a second active period of the first or second control signal.
The method according to claim 1,
The driver
A first strobe generator for outputting first and second strobe signals according to the common enable signal and the control signal; And
A switching driver for outputting first data according to the first strobe signal and for outputting second data according to the second strobe signal,
And a data input / output device
A plurality of drivers capable of performing a stand-by operation; And
A pulse control signal generator for generating a plurality of control signals for respectively controlling input and output timings of data for each of the plurality of drivers and a common enable signal connected in common to the plurality of drivers and activated in a desk operation mode,
A data input / output device





KR1020120147521A 2012-12-17 2012-12-17 data input/output apparatus KR20140078301A (en)

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Publications (1)

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