KR20140076798A - Manufacturing method of a semiconductor memory device - Google Patents

Manufacturing method of a semiconductor memory device Download PDF

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Publication number
KR20140076798A
KR20140076798A KR1020120145242A KR20120145242A KR20140076798A KR 20140076798 A KR20140076798 A KR 20140076798A KR 1020120145242 A KR1020120145242 A KR 1020120145242A KR 20120145242 A KR20120145242 A KR 20120145242A KR 20140076798 A KR20140076798 A KR 20140076798A
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South Korea
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film
polysilicon
pattern
forming
metal
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KR1020120145242A
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Korean (ko)
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양영호
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에스케이하이닉스 주식회사
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Priority to KR1020120145242A priority Critical patent/KR20140076798A/en
Publication of KR20140076798A publication Critical patent/KR20140076798A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention relates to a technique for forming a second silicon pattern on a sidewall of a first silicon pattern protruded from an insulating film and then performing a silicidation process so that the second silicon pattern reacts with the metal during the silicidation process even if the line width of the first silicon pattern is narrow. It is possible to secure a sufficient amount of silicon.

Description

[0001] The present invention relates to a method of manufacturing a semiconductor memory device,

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device including a silicide process.

In order to highly integrate the semiconductor memory device, the size of the patterns constituting the semiconductor memory device is reduced. As the size of the patterns is reduced, as the resistance of the conductive pattern increases, measures for lowering the resistance of the conductive pattern are being developed.

A silicide process has been introduced as a method for reducing the resistance of the conductive pattern. A silicide process is a process of depositing a metal film on a silicon pattern and diffusing a metal from the metal film to a silicon pattern so as to react with the silicon of the silicon pattern to convert a part of the silicon pattern into a metal silicide.

The above-described line width of the silicon pattern can be reduced in the course of the silicide process. When the metal pattern is reacted with the silicon pattern having a reduced line width, there is a problem that the final conductive pattern formed through the silicide process is broken due to insufficient amount of silicon to react with the metal. As a result, malfunction of the semiconductor memory element is caused.

An embodiment of the present invention provides a method of manufacturing a semiconductor memory device capable of reducing the malfunction of a semiconductor memory device.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes: forming first polysilicon patterns on a substrate; Forming a first insulating layer having a height lower than the first polysilicon patterns between the first polysilicon patterns; Forming a second polysilicon pattern on a sidewall of the first polysilicon pattern; And forming a metal silicide film by siliciding the second polysilicon pattern and the first polysilicon pattern.

A second silicon pattern is formed on a sidewall of a first silicon pattern protruding from an insulating film, and then a silicidation process is performed. Thus, even if the line width of the first silicon pattern is narrow, It is possible to secure an area to be converted. Accordingly, the present invention can sufficiently secure the amount of silicon to react with the metal during the silicidation process, thereby reducing the malfunction of the semiconductor memory device.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
2 is a block diagram illustrating a memory system according to an embodiment of the present invention.
3 is a configuration diagram illustrating a computing system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limiting the scope of the invention to those skilled in the art It is provided to let you know completely.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1A, first polysilicon patterns 109 are formed on a semiconductor substrate 101. The first polysilicon patterns 109 may be a control gate of a NAND flash memory device. In this case, the dielectric film pattern 107, the data storage film pattern 105, and the gate insulating film pattern 103 may be further stacked under the first polysilicon patterns 109, respectively. An example of a process of forming the stacked gate G formed of the lamination structure of the gate insulating film pattern 103, the data storage film pattern 105, the dielectric film pattern 107 and the first polysilicon pattern 109 as described above Will be described in more detail as follows.

First, an impurity for forming a well (not shown) and an impurity for controlling a threshold voltage may be implanted into the semiconductor substrate 101. Thereafter, the surface of the semiconductor substrate 101 may be oxidized using a mixed gas of O 2 and H 2 , or an oxide film may be deposited on the semiconductor substrate 101 to form a gate insulating film. The gate insulating film may include a silicon oxide film. Thereafter, a process of annealing the gate insulating film at a high temperature in an NO or N 2 O atmosphere may be further performed to reduce the tunneling phenomenon of the hot carrier.

Then, an information storage film is formed on the gate insulating film. The information storage film may be formed of a nitride film capable of charge trapping, a polysilicon film, or an amorphous silicon film. Further, the information storage film may be formed of a doped polysilicon film containing P type or N type impurities. In this case, the information storage film may be formed in a structure in which a plurality of layers of doped polysilicon films having different impurity concentrations are stacked. In order to reduce the grain size of the doped polysilicon film, impurities such as C, N, and O can be implanted during the deposition of the doped polysilicon films.

Subsequently, after the element isolation region (not shown) of the semiconductor substrate 101 is exposed by etching the information storage film and the gate insulating film, a device isolation region of the semiconductor substrate 101 is etched to form a trench (not shown). Thereafter, the trench is filled with an insulating film (not shown), the surface of the insulating film is planarized, and then the height of the insulating film is lowered to a target height by an etching process to separate the active regions of the semiconductor substrate 101 ).

Thereafter, a dielectric film is formed on the entire structure where the device isolation film is formed. The dielectric film may be formed of a laminate of a silicon oxide film, a silicon nitride film, and a silicon oxide film. Alternatively, the dielectric film may be formed of a high-k dielectric film having a higher dielectric constant than the silicon oxide film. Examples of the high-dielectric film include a hafnium oxide film, a tantalum oxide film, and a zirconium oxide film.

Then, a first polysilicon film for a control gate is formed on the dielectric film. The first polysilicon film may be formed of a doped polysilicon film including N type or P type dopants. Thereafter, gate mask patterns are formed on the first polysilicon film. The gate mask pattern may be formed in a line type along the direction crossing the device isolation film and the active region. The first polysilicon film, the dielectric film, and the information storage film are etched by an etching process using these gate mask patterns as an etching barrier. At this time, the gate insulating film can be further etched. Thus, stacked gates G in which the gate insulating film pattern 103, the data storage film pattern 105, the dielectric film pattern 107, and the first polysilicon pattern 109 are stacked can be formed.

Thereafter, a first insulating film 111 filling the space between the gates G and separating the gates G is formed. The first insulating layer 111 may be formed of an oxide layer. Then, a step of planarizing the surface of the first insulating film 111 may be further performed. At this time, the gate mask pattern may be removed and the upper surface of the first polysilicon pattern 109 may be exposed.

Subsequently, a part of the thickness of the first insulating film 111 is further etched and a cleaning process is performed. The height h2 of the first insulating film 111 is formed to be lower than the height h1 of the gate pattern G. [ As a result, the first polysilicon pattern 109 protrudes from the first insulating film 111, and the sidewalls of the first polysilicon pattern 109 are partially exposed.

Next, a second polysilicon film 121 is formed along the surface of the first polysilicon pattern 109 and the surface of the first insulating film 111. The second polysilicon film 121 may be a doped polysilicon film or an unsupported polysilicon film.

A part of the first polysilicon pattern 109 may be lost during the etching process and the cleaning process of the first insulating film 111 described above. The second polysilicon film 121 can not only compensate for the lost amount of the first polysilicon pattern 109 but also increase the amount of silicon that will react with the metal during the subsequent silicidation process.

The embodiment of the present invention allows the second polysilicon film 121 to be formed along the step between the first insulating film 111 and the first polysilicon pattern 109. [ For this, the second polysilicon film 121 may be formed by a low pressure chemical vapor deposition (LP CVD) method or an atomic layer deposition (ALD) method. In addition, the thickness of the second polysilicon film 121 may be 10% to 20% of the width of the first polysilicon pattern 109.

Referring to FIG. 1B, a process of implanting impurities into the second polysilicon film 121 may be further performed. The impurity implantation angle, impurity implantation energy, impurity type, and the like can be controlled in various manners.

The impurity implantation may be performed to implant impurities into a part of the second polysilicon film 121 or may be performed to improve the electrical characteristics of the control gate by increasing the dopant concentration in the control gate . As the impurities, tetravalent elements such as carbon or N type impurities or P type impurities may be used. In particular, impurities of the same type as the impurity contained in the first polysilicon pattern 109 may be implanted into the second polysilicon film 121 to improve the electrical characteristics of the control gate. At this time, the impurity implantation angle can be tilted in various directions so that impurities can be uniformly injected into the second polysilicon film 121.

The impurity implantation angle may be a direction perpendicular to the surface of the semiconductor substrate 101 in order to implant impurities into a partial region of the second polysilicon film 121, Can be controlled to the deposition thickness (D). At this time, the impurity implantation region of the second polysilicon film 121 may be damaged.

Referring to FIG. 1C, the second polysilicon film 121 is etched to form a second polysilicon pattern 121P on the sidewalls of the first polysilicon pattern 109. As shown in FIG. The etching process of the second polysilicon film 121 may be performed by the following etching process without separately forming the etching barrier.

As one example, when an impurity is implanted into a partial region (hereinafter referred to as "first region") of the second polysilicon film 121 in the impurity implantation process described above with reference to FIG. 1B, The second polysilicon pattern 121P may be formed by selectively etching the first region. Here, the second polysilicon pattern 121P is a second region of the second polysilicon film 121 that is not damaged by the impurity injection energy because the impurity is not a target of the implantation process. The step of selectively etching the first region of the second polysilicon film 121 can be performed by a wet etching method using a mixture of NH 4 OH, H 2 O 2 , and H 2 O or a mixture containing HNO 3 have.

As another example, the second polysilicon film 121 may be etched to form the second polysilicon pattern 121P by an anisotropic dry etching method in which the etching amount in the direction perpendicular to the semiconductor substrate 101 is relatively large .

Referring to FIG. 1D, a metal film 131 for silicidation is formed along the surfaces of the first polysilicon pattern 109, the second polysilicon pattern 121P, and the first insulating film 111. The metal film 131 may include cobalt.

A buffer film may be further formed on the metal film 131 to prevent the metal film 131 from being oxidized during a subsequent annealing process for silicidation. As the buffer film, a laminate of titanium (Ti) and titanium nitride (TiN) may be used.

Referring to FIG. 1E, an annealing process is performed at a first temperature so that the metal film 131 and the first and second polysilicon patterns 109 and 121P can react with each other. The metal from the metal film 131 diffuses toward the first and second polysilicon patterns 109 and 121P at the first temperature. When the metal film 131 is formed of cobalt, cobalt diffuses toward the first and second polysilicon patterns 109 and 121P at a first temperature to form a part of the first polysilicon pattern 109 and the second polysilicon pattern 121P) changes to CoSi. In the embodiment of the present invention, the amount of silicon capable of reacting with the metal can be secured by the second polysilicon pattern 121P. Accordingly, in the embodiment of the present invention, it is possible to prevent the portion of the first polysilicon pattern 109 from being excessively high in content due to the insufficient amount of silicon to react with the metal.

Thereafter, the metal film 131 which has not reacted with the first and second polysilicon patterns 109 and 121P is removed. At this time, the buffer film formed on the metal film 131 is also removed. The removal process of the metal film 131 may be performed using a sulfuric acid (H 2 SO 4 ) mixture. The region where the metal content is excessively high can be removed during the removal process of the metal film 131 and the buffer film in the metal and silicon reaction regions. However, in the embodiment of the present invention, since the amount of silicon to be reacted with the metal is secured through the second polysilicon pattern 121P, the area of the region where the metal content is excessively high in the metal and silicon reaction regions can be reduced. It is possible to reduce the amount of loss of the reaction region of the catalyst.

Then, an annealing process is performed at a second temperature higher than the first temperature. Thus, a metal silicide film 141 having a resistance lower than that of the first and second polysilicon patterns 109 and 121P is formed. The metal silicide film 141 may be CoSi 2 formed at the first temperature and CoSi 2 that is phase-changed at the second temperature. CoSi 2 is a more stable phase than CoSi and has low resistance.

The metal silicide film 141 is formed by reacting a portion formed by reaction with the second polysilicon pattern 121P and a first region of the first polysilicon pattern 109 adjacent to the second polysilicon pattern 121P . The second region 109a of the first polysilicon pattern between the first insulating films 111 can remain without reacting with the metal. Since the metal silicide film 141 includes a portion reacting with the second polysilicon pattern 121P formed on the sidewall of the first polysilicon pattern 109, the width W1 of the second region 109a of the first polysilicon pattern And a width W2 larger than the width W2. The second region 109a of the first polysilicon pattern and the metal silicide film 141 can be used as the control gate pattern CG.

Since the metal silicide film 141 has a width W2 wider than the second region 109a of the first polysilicon pattern as described above, the volume of the metal silicide film 141 is ensured, The resistance can be reduced. Further, in the embodiment of the present invention, the area of the region where the metal content is excessively high in the metal and silicon reaction regions is reduced, thereby reducing the area of the metal and silicon reaction regions lost during the process of removing the metal film 131. Thus, the embodiment of the present invention can reduce the breakage of the control gate pattern CG due to the loss of the metal and silicon reaction regions, thereby reducing the malfunction of the semiconductor memory device.

Referring to FIG. 1F, the recess 151 is formed by etching the first insulating layer 111 by an etching process using the metal silicide layer 141 as an etching barrier. The first insulating film 111 may be etched using an HF mixture. The etching process of the first insulating film 111 may be performed by a wet process or a dry process.

Referring to FIG. 1G, a second insulating layer 161 is formed on the entire structure where the recessed region 151 is formed. The second insulating layer 161 may be formed of an oxide layer.

During the deposition process for forming the second insulating film 161, the region between the neighboring metal silicide films 141 is first filled before the recessed region 151 is filled, A gap 171 may be formed. This is possible because the top width of the metal silicide film 141 is formed broad by the second polysilicon pattern 121P.

The air-gap 171 can reduce parasitic capacitances between neighboring information storage film patterns 105 and parasitic capacitors between neighboring control gates CG.

2 is a block diagram illustrating a memory system according to an embodiment of the present invention.

Referring to FIG. 2, a memory system 1100 according to an embodiment of the present invention includes a non-volatile memory element 1120 and a memory controller 1110.

Nonvolatile memory element 1120 includes a semiconductor memory element formed through the process described above with reference to FIGS. 1A through 1G. In addition, the non-volatile memory element 1120 may be a multi-chip package composed of a plurality of flash memory chips.

The memory controller 1110 is configured to control the non-volatile memory element 1120 and may include an SRAM 1111, a CPU 1112, a host interface 1113, an ECC 1114, a memory interface 1115 . The SRAM 1111 is used as an operation memory of the CPU 1112 and the CPU 1112 performs all control operations for data exchange of the memory controller 1110 and the host interface 1113 is connected to the memory system 1100 And a host computer. The ECC 1114 also detects and corrects errors contained in the data read from the non-volatile memory element 1120 and the memory interface 1115 performs interfacing with the non-volatile memory element 1120. In addition, the memory controller 1110 may further include a ROM or the like for storing code data for interfacing with a host.

Thus, the memory system 1100 having the configuration can be a memory card or a solid state disk (SSD) in which the nonvolatile memory element 1120 and the controller 1110 are combined. For example, if the memory system 1100 is an SSD, the memory controller 1110 may be connected to the external (e.g., via a USB), MMC, PCI-E, SATA, PATA, SCSI, ESDI, IDE, For example, a host).

3 is a configuration diagram illustrating a computing system according to an embodiment of the present invention.

3, a computing system 1200 according to an embodiment of the present invention includes a CPU 1220 electrically coupled to a system bus 1260, a RAM 1230, a user interface 1240, a modem 1250, a memory 1250, System 1210 shown in FIG. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile deem, .

The memory system 1210 may be comprised of a nonvolatile memory 1212 and a memory controller 1211, as described above with reference to FIG.

101: semiconductor substrate 103: gate insulating film pattern
105: information storage film pattern 107: dielectric film pattern
109: first polysilicon pattern 121: second polysilicon film
121P: second polysilicon pattern 111: first insulating film
141: metal silicide film 151: recessed region
161: second insulating film 171: air-gap

Claims (5)

Forming first polysilicon patterns on a substrate;
Forming a first insulating layer having a height lower than the first polysilicon patterns between the first polysilicon patterns;
Forming a second polysilicon pattern on a sidewall of the first polysilicon pattern; And
And forming a metal silicide film by siliciding the second polysilicon pattern and the first polysilicon pattern. The method according to claim 1,
Wherein forming the second polysilicon pattern comprises:
Depositing a second polysilicon film along the surface of the first polysilicon pattern and the first insulating film;
Implanting an impurity into the second polysilicon film; And
And selectively etching the impurity-implanted region of the second polysilicon film. 3. The method of claim 2,
Wherein the step of selectively etching the impurity-implanted region of the second polysilicon film is performed using a mixture of NH 4 OH, H 2 O 2 , and H 2 O, or HNO 3 . The method according to claim 1,
Wherein forming the second polysilicon pattern comprises:
Depositing a second polysilicon film along the surface of the first polysilicon pattern and the first insulating film; And
And etching the second polysilicon film by an anisotropic dry etching method. The method according to claim 1,
Forming a recess region in the first insulating layer by etching the first insulating layer using the metal silicide layer as an etching barrier;
And forming a second insulating film on the entire structure where the metal silicide film and the recessed region are formed such that an air gap is defined in the recessed region.
KR1020120145242A 2012-12-13 2012-12-13 Manufacturing method of a semiconductor memory device KR20140076798A (en)

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