KR20140072367A - Nonvolatile memory device and operating method thereof - Google Patents

Nonvolatile memory device and operating method thereof Download PDF

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Publication number
KR20140072367A
KR20140072367A KR1020120139023A KR20120139023A KR20140072367A KR 20140072367 A KR20140072367 A KR 20140072367A KR 1020120139023 A KR1020120139023 A KR 1020120139023A KR 20120139023 A KR20120139023 A KR 20120139023A KR 20140072367 A KR20140072367 A KR 20140072367A
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data
output
control signal
input
memory device
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KR1020120139023A
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Korean (ko)
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이완섭
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에스케이하이닉스 주식회사
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Publication of KR20140072367A publication Critical patent/KR20140072367A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and an operation method thereof. A method of operating a nonvolatile memory device according to an embodiment of the present invention includes receiving or outputting data according to a control signal irrespective of a data input / output operation applied while a write control signal is activated, And receives or outputs the data whenever the signal transitions from a logic low to a logic high and from a logic high to a logic low.

Figure P1020120139023

Description

[0001] NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF [0002]

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a method of operating the same.

Semiconductor memory devices are generally classified as volatile memory devices and non-volatile memory devices. The volatile memory device loses the stored data when the power is turned off, but the non-volatile memory device can save the stored data even when the power is turned off. A non-volatile memory device includes various types of memory cells.

The nonvolatile memory device includes a flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) A phase change memory device using chalcogenide alloys, and a resistive memory device (RERAM) using a transition metal oxide.

Among nonvolatile memory devices, a flash memory device is classified into a NOR flash memory device and a NAND flash memory device depending on the connection state of a memory cell and a bit line. The NOR flash memory device has a structure in which two or more memory cell transistors are connected in parallel to one bit line. Thus, the NOR flash memory device has excellent random access time characteristics. On the other hand, the NAND flash memory device has a structure in which two or more memory cell transistors are connected in series to one bit line. This structure is called a cell string structure and requires one bit line contact per cell string. Therefore, the NAND flash memory device has excellent characteristics in the integrated circuit.

The NAND flash memory device not only has a high degree of integration but also has a disadvantage of slow operation speed. The NAND flash memory device performs reading and writing operations on a page basis due to its structural characteristics. Here, a page refers to a unit for simultaneously operating a plurality of memory cells shared in a word line. Since the NAND flash memory device performs the read and write operations in page units, the operation speed of the NAND flash memory device can be increased by increasing the data input or output throughput. In addition, by increasing the data input or output throughput of the NAND flash memory device, it is possible to reduce the time required for the test time of the NAND flash memory device. Accordingly, various methods for increasing the data input or output throughput of a NAND flash memory device have been studied.

An embodiment of the present invention is to provide a nonvolatile memory device with improved data input or output throughput and a method of operating a nonvolatile memory device to increase data input or output throughput.

A method of operating a nonvolatile memory device according to an embodiment of the present invention includes receiving or outputting data according to a control signal irrespective of a data input / output operation applied while a write control signal is activated, And receives or outputs the data whenever the signal transitions from a logic low to a logic high and from a logic high to a logic low.

Another nonvolatile memory device according to an embodiment of the present invention includes memory cells arranged in a region where bit lines and word lines cross each other; Control logic configured to control read, write and erase operations of the memory cells; And an input / output buffer block configured to receive data to be stored in the memory cells under control of the control logic from an external device or to output data read from the memory cells to the external device, And is configured to receive or output data whenever a control signal irrespective of a data input / output operation applied while a write control signal is activated transitions from a logic low to a logic high and from a logic high to a logic low.

According to an embodiment of the present invention, the data input or output throughput of the non-volatile memory device can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an exemplary connection relationship between a nonvolatile memory device and an external device. FIG.
2 is a block diagram illustrating an exemplary non-volatile memory device according to an embodiment of the present invention.
3 is a timing chart for explaining a data input method of a nonvolatile memory device according to an embodiment of the present invention.
4 is a timing chart for explaining a data output method of a nonvolatile memory device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein, It is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation of the scope of the appended claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / coupled " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an exemplary connection relationship between a nonvolatile memory device and an external device. FIG. Referring to FIG. 1, a user device 10 includes an external device 11, a first nonvolatile memory device 13, and a second nonvolatile memory device 15.

The external device 11 may be configured as any one of a host device, a memory controller, a test device, and the like. That is, the external device 11 may be configured as an apparatus for controlling the non-volatile memory devices 13 and 15. [

The external device 11 is connected to the non-volatile memory devices 13 and 15 via n channels due to physical limitations. Here, the channel means a physical path for transmitting the control signals CTR_SG for controlling the nonvolatile memory devices 13 and 15. In addition, the channel means a physical path for transmitting data Data between the external device 11 and the non-volatile memory devices 13 and 15.

Since the non-volatile memory devices 13 and 15 require (n / 2) channels for the transmission of control signals and data, the external device 11 can store up to two non-volatile memory devices 13 and 15) can be controlled. If the non-volatile memory devices 13 and 15 require (n / 2) channels for transmission of control signals and data, the external device 11 controls two or more non-volatile memory devices It will be well understood.

According to the embodiment of the present invention, only four input / output channels are used for data transfer of the nonvolatile memory devices 13 and 15. [ That is, the nonvolatile memory devices 13 and 15 sequentially write the 4-bit (partial) partial data transmitted through the four data input pins (I / O [3: 0] And generates the buffered partial data as 2-byte (2-Bytes) internal data. In addition, the non-volatile memory devices 13 and 15 buffer the 2-byte internal data, divide the buffered internal data into 4-bit sized partial data, and divide the divided partial data into four data output pins I / O [3: 0]) to the external device 11.

According to the embodiment of the present invention, since the number of channels for transferring data (or the number of input / output pins of nonvolatile memory devices 13 and 15) can be reduced, Lt; RTI ID = 0.0 > non-volatile < / RTI > memory devices. In addition, the non-volatile memory devices 13 and 15 generate partial data of 4-bit size as internal data of 2-byte size or internal data of 2-byte size as partial data of 4-bit size The data input or output throughput of the non-volatile memory devices 13 and 15 can be increased. An operation method for increasing the data input or output throughput of the data input / output pin reduced non-volatile memory device and the non-volatile memory devices 13 and 15 will be described in detail below.

2 is a block diagram illustrating an exemplary non-volatile memory device according to an embodiment of the present invention. 2, the nonvolatile memory device 100 includes a memory cell array 110, a row decoder 120, a column decoder 130, a data read / write block 140, an input / output buffer block 150, And control logic 160. The input / output buffer block 150 includes a partial data storage block 151.

The memory cell array 110 includes a plurality of memory cells arranged in an intersection region of the bit lines BL0 to BLn and the word lines WL0 to WLm. Each memory cell may store 1-bit data. Such a memory cell is called a single level cell. A single level cell is programmed to have a threshold voltage corresponding to an erase state and a program state. As another example, each memory cell may store 2-bit data or more. Such a memory cell is called a multi level cell. The multi-level cell is programmed to have a threshold voltage corresponding to either an erase state or a plurality of program states. The memory cell array 110 may be configured to have a single-layer array structure (also referred to as a two-dimensional array structure) or a multi-layer array structure (or a three-dimensional array structure) Can be implemented.

The row decoder 120 operates under the control of the control logic 160. The row decoder 120 is connected to the memory cell array 110 through the word lines WL0 to WLm. The row decoder 120 is configured to decode an externally input address. The row decoder 120 is configured to perform a selecting operation and a driving operation on the word lines (WL0 to WLm) in accordance with the decoding result.

The column decoder 130 operates under the control of the control logic 160. The column decoder 130 is connected to the memory cell array 110 through the bit lines BL0 to BLn. The column decoder 130 is configured to decode an externally input address. The column decoder 130 is configured to connect the bit lines BL0 to BLn and the data read / write block 140 in a predetermined unit according to the decoding result.

The data read / write block 140 operates under the control of the control logic 160. The data read / write block 140 is configured to operate as a write driver or as a sense amplifier, depending on the mode of operation. For example, the data read / write block 140 is configured to store the data input through the input / output buffer block 150 in the memory cells included in the memory cell array 110 during a program operation. As another example, the data read / write block 140 is configured to output data read from the memory cells included in the memory cell array 110 to the input / output buffer block 150 during a read operation.

The input / output buffer block 150 is configured to receive data from an external device (11 in FIG. 1) or output data to an external device. To this end, the input / output buffer block 150 may include a data latch circuit (not shown) and an output driving circuit (not shown).

The input / output buffer block 150 includes a partial data storage block 151. The partial data storage block 151 is configured to sequentially buffer 4-bit-sized partial data transmitted through four data input pins among data input pins (not shown). The partial data storage block 151 is configured to generate the buffered partial data into 2-byte-sized internal data. The internal data may be generated by combining four partial data of 4-bit size and storing the partial data in the partial data storage block 151 again. As another example, the internal data may be generated by sequentially providing the partial data buffered in the partial data storage block 151 to the data read / write block 140 in 2-byte order.

The partial data storage block 151 is configured to generate the internal data provided from the data read / write block 140 as partial data of 4-bit size. The partial data may be generated by dividing the internal data into 4-bit units and storing the divided data in the partial data storage block 151 again. As another example, the partial data may be generated by an operation of sequentially providing the internal data stored in the partial data storage block 151 to the data latch circuit (not shown) of the input / output buffer block 150 in 4-bit order .

The control logic 160 is configured to control all operations of the non-volatile memory device 100 in response to control signals provided from an external device. For example, the control logic 160 may control the read, write (or program), and erase operations of the non-volatile memory device 100. In addition to the general read, program, erase operations, the control logic 160 may also control certain operations, such as a test mode. Here, the test mode means a specific operation mode provided for testing the non-volatile memory device 100 or setting the operation, initial value, etc. of the non-volatile memory device. According to the embodiment of the present invention, a series of operations for generating partial data as internal data or generating internal data as partial data can be performed during the test mode.

3 is a timing chart for explaining a data input method of a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 3, when a 4-bit size partial data is inputted through four data input pins, a series of processes of generating partial data into 2-byte internal data and performing a write operation will be described The control signals and their waveforms are shown.

The nonvolatile memory device (100 of FIG. 2) can use an input / output multiplexing method. That is, the nonvolatile memory device 100 can receive data as well as commands and addresses through the data input / output pins. In order to use the input / output multiplexing scheme, the nonvolatile memory device 100 can determine what is the signal applied to the data input / output pins through the combination of the control signals provided. Illustratively, such control signals may consist of a chip enable signal CE, an instruction latch enable signal CLE, an address latch enable signal ALE, and a write enable signal WE. It will be appreciated that these control signals are merely intended to illustrate embodiments of the present invention and may vary depending on the type of nonvolatile memory device 100.

In the name of the control signals, the symbol "#" means that the signal is activated when it is logic low. The chip enable signal CE # is a control signal for activating the nonvolatile memory device. The command latch enable signal CLE is a control signal for notifying that the signal input through the data input / output pins is a command. The address latch enable signal ALE is a control signal for notifying that the signal input through the data input / output pins is an address. The write enable signal WE # is a control signal for inputting an instruction, address, or data through the data input / output pins.

The write protection signal WP is a control signal for preventing an abnormal operation of the nonvolatile memory device 100, for example, an unintended write or erase operation. According to the embodiment of the present invention, partial data of 4-bit size can be input according to the write protection signal WP that is toggled while the nonvolatile memory device 100 operates in the test mode. As another example, 4-bit size partial data may be input according to the write protection signal WP being toggled while the non-volatile memory device 100 is operating in the normal mode. That is, the write protection signal WP can be used as a control signal for data input in addition to the original control purpose.

The write operation of the nonvolatile memory device 100 is performed while the chip enable signal CE # is activated. When the command latch enable signal CLE and the write enable signal WE # are activated, the first write command W1 is provided to the nonvolatile memory device 100. [ When the address latch enable signal ALE and the write enable signal WE # are activated, an address ADDR indicating an area of the memory cell array 110 in which data is to be stored is provided to the nonvolatile memory device 100.

After the first write command W1 and the address ADDR are provided, data is provided to the nonvolatile memory device 100. [ Four partial data 4b are inputted according to the write protection signal WP which is toggled at least twice while the write enable signal WE # is activated (i.e., during t1 time). For example, the partial data 4b is input when the write protection signal WP transitions from a logic low to a logic high and from a logic high to a logic low. The four partial data 4b are generated as the internal data D1 and D2 of 2-byte size according to the input order. In this way, the partial data 4b to be inputted later is generated as the internal data.

By this operation, substantially the same operation as inputting the 2-byte size data for one period (i.e., t2 time) of the write enable signal WE # can be performed. That is, since data of 2-byte size can be input for one cycle of the write enable signal WE # while using four data input pins, data input throughput can be increased, and the nonvolatile memory device 100 The number of channels required for the control of the channel can be reduced.

The second write command W2 is provided to the nonvolatile memory device 100 when the command latch enable signal CLE and the write enable signal WE # are activated after all data is provided. When the second write command W2 is provided, the generated internal data is substantially programmed into the memory cell array 110, and the write operation is ended.

4 is a timing chart for explaining a data output method of a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 4, control signals and their waveforms for describing a sequence of generating 4-bit-sized partial data from the read internal data and outputting the generated partial data to an external device .

As described above, the nonvolatile memory device (100 in FIG. 2) can use the input / output multiplexing scheme. In using the input / output multiplexing scheme, the read operation of the nonvolatile memory device 100 requires another control signal, unlike the write operation. That is, as a control signal for controlling the read operation of the nonvolatile memory device 100, the chip enable signal CE #, the command latch enable signal CLE, the address latch enable signal ALE, The signal WE # and the read enable signal RE are used.

Since the chip enable signal CE #, the command latch enable signal CLE, the address latch enable signal ALE and the write enable signal WE # have been described in detail in FIG. 3, Is omitted. The read enable signal RE # is a control signal for outputting data read from the memory cell array (110 in FIG. 2) to an external device (11 in FIG. 1).

The write protection signal WP is a control signal for preventing an abnormal operation of the nonvolatile memory device 100, for example, an unintended write or erase operation. According to the embodiment of the present invention, 4-bit size partial data may be output according to the write protection signal WP that is toggled while the non-volatile memory device 100 is operating in the test mode. As another example, 4-bit size partial data may be output according to the write protection signal WP being toggled while the non-volatile memory device 100 is operating in the normal mode. That is, the write protection signal WP can be used as a control signal for data output in addition to the original control purpose.

The write operation of the nonvolatile memory device 100 is performed while the chip enable signal CE # is activated. When the command latch enable signal CLE and the write enable signal WE # are activated, the first read command R1 is provided to the nonvolatile memory device 100. [ When the address latch enable signal ALE and the write enable signal WE # are activated, an address ADDR indicating an area of the memory cell array 110 from which data is to be read is provided to the nonvolatile memory device 100. When the command latch enable signal CLE and the write enable signal WE # are activated, the second read command R 2 is provided to the nonvolatile memory device 100.

After the data is read from the memory cell array 110 to the data input / output block (140 in FIG. 2), operations for outputting the read data to the external device 11 are performed. Bit internal data D1 and D2 in accordance with a write protection signal WP which is toggled at least twice during the time t3 during the activation of the read enable signal RE # And outputs the partial data. For example, the internal data D1 and D2 are generated with four partial data 4b when the write protection signal WP transitions from logic low to logic high and from logic high to logic low . The four partial data 4b are output to the external device through the four data input pins in accordance with the generated order. In this way, the remaining internal data are generated as partial data and output.

By this operation, substantially the same operation as that of outputting 2-byte size data during one period of the read enable signal RE # (i.e., during t4 time) can be performed. In other words, since data of 2-byte size can be output during one period of the read enable signal RE # while using four data output pins, the data output throughput can be increased, and the nonvolatile memory device 100 The number of channels required for the control of the channel can be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. It will be appreciated that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention.

100: Nonvolatile memory device
110: memory cell array
120: row decoder
130: column decoder
140: Data read / write block
150: input / output buffer block
160: control logic

Claims (11)

A method of operating a non-volatile memory device comprising:
The data input / output unit receives or outputs data according to a control signal irrespective of a data input / output operation applied while the write control signal is activated,
Wherein each time a control signal independent of the data input / output operation transitions from a logic low to a logic high and from a logic high to a logic low, the method receives or outputs the data. The method according to claim 1,
Wherein the control signal irrespective of the data input / output operation is a control signal for protecting the nonvolatile memory device from performing a write or erase operation. 3. The method of claim 2,
Wherein the control signal irrelevant to the data input / output operation is used for data input / output control while the nonvolatile memory device operates in a test mode. The method according to claim 1,
Wherein the control signal independent of the data input / output operation transitions from a logic low to a logic high at least twice while the write control signal is active and from a logic high to a logic low. 5. The method of claim 4,
Wherein the 4-bit data is input or output every time a control signal irrelevant to the data input / output operation transitions from a logic low to a logic high and from a logic high to a logic low. Memory cells arranged in an area where bit lines and word lines cross;
Control logic configured to control read, write and erase operations of the memory cells; And
And an input / output buffer block configured to receive data to be stored in the memory cells under the control of the control logic from an external device or to output data read from the memory cells to the external device,
The input / output buffer block includes a nonvolatile memory configured to receive or output data when a control signal irrespective of a data input / output operation applied while the write control signal is activated is changed from a logic low to a logic high and from a logic high to a logic low, Memory device. The method according to claim 6,
Wherein the control signal irrespective of the data input / output operation is a control signal for protecting the nonvolatile memory device from performing a write or erase operation. 8. The method of claim 7,
Wherein the input / output buffer block is configured to receive or output the data according to a control signal that is independent of the data input / output operation in which the write control signal is transitioned at least twice from a logic low to a logic high and from a logic high to a logic low Volatile memory device. 9. The method of claim 8,
Wherein the input / output buffer block is configured to receive or output 4-bit size partial data whenever a control signal irrelevant to the data input / output operation transitions from a logic low to a logic high and from a logic high to a logic low. 10. The method of claim 9,
Wherein the input / output buffer block comprises a partial data storage block configured to buffer the input partial data and generate the buffered partial data into 2-byte internal data. 11. The method of claim 10,
Wherein the partial data storage block is configured to buffer 2-byte sized internal data read from the memory cells and to divide the buffered internal data into the partial data.
KR1020120139023A 2012-12-03 2012-12-03 Nonvolatile memory device and operating method thereof KR20140072367A (en)

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