KR20140071526A - Delay locked loop circuit and operation method for the same - Google Patents

Abstract

Provided is a delay locked loop (DLL) circuit whose operation delay amount is to be effectively used, comprising a first DLL variably delaying a first internal clock corresponding to a first edge of a source clock and outputting a first delay locked clock to make delay locking, a second DLL variably delaying a second internal clock corresponding to a second edge of the source clock and outputting a second delay locked clock to make delay locking, and a clock input multiplexing unit initializing the first DLL in response to activation of an input control signal indicating that the first and second DLLs fail to make delay locking, and subsequently inputting the second delay locking clock, instead of the first internal clock, to the first DLL.

Description

TECHNICAL FIELD [0001] The present invention relates to a delay locked loop circuit and a method of operating the delay locked loop circuit.

The present invention relates to a semiconductor design technology, and more particularly, to a delay locked loop (DLL) circuit. More particularly, the present invention relates to a technique for efficiently using an operation delay amount of a delay locked loop to be.

In general, a delay locked loop (DLL) circuit is used to provide an internal clock whose phase precedes a reference clock obtained by converting an external clock.

That is, since the internal clock used in the semiconductor device is a clock in which the external clock is buffered, immediately after input to the semiconductor device, the external clock and the internal clock have the same phase. However, the internal clock is delayed while operating the internal circuits of the semiconductor device (meaning a clock buffer, a transmission line, etc.), resulting in a phase difference from the external clock. In this way, if the phase difference generated between the internal clock and the external clock is maintained, a normal synchronization operation can not be performed between the semiconductor device and arbitrary devices outside the semiconductor device.

Therefore, the delay locked loop (DLL) circuit compensates in advance the phase difference between the internal clock and the external clock, which is expected to occur due to the internal circuits of the semiconductor device, in the semiconductor device so that the internal clock output to the outside of the semiconductor device becomes an external clock And is used to maintain the synchronization state.

As described above, the delay locked loop (DLL) circuit controls the phase of the internal clock to be ahead of the external clock by a predetermined time in advance in order to compensate the phase difference between the external clock and the internal clock in advance.

Meanwhile, a delay locked loop (DLL) circuit can be generally divided into a delay locked loop (DLL) circuit that operates in a single manner and a delay locked loop (DLL) circuit that operates in a dual mode, have. In this case, a delay locked loop (DLL) circuit that operates as a single has an advantage of occupying a relatively small area as compared with a delay locked loop (DLL) circuit that operates as a dual, And has a disadvantage that the delay fixing operation speed is slow.

1 is a block diagram showing a configuration of a delay locked loop (DLL) circuit operating in a dual mode according to the related art.

Referring to FIG. 1, a delay locked loop (DLL) circuit operating in a dual mode according to the related art includes a clock input buffer 10, a first phase comparing unit 20, a second phase comparing unit 30 The first variable delay line 40, the second variable delay line 50, the first delayed replica model unit 60, the second delayed replica model unit 70, and the clock output multiplexer 80, and a clock output buffer 90.

The clock input buffer 10 buffers the external clock EXT_CLK to generate a source clock REF_CLK.

The first phase comparing unit 20 compares the phase of the source clock REF_CLK with the phase of the first feedback clock FB_CLK1.

The second phase comparing unit 30 compares the phase of the source clock REF_CLK with the phase of the second feedback clock FB_CLK2.

The first variable delay line 40 variably delays the source clock REF_CLK in response to the output signal PD1 of the first phase comparator 20 and outputs it as a first delay locked clock DLL_CLK1.

The second variable delay line 50 variably delays the source clock REF_CLKb whose phase is inverted in response to the output signal PD2 of the second phase comparator 30 and outputs it as a second delay locked clock DLL_CLK2 do.

The first delayed replica modeling unit 60 reflects the delay amount corresponding to the delay path of the source clock REF_CLK to the first delay locked clock DLL_CLK1 and outputs it as the first feedback clock FB_CLK1.

The second delayed replica modeling unit 70 reflects the delay amount corresponding to the delay path of the source clock REF_CLK to the second delay locked clock DLL_CLK2 and outputs it as the second feedback clock FB_CLK2.

The clock output multiplexing unit 80 selects either one of the first delay locked clock DLL_CLK1 and the second delay locked clock DLL_CLK2 according to whether or not the delay locked state has been achieved and outputs the selected clock as the final delay locked clock DLL_CLKF Output.

The clock output buffer 90 buffers the final delay locked clock (DLL_CLKF) and outputs it to the outside of the delay locked loop (DLL) circuit.

The operation of the delay locked loop (DLL) circuit according to the prior art based on the above-described configuration will be described below.

FIG. 2 is a graph illustrating the operation of a delay locked loop (DLL) circuit according to the prior art shown in FIG. 1 and its problem.

2, the maximum delay length adjustable in each of the first variable delay line 40 and the second variable delay line 50 is set to 5 ns, and the first delay replica model portion 60 and the second delay replica line 50 Is a graph showing a state immediately before the delay fixing operation is started in a state where the delay amount corresponding to the delay path of the source clock REF_CLK modeled by the delayed replica modeling unit 70 is set to 4.4 ns. Further, it is a graph in which one period (1 tck) of the source clock REF_CLK is set to '18. 8 ns' to illustrate the maximum value of the adjustable delay amount through the delay fixing operation.

Therefore, the rising edge b of the first feedback clock FB_CLK1 occurs at a time when 4.4 ns from the rising edge a of the source clock REF_CLK has elapsed, and the second feedback clock FB_CLK2 is generated at the rising edge The phase of the clock FB_CLK1 is inverted.

When the delay fixing operation is started in this state, the first feedback comparator 20, the first variable delay line 40, and the first delay replica model unit 60 perform the delay fixing operation, FB_CLK1 is only the time point c corresponding to 9.4 ns based on the first rising edge a of the source clock REF_CLK, It can be seen that the time point up to the rising edge d is insufficient. Therefore, the delay locked operation of the first phase comparing unit 20, the first variable delay line 40, and the first delay replica model unit 60 is in a failed state.

However, the second feedback clock FB_CLK2 has the second phase comparator 30 and the second phase comparator 30 since the rising edge e starts after 9.4 ns from the rising edge b of the first feedback clock FB_CLK1 The maximum amount of delay that the second feedback clock FB_CLK2 can reach through the delay fixing operation of the second variable delay line 50 and the second delay replica model portion 70 is the same as the first rise of the source clock REF_CLK (D) corresponding to 18.8 ns based on the edge (a) and reaches the second rising edge (d) of the source clock REF_CLK exactly. Therefore, the delay locked operation of the second phase comparator 30, the second variable delay line 50, and the second delay replica model unit 70 is in a successful state.

The second delay locked clock DLL_CLK2 generated through the operation of the second phase comparator 30 and the second variable delay line 50 and the second delay replica model unit 70 is converted into a final delay locked clock DLL_CLKF).

However, in the operation of the delay locked loop (DLL) operating in the dual mode according to the related art described above, the first phase comparator 20, the first variable delay line 40 and the first delay replica model 60 There is a problem in that a standby state in which no operation is performed after the delay fixing operation is determined to be failed. That is, in the case where the delay fixing is successful only in the delay fixing operation of the second phase comparator 30, the second variable delay line 50 and the second delay replica model unit 70, the first phase comparator 20 There is a problem that the first variable delay line 40 and the first delay replica model unit 60 operate without any meaning.

An embodiment of the present invention relates to a delay locked loop (DLL) circuit that operates in a dual mode in which a delay amount of a delay fixing operation is efficiently used, Loop (DLL) circuit.

According to an aspect of the present invention, there is provided a delay locked loop circuit comprising: a first delay circuit for delaying a first internal clock corresponding to a first edge of a source clock by a variable delay, Delay locked loop; A second delay locked loop for variably delaying a second internal clock corresponding to a second edge of the source clock to output a second delay locked clock as a second delay fixed clock for achieving delay lock; And initializing the first delay locked loop in response to the activation of an input control signal indicating that the first and second delay locked loops are not both delay locked. And a clock input multiplexer for inputting the second delay locked clock instead of the first internal clock to the first delay locked loop.

According to another aspect of the present invention, there is provided a method for controlling a source clock or a second delay locked clock by varying a source clock or a second delay locked clock according to whether an input control signal is activated, A first delay locked loop for delaying and outputting the first delay locked loop as a first delay locked clock and reflecting the delay path of the source clock to the first delay locked clock to generate the first feedback clock; And a variable delay circuit for variably delaying the phase-inverted source clock to output a delayed path between the source clock and the second feedback clock as the second delay locked clock, A second delay locked loop for generating a second feedback clock; And an operation control section for activating the input control signal in response to both of the first and second delay locked loops reaching a limit delay amount.

According to another aspect of the present invention, there is provided a method of controlling a delay locked loop circuit comprising: a first delay fixing step of variably delaying a source clock to output a first delay locked clock; A second delay fixing step of variably delaying the source clock whose phase has been inverted to output a second delay locked clock as a delay locked state; And when the delay fixing fails in the second delay fixing step following the first delay fixing step, the first delay fixing step is initialized and then the second delay fixing clock is replaced with the first delay fixing clock instead of the source clock And a third delay fixing step of outputting the first delay locked clock by applying the first delay locked loop.

The present invention relates to a delay locked loop (DLL) circuit which operates in a dual mode, wherein when a dual operation consists of first and second delay locked loop operations that operate independently of each other, (DLL) in which the operations of the first and second delay locked loops are successively connected to each other in response to the failure of the operation of the first and second delay locked loops It is possible to greatly increase the amount of the delay amount applicable to the delay fixing operation while minimizing the increase in the area.

1 is a block diagram showing the configuration of a delay locked loop (DLL) circuit operating in a dual mode according to the prior art;
FIG. 2 is a graph illustrating the operation of a delay locked loop (DLL) circuit according to the prior art shown in FIG. 1 and its problem.
3 is a block diagram illustrating a configuration of a delay locked loop (DLL) circuit that operates in a dual manner according to a first embodiment of the present invention.
4 is a block diagram illustrating a configuration of a dual-function delay locked loop (DLL) circuit according to a second embodiment of the present invention;
FIG. 5 is a graph illustrating the operation of a delay locked loop (DLL) circuit according to an embodiment of the present invention shown in FIGS. 3 and 4; FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, Is provided to fully inform the user.

≪ Embodiment 1 >

FIG. 3 is a block diagram showing the configuration of a delay locked loop (DLL) circuit operating in a dual mode according to a first embodiment of the present invention.

Referring to FIG. 3, a dual delay locked loop (DLL) circuit according to the first embodiment of the present invention includes a clock input buffer 310, a first delay locked loop 320, 2 delay locked loop 330, a clock input multiplexer 360, a clock output multiplexer 380, and a clock output buffer 390.

Here, the first delay locked loop 320 includes a first phase comparator 322, a first variable delay line 324, and a first delayed replica model 326.

The second delay locked loop 330 includes a second phase comparator 332, a second variable delay line 334, and a second delay replica model 336.

The clock input multiplexing unit 360 includes an input control signal output unit 362, a reset pulse generation unit 364, and a selection transfer unit 366.

The first delay locked loop 320 variably delays and outputs the source clock REF_CLK corresponding to the first edge of the source clock REF_CLK as a first delay locked clock DLL_CLK1 to achieve delay lock.

The first delay locked loop 320 performs an operation for achieving the delay locked state when the first delay locked loop DLL_CLK1 output from the first delay locked loop 320 has a delay path of the source clock REF_CLK, The delay amount corresponding to the delay time is reflected.

The first edge of the source clock REF_CLK may also mean the rising edge of the source clock REF_CLK and the falling edge of the source clock REF_CLK. That is, the source clock REF_CLK corresponding to the first edge of the source clock REF_CLK becomes the same clock as the source clock REF_CLK, and the rising edge of the source clock REF_CLK corresponds to the rising edge of the source clock REF_CLK Or a form in which the rising edge of the source clock REF_CLK corresponds to the falling edge of the source clock REF_CLK with a phase inverted in the phase of the source clock REF_CLK.

Note that, in the figure, the first edge of the source clock REF_CLK indicates the rising edge of the source clock REF_CLK, and the source clock REF_CLK and the source clock REF_CLK become the same clock. In this manner, when the source clock REF_CLK and the source clock REF_CLK become the same clock, the first delay locked loop 320 performs the delay locked operation based on the rising edge of the source clock REF_CLK. That is, the first delay locked loop 320 performs a delay locked operation to synchronize the rising edge of the first feedback clock FB_CLK1 with respect to the rising edge of the source clock REF_CLK.

Specifically, the first phase comparator 322 among the components of the first delay locked loop 320 compares the phase of the source clock REF_CLK with the phase of the first feedback clock FB_CLK1. That is, whether the phase of the rising edge of the first feedback clock FB_CLK1 is earlier or later than the rising edge of the source clock REF_CLK is determined to determine the logic level of the output signal PD1. For example, when the output signal PD1 of the first phase comparator 322 is logic 'high', the rising edge of the source clock REF_CLK has a phase higher than the rising edge of the first feedback clock FB_CLK1 And that the rise edge of the source clock REF_CLK has a phase that is later than the rising edge of the first feedback clock FB_CLK1 in the case of logic "low" (Low).

The first variable delay line 324 among the constituent elements of the first delay locked loop 320 receives the source clock REF_CLK by a delay amount corresponding to the output signal PD1 of the first phase comparator 322 The reset pulse generator (360) included in the clock input multiplexer (360) activates the first fixed failure signal (DLY_END1) in response to reaching the limit delay amount, The delay amount is initialized in response to the reset pulse RESETP output from the delay circuit 364. That is, the first variable delay line 324 increases or decreases the internal delay amount according to the logic level of the signal PD1 output from the first phase comparator 322, and outputs the source clock REF_CLK And outputs it as a first delay locked clock (DLL_CLK1). Since the total delay amount of the first variable delay line 324 is a predetermined portion at the time of designing, if the internal delay amount is continuously increased according to the signal PD1 output from the first phase comparator 322, It is possible to reach a limit delay amount that can not increase the delay amount. In this manner, when the limit delay amount is reached, the operation is performed to activate the first fixing failure signal DLY_END1. In addition, the internal delay amount can be initialized in response to the toggling of the reset pulse RESETP generated in the reset pulse generating unit 364, which will be described later, And initializing the internal delay amount to '0'.

The first delayed replica modeling unit 326 of the elements of the first delay locked loop 320 reflects the delay amount corresponding to the delay path of the source clock REF_CLK in the first delay locked clock DLL_CLK1 And outputs it as the first feedback clock FB_CLK1. That is, the delay amount corresponding to the delay path of the source clock (REF_CLK) is preliminarily modeled in the first delay replica modeling unit 326, and the delayed first delay locked clock DLL_CLK1 is delayed as the first feedback clock FB_CLK1 Output.

The second delay locked loop 330 variably delays the source clock REF_CLKb in which the phase corresponding to the second edge of the source clock REF_CLK is inverted to achieve the delay locked state and outputs it as the second delay locked clock DLL_CLK2 do.

The operation of the second delay locked loop 330 to perform the delay locked operation means that the second delay locked loop DLL_CLK2 output from the second delay locked loop 330 is delayed by a delay path of the source clock REF_CLK, The delay amount corresponding to the delay time is reflected.

Further, the second edge of the source clock REF_CLK may mean a falling edge of the source clock REF_CLK and may mean a rising edge of the source clock REF_CLK. However, it is a concept opposite to the first edge of the source clock REF_CLK. That is, when the first edge of the source clock REF_CLK indicates the rising edge of the source clock REF_CLK, the second edge of the source clock REF_CLK indicates the falling edge of the source clock REF_CLK, The second edge of the source clock REF_CLK means the rising edge of the source clock REF_CLK when the first edge of the source clock REF_CLK indicates the falling edge of the source clock REF_CLK. Thus, in the first delay locked loop 320, when the source clock REF_CLK becomes the same clock as the source clock REF_CLK, the phase-inverted source clock REF_CLKb is a clock obtained by inverting the phase of the source clock REF_CLK And the source clock REF_CLK becomes a clock obtained by inverting the phase of the source clock REF_CLK, the source clock REF_CLKb whose phase is inverted becomes the same clock as the source clock REF_CLK.

For reference, the figure illustrates the case where the second edge of the source clock REF_CLK indicates the falling edge of the source clock REF_CLK, and a clock which inverts the phase of the source clock REF_CLK and a source clock REF_CLKb) become the same clock. In this manner, when the source clock REF_CLKb in which the clock phase inverted from the phase of the source clock REF_CLK is inverted becomes the same clock, the second delay locked loop 330 delays based on the rising edge of the source clock REF_CLK Thereby performing a fixed operation. That is, the second delay locked loop 330 performs a delay locked operation to synchronize the rising edge of the second feedback clock FB_CLK2 with respect to the rising edge of the source clock REF_CLK.

The second phase comparator 332 among the components of the second delay locked loop 330 compares the phases of the source clock REF_CLK and the second feedback clock FB_CLK2. That is, whether the phase of the rising edge of the second feedback clock FB_CLK2 is ahead or behind is determined based on the rising edge of the source clock REF_CLK to determine the logic level of the output signal PD2. For example, when the output signal PD2 of the second phase comparator 332 is logic 'high', the rising edge of the source clock REF_CLK has a phase higher than the rising edge of the second feedback clock FB_CLK2 And when the logic low is Low, the rising edge of the source clock REF_CLK has a phase after the rising edge of the second feedback clock FB_CLK2.

The second variable delay line 334 among the constituent elements of the second delay locked loop 330 is connected to a source clock signal whose phase is inverted by a delay amount corresponding to the output signal PD2 of the second phase comparator 332, (REF_CLKb) as the second delay locked clock (DLL_CLK2), and activates the second fixed failure signal (DLY_END2) in response to reaching the limit delay amount. In other words, the second variable delay line 334 is connected to the source of the inverted phase of the source clock signal CLK through the operation of increasing or decreasing the internal delay amount according to the logic level of the signal PD2 output from the second phase comparator 332. [ (REF_CLKb) and outputs it as a second delay locked clock (DLL_CLK2). Since the total delay amount of the second variable delay line 334 is a predetermined portion at the time of designing, if the internal delay amount is continuously increased according to the signal PD2 outputted from the second phase comparator 332, It is possible to reach a limit delay amount in which the abnormal delay amount can not be increased. In this manner, when the limit delay amount is reached, the operation is performed to activate the second fixed failure signal DLY_END2.

The second delay copy model unit 336 of the second delay locked loop 330 reflects the delay amount corresponding to the delay path of the source clock REF_CLK in the second delay locked clock DLL_CLK2 And outputs it as the second feedback clock FB_CLK2. That is, the delay amount corresponding to the delay path of the source clock (REF_CLK) is preliminarily modeled in the second delay replica model unit 336 and the second delay locked clock (DLL_CLK2) is delayed as the second feedback clock FB_CLK2 Output.

The clock input multiplexing unit 360 activates the input control signal IN_SEL indicating that the first delay locked loop 320 and the second delay locked loop 330 can not perform the delay locking, Initialize the first delay locked loop 320 in response to the IN_SEL being activated. Then, a second delay locked clock (DLL_CLK2) is input to the first delay locked loop 320 instead of the first internal clock IN_CLK. That is, the clock input multiplexer 360 multiplies the first fixed failure signal DLY_END1 and the second variable delay line 334, which are activated when the first variable delay line 324 reaches the limit delay amount, Activates the input control signal IN_SEL and at the same time toggles the reset pulse RESETP to initialize the first variable delay line 324 when both the second fixed failure signal DLY_END2 activated when the second fixed delay line 324 is activated, The first variable delay line 324 and the second variable delay line 334 are simultaneously applied to the first variable delay line 324 and the second variable delay line 334, Delay line 324. [ Accordingly, a first delay locked loop (DLL) including the first variable delay line 324 is connected to the first feedback clock (FB_CLK1) and the source clock (REF_CLK), which are generated from the second delay locked clock (DLL_CLK2) So that the delay locked state can be achieved.

Specifically, the input control signal output unit 362 of the clock input multiplex unit 360 receives the first fixed failure signal DLY_END1 indicating that the first delay locked loop 320 can not perform the delay locked state, 2 activates the input control signal IN_SEL in response to both the second fixed failure signal DLY_END2 indicating that the second fixed locking loop 330 fails to perform the delay locking.

The reset pulse generator 364 among the components of the clock input multiplexer 360 generates a reset pulse RESETP that toggles for a set time in response to the activation of the input control signal IN_SEL.

The first fixed failure signal DLY_END1 activated when the variable delay amount of the first variable delay line 324 among the components of the first delay locked loop 320 reaches the limit is input to the clock input multiplexer 360 May be configured to be inactivated when the first variable delay line 324 is initialized in response to the toggling of the reset pulse RESETP output from the reset pulse generator 364, In this type of configuration, the activation state of the input control signal IN_SEL must be maintained as it is, even if the activated first fixation failure signal DLY_END1 is deactivated in response to the toggling of the reset pulse RESETP, so that the input control signal IN_SEL The input control signal output unit 362 may be further complicated. On the other hand, in response to the fact that the variable delay amount of the first variable delay line 324 again reaches the limit in a state where the input control signal IN_SEL is activated, the final fixed failure signal DLY_ENDF) - not shown directly in the figure. That is, the delay locked loop (DLL) circuit is more complicated - it occupies a larger area. However, since there is a fixed failure judgment part, the final delay locked operation failure of the delay locked loop (DLL) .

Of course, the first fixing failure signal DLY_END1 may be kept active regardless of the toggling of the reset pulse RESETP. In this configuration, the configuration of the input control signal output unit 362 for determining whether to activate the input control signal IN_SEL can be configured very simply. For example, the input control signal output unit 362 may be configured through a configuration of a NAND gate and an inverter for receiving a first fixed failure signal DLY_END1 and a second fixed failure signal DLY_END2 to perform an AND operation. On the other hand, since there is no way to detect that the variable delay amount of the first variable delay line 324 again reaches the limit under the condition that the input control signal IN_SEL is activated, the final There is a disadvantage that it is not possible to quickly catch the delay fixing operation failure, but there is an advantage that the configuration of the delay locked loop (DLL) circuit is very simple.

The selection transfer unit 366 among the components of the clock input multiplexer 360 selects the source clock REF_CLK in a period in which the input control signal IN_SEL is inactive and transfers the selected source clock REF_CLK to the first delay locked loop 320 And selects and transmits the second delay locked clock (DLL_CLK2) to the first delay locked loop 320 in the active period. That is, in the state where neither the first variable delay line 324 nor the second variable delay line 334 reaches the limit delay amount, the selection transfer section 366 selects the source clock REF_CLK To be used for the delay locked operation of the first delay locked loop 320. However, in a state where the first variable delay line 324 and the second variable delay line 334 both reach the limit delay amount, the second delay locked clock DLL_CLK2 is selected and the first delay locked loop 320). ≪ / RTI >

The clock output multiplexer 380 outputs the first delay locked clock DLL_CLK1 as a final delay locked clock in response to the delay locked state in the operation of the first delay locked loop 320, And outputs the second delay locked clock DLL_CLK2 as the final delay locked clock DLL_CLKF in response to the delay locked state in the operation of the fixed loop 330. [ For reference, signals for detecting that delay locking is performed in the operation of the first delay locked loop 320 or the second delay locked loop 330 are not directly shown in the drawing. However, in the actual circuit configuration, it may be considered that signals for detecting that delay locking is performed in the operation of the first delay locked loop 320 or the second delay locked loop 330 are included, This is a matter of course in the configuration of a loop (DLL) circuit, so we will not discuss it in more detail here.

In the delay locked loop (DLL) circuit operating in a dual manner according to the first embodiment of the present invention described above, both of the first variable delay line 324 and the second variable delay line 334 are delayed The second delay locked clock DLL_CLK2 is provided to the first delay locked loop 320 instead of the source clock REF_CLK. That is, when the first variable delay line 324 and the second variable delay line 334, which are opposite to each other, reach the limit delay amount, the first delay locked clock DLL_CLK1 is inverted to the phase of the source clock REF_CLKb, But is provided to the second delay locked loop 330 instead.

When the total delay amount of the first variable delay line 324 and the total delay amount of the second variable delay line 334 are equal to each other, The phase at the time point at which the limit delay amount reaches the limit delay amount on the line 324 reaches the limit delay amount of the second variable delay line 334 is in the advanced state.

For example, when the reference time point of the delay locked operation is the rising edge of the source clock REF_CLK, the first delay locked loop 320 receives the source clock REF_CLK corresponding to the rising edge of the source clock REF_CLK, The second delay locked loop 330 receives the source clock REF_CLKb whose phase is inverted corresponding to the falling edge of the source clock REF_CLK, 324 and the second variable delay line 334 reach the limit delays, the phase of the second delay locked clock DLL_CLK2 must be behind the first delay locked clock DLL_CLK1.

Likewise, when the reference time point of the delay fixing operation is the falling edge of the source clock REF_CLK, the first delay locked loop 320 receives the source clock REF_CLK corresponding to the falling edge of the source clock REF_CLK, And the second delay locked loop 330 receives the source clock REF_CLKb whose phase is inverted corresponding to the rising edge of the source clock REF_CLK, 324 and the second variable delay line 334 reach the limit delays, the phase of the second delay locked clock DLL_CLK2 must be behind the first delay locked clock DLL_CLK1.

≪ Embodiment 2 >

FIG. 4 is a block diagram showing a configuration of a dual-function delay locked loop (DLL) circuit according to a second embodiment of the present invention.

Referring to FIG. 4, a dual delay locked loop (DLL) circuit according to a second embodiment of the present invention includes a clock input buffer 410, a first delay locked loop 420, A delay locked loop 430, an operation control unit 460, a clock output multiplexing unit 480, and a clock output buffer 490.

Here, the first delay locked loop 420 includes a first phase comparator 422, a selection transfer section 428, a first variable delay line 424, and a first delay replica model section 426 .

The second delay locked loop 430 includes a second phase comparator 432, a second variable delay line 434, and a second delay replica model 436.

The operation control unit 460 includes an input control signal output unit 462 and a reset pulse generation unit 464. [

The first delay locked loop 420 is controlled by a source clock REF_CLK or a second delay locked state based on the activation of the input control signal IN_SEL to establish a delay lock between the source clock REF_CLK and the first feedback clock FB_CLK1. And outputs the first delay locked clock DLL_CLK1 as a first delay locked clock DLL_CLK1 while reflecting the delay path of the source clock REF_CLK to the first delay locked clock DLL_CLK1 as a first feedback clock FB_CLK1 .

Here, the fact that the delay lock is established between the source clock REF_CLK and the first feedback clock FB_CLK1 means that the phases of the rising edge of the source clock REF_CLK and the rising edge of the first feedback clock FB_CLK1 are synchronized Operation and may mean to perform a delay locking operation so that the phases of the falling edge of the source clock REF_CLK and the falling edge of the first feedback clock FB_CLK1 are synchronized. This is the part that can be changed by the designer's choice.

For reference, the figure shows a case where the delay fixing operation is performed such that the rising edge of the source clock REF_CLK and the rising edge of the first feedback clock FB_CLK1 are synchronized. That is, the first delay locked loop 420 performs a delay locked operation to synchronize the rising edge of the first feedback clock FB_CLK1 with respect to the rising edge of the source clock REF_CLK.

Specifically, the first phase comparator 422 among the components of the first delay locked loop 420 compares the phases of the source clock REF_CLK and the first feedback clock FB_CLK1. That is, whether the phase of the rising edge of the first feedback clock FB_CLK1 is earlier or later than the rising edge of the source clock REF_CLK is determined to determine the logic level of the output signal PD1. For example, when the output signal PD1 of the first phase comparing unit 422 is logic 'high', the rising edge of the source clock REF_CLK has a phase higher than the rising edge of the first feedback clock FB_CLK1 And that the rise edge of the source clock REF_CLK has a phase that is later than the rising edge of the first feedback clock FB_CLK1 in the case of logic "low" (Low).

The selection transfer unit 428 of the first delay locked loop 420 selects the source clock REF_CLK in a period in which the input control signal IN_SEL is inactivated and outputs the selected source clock REF_CLK to the first variable delay line 424 And selects and transmits the second delay locked clock DLL_CLK2 to the first variable delay line 424 in the active period. That is, in the state where neither the first variable delay line 424 nor the second variable delay line 434 reaches the limit delay amount, the selection transfer section 428 selects the source clock REF_CLK To be used for the delay locked operation of the first delay locked loop 420. However, in a state where the first variable delay line 424 and the second variable delay line 434 both reach the limit delay amount, a second delay locked clock DLL_CLK2 is selected and a first delay locked loop 420). ≪ / RTI >

The first variable delay line 424 among the components of the first delay locked loop 420 receives the source clock REF_CLK by a delay amount corresponding to the output signal PD1 of the first phase comparator 422 The reset pulse generator 464 included in the operation controller 460 activates the first fixed failure signal DLY_END1 in response to reaching the limit delay amount and outputs the reset pulse as the first delay locked clock DLL_CLK1, The delay amount is initialized in response to the reset pulse RESETP output from the reset pulse generating circuit. That is, the first variable delay line 424 increases or decreases the internal delay amount according to the logic level of the signal PD1 output from the first phase comparing unit 422, thereby reducing the source clock REF_CLK And outputs it as a first delay locked clock (DLL_CLK1). Since the total delay amount of the first variable delay line 424 is a predetermined portion at the time of designing, if the internal delay amount is continuously increased according to the signal PD1 output from the first phase comparator 422, It is possible to reach a limit delay amount that can not increase the delay amount. In this manner, when the limit delay amount is reached, the operation is performed to activate the first fixing failure signal DLY_END1. In addition, the internal delay amount can be initialized in response to the toggling of the reset pulse RESETP generated in the reset pulse generating unit 464, which will be described later, And initializing the internal delay amount to '0'.

The first delayed replica model unit 426 among the components of the first delay locked loop 420 reflects the delay amount corresponding to the delay path of the source clock REF_CLK to the first delay locked clock DLL_CLK1 And outputs it as the first feedback clock FB_CLK1. That is, the delay amount corresponding to the delay path of the source clock (REF_CLK) is preliminarily modeled in the first delayed replica model unit 426, and the delayed first delay locked clock DLL_CLK1 is delayed as the first feedback clock FB_CLK1 Output.

The second delay locked loop 430 variably delays the phase-inverted source clock REF_CLKb to achieve a delay lock between the source clock REF_CLK and the second feedback clock FB_CLK2 to generate a second delay locked clock DLL_CLK2, And generates a second feedback clock FB_CLK2 by reflecting the delay path of the source clock REF_CLK to the second delay locked clock DLL_CLK2.

Here, the fact that the delay lock is established between the source clock REF_CLK and the second feedback clock FB_CLK2 means that the phases of the rising edge of the source clock REF_CLK and the rising edge of the second feedback clock FB_CLK2 are synchronized with each other, Operation and may mean to perform a delay locked operation so that the phases of the falling edge of the source clock REF_CLK and the falling edge of the second feedback clock FB_CLK2 are synchronized. This is the part that can be changed by the designer's choice. However, when the delay locked operation is performed such that the rising edge of the source clock REF_CLK and the rising edge of the first feedback clock FB_CLK1 are synchronized in the first delay locked loop 420, the second delay locked loop 430 Also performs a delay locking operation so that the rising edge of the source clock REF_CLK and the rising edge of the second feedback clock FB_CLK2 are synchronized in phase. Similarly, when performing the delay locked operation so that the phases of the falling edge of the source clock REF_CLK and the falling edge of the first feedback clock FB_CLK1 are synchronized in the first delay locked loop 420, the second delay locked loop 430 Performs a delay locking operation so that the phases of the falling edge of the source clock REF_CLK and the falling edge of the second feedback clock FB_CLK2 are synchronized.

For reference, the figure shows a case where the delay fixing operation is performed so that the rising edge of the source clock REF_CLK and the rising edge of the second feedback clock FB_CLK2 are synchronized. That is, the second delay locked loop 430 performs the delay locked operation to synchronize the rising edge of the second feedback clock FB_CLK2 with respect to the rising edge of the source clock REF_CLK.

The second phase comparator 432 of the components of the second delay locked loop 430 compares the phases of the source clock REF_CLK and the second feedback clock FB_CLK2. That is, whether the phase of the rising edge of the second feedback clock FB_CLK2 is ahead or behind is determined based on the rising edge of the source clock REF_CLK to determine the logic level of the output signal PD2. For example, when the output signal PD2 of the second phase comparing unit 432 is logic 'high', the rising edge of the source clock REF_CLK has a phase higher than the rising edge of the second feedback clock FB_CLK2 And when the logic low is Low, the rising edge of the source clock REF_CLK has a phase after the rising edge of the second feedback clock FB_CLK2.

The second variable delay line 434 among the components of the second delay locked loop 430 is connected to a source clock signal whose phase is inverted by a delay amount corresponding to the output signal PD2 of the second phase comparing unit 432, (REF_CLKb) as the second delay locked clock (DLL_CLK2), and activates the second fixed failure signal (DLY_END2) in response to reaching the limit delay amount. That is, the second variable delay line 434 increases or decreases the internal delay amount according to the logic level of the signal PD2 output from the second phase comparing unit 432, (REF_CLKb) and outputs it as a second delay locked clock (DLL_CLK2). Since the total delay amount of the second variable delay line 434 is a predetermined portion at the time of designing, if the internal delay amount is continuously increased according to the signal PD2 outputted from the second phase comparator 432, It is possible to reach a limit delay amount in which the abnormal delay amount can not be increased. In this manner, when the limit delay amount is reached, the operation is performed to activate the second fixed failure signal DLY_END2.

The second delay replica model unit 436 of the second delay locked loop model 430 reflects the delay amount corresponding to the delay path of the source clock REF_CLK to the second delay locked clock DLL_CLK2 And outputs it as the second feedback clock FB_CLK2. That is, the delay amount corresponding to the delay path of the source clock (REF_CLK) is preliminarily modeled in the second delay replica model unit 436, and the second delay fixed clock DLL_CLK2 is delayed as the second feedback clock FB_CLK2 Output.

The operation control unit 460 activates the input control signal IN_SEL indicating that the first delay locked loop 420 and the second delay locked loop 430 can not perform the delay locking operation, Initializes the first delay locked loop 420 in response to activation of the first delay locked loop 420. That is, when the first fixed failure signal DLY_END1 and the second variable delay line 434, which are activated when the first variable delay line 424 reaches the limit delay amount, reach the limit delay amount Activates the input control signal IN_SEL and at the same time toggles the reset pulse RESETP to initialize the first variable delay line 424 when both the second fixed failure signal DLY_END2 activated when the first fixed delay line DLY_END2 is activated. Therefore, in the first delay locked loop (DLL) including the first variable delay line 424, the phase of the first feedback clock FB_CLK1 and the source clock REF_CLK generated with the second delay locked clock DLL_CLK2 as a start point So that the delay locked state can be achieved.

The input control signal output unit 462 of the operation control unit 460 outputs the first fixed failure signal DLY_END1 indicating that the first delay locked loop 420 fails to perform the delay locked state, And activates the input control signal IN_SEL in response to both the second fixed failure signal DLY_END2 indicating that the fixed loop 430 does not achieve the delay locking.

The reset pulse generator 464 of the operation control unit 460 generates a reset pulse RESETP that toggles for a set time in response to the activation of the input control signal IN_SEL.

At this time, the first fixed failure signal DLY_END1, which is activated when the variable delay amount of the first variable delay line 424 among the components of the first delay locked loop 420 reaches the limit, And may be configured such that it is inactivated when the first variable delay line 424 is initialized in response to the toggling of the reset pulse RESETP output from the reset pulse generator 464 among the components. In this type of configuration, the activation state of the input control signal IN_SEL must be maintained as it is, even if the activated first fixation failure signal DLY_END1 is deactivated in response to the toggling of the reset pulse RESETP, so that the input control signal IN_SEL The input control signal output unit 462 may be further complicated. On the other hand, in response to the fact that the variable delay amount of the first variable delay line 424 again reaches the limit in a state in which the input control signal IN_SEL is activated, the final fixed failure signal DLY_ENDF) - not shown directly in the figure. That is, the delay locked loop (DLL) circuit is more complicated - it occupies a larger area. However, since there is a fixed failure judgment part, the final delay locked operation failure of the delay locked loop (DLL) .

Of course, the first fixing failure signal DLY_END1 may be kept active regardless of the toggling of the reset pulse RESETP. In this configuration, the configuration of the input control signal output unit 462 for determining whether or not the input control signal IN_SEL is activated can be configured very simply. For example, the input control signal output unit 462 may be configured through a configuration of a NAND gate and an inverter for receiving the first fixing failure signal DLY_END1 and the second fixing failure signal DLY_END2 and performing an AND operation. On the other hand, since there is no way to detect that the amount of variable delay of the first variable delay line 424 again reaches the limit while the input control signal IN_SEL is active, the final There is a disadvantage that it is not possible to quickly catch the delay fixing operation failure, but there is an advantage that the configuration of the delay locked loop (DLL) circuit is very simple.

The clock output multiplexer 480 outputs the first delay locked clock DLL_CLK1 as the final delay locked clock in response to the delay locked state in the operation of the first delay locked loop 420, And outputs the second delay locked clock DLL_CLK2 as the final delay locked clock DLL_CLKF in response to the delay locked state in the operation of the fixed loop 430. [ For reference, signals for detecting that delay locking is performed in the operation of the first delay locked loop 420 or the second delay locked loop 430 are not directly shown in the drawing. However, in the actual circuit configuration, signals for detecting that the delay locked state is established during the operation of the first delay locked loop 420 or the second delay locked loop 430 may be included, This is a matter of course in the configuration of a loop (DLL) circuit, so we will not discuss it in more detail here.

In the delay locked loop (DLL) circuit operating in a dual manner according to the second embodiment of the present invention described above, both the first variable delay line 424 and the second variable delay line 434 are delayed The second delay locked clock DLL_CLK2 is provided to the first variable delay line 424 instead of the source clock REF_CLK. That is, when the first variable delay line 424 and the second variable delay line 434, which are opposite to each other, reach the limit delay amount, the first delay locked clock DLL_CLK1 is inverted in phase with the source clock REF_CLKb, And the second variable delay line 434 is provided instead of the second variable delay line 434.

If it is assumed that the total delay amount of the first variable delay line 424 and the total delay amount of the second variable delay line 434 are equal to each other, The phase at the time point when the limit delay amount reaches the limit delay amount on the line 424 reaches the limit delay amount of the second variable delay line 434 is in the advanced state.

For example, when the reference time point of the delay locked operation is the rising edge of the source clock REF_CLK, the first delay locked loop 420 receives the source clock REF_CLK corresponding to the rising edge of the source clock REF_CLK, The second delay locked loop 430 receives the source clock REF_CLKb whose phase is inverted corresponding to the falling edge of the source clock REF_CLK, The second delay locked clock DLL_CLK2 must be behind the first delay locked clock DLL_CLK1 at the time when both of the first variable delay line 424 and the second variable delay line 434 reach the limit delay amount.

Likewise, when the reference time point of the delay fixing operation is the falling edge of the source clock REF_CLK, the first delay locked loop 420 receives the source clock REF_CLK corresponding to the falling edge of the source clock REF_CLK, The second delay locked loop 430 receives the source clock REF_CLKb whose phase is inverted corresponding to the rising edge of the source clock REF_CLK, The second delay locked clock DLL_CLK2 must be behind the first delay locked clock DLL_CLK1 at the time when both of the first variable delay line 424 and the second variable delay line 434 reach the limit delay amount.

FIG. 5 is a graph illustrating the operation of a delay locked loop (DLL) circuit according to an embodiment of the present invention shown in FIG. 3 and FIG.

5, the maximum delay length adjustable in the first variable delay lines 324 and 424 and the second variable delay lines 334 and 434 is set to '5 ns', and the first delayed replica model unit 326 And the delay amount corresponding to the delay path of the source clock REF_CLK modeled by the second delay replica model units 336 and 436 is set to 4.4 ns. Fig. Further, it is a graph in which one period (1 tck) of the source clock REF_CLK is set to '28.8 ns' to illustrate the maximum value of the adjustable delay amount through the delay fixing operation.

Therefore, the rising edge b of the first feedback clock FB_CLK1 occurs at a time when 4.4 ns from the rising edge a of the source clock REF_CLK has elapsed, and the second feedback clock FB_CLK2 is generated at the rising edge The phase of the clock FB_CLK1 is inverted.

When the delay fixing operation is started in this state, the maximum amount of delay that the first feedback clock FB_CLK1 can reach through the delay fixing operation of the first delay locked loop 320 or 420 is the source clock REF_CLK, (C) corresponding to '9.4 ns' based on the first rising edge (a) of the source clock (REF_CLK). Therefore, it is found that the time until the next rising edge (d) of the source clock REF_CLK becomes insufficient. Therefore, the delay locked operation of the first delay locked loop 320, 420 becomes a failed state.

The second feedback clock FB_CLK2 is also supplied to the second delay locked loop 330, 430 (although the rising edge e is started at the time when 18.8 ns has elapsed from the rising edge b of the first feedback clock FB_CLK1) The maximum amount of delay that the second feedback clock FB_CLK2 can reach through the delay fixing operation of the source clock REF_CLK is equal to the time e at which the first rising edge a of the source clock REF_CLK corresponds to 23.8 ns ), It is found that the time point until the second rising edge d of the source clock REF_CLK becomes insufficient. Therefore, the delay locked operation of the second delay locked loop (330, 430) is in a failed state.

In this way, at the time when the delay fixing operation of the first delay locked loop 320, 420 and the second delay locked loop 420, 430 fail, the first delay locked loop 320, 420 outputs the source clock REF_CLK, The second delay locked clock DLL_CLK2 is applied instead of the first internal clock IN_CLK1 and the delay locked operation is continued. That is, from the time point of '23.8 ns' based on the first rising edge a of the source clock REF_CLK at which the delay fixing operation of the second delay locked loop 330 or 430 fails, the first delay locked loop 320 , 420 are again performed. Therefore, the maximum amount of delay that the first feedback clock FB_CLK1 can reach through the delay fixing operation of the first delay locked loops 320 and 420 is' 28.8 ns' and reaches the second rising edge (d) of the source clock REF_CLK exactly. Therefore, the delay fixing operation of the first delay locked loop 320, 420 is changed from a failed state to a successful state.

The delay fixing operation of the first delay locked loops 320 and 420 and the delay fixing operation of the second delay locked loops 330 and 430 are repeated again And outputs the generated first delay locked clock DLL_CLK1 as a final delay locked clock DLL_CLKF.

In this way, according to the embodiment of the present invention, in the dual fixed delay locked loop (DLL) circuit, the delay locked operation of the first delay locked loops 320 and 420 and the second delay locked loops 330 and 430 It is possible to greatly increase the amount of variable delay that can be used for the delay locked operation by extending the delay locked operation using the first delay locked loop 320, .

That is, in a delay locked loop (DLL) circuit operating in a dual mode according to an embodiment of the present invention, when starting the delay locked operation, the dual locked loop operates normally, And the second delay locked loops 330 and 430 perform delay locked operation independently of each other, so that a fast delay locked operation can be performed. When the first and second delay locked loops 320 and 420 and the second delay locked loops 330 and 430 fail to perform the delay locked operation, the operation result of the second delay locked loop 330 and 430 becomes the first delay The first and second delay locked loops 320 and 420 and the second delay locked loop 330 and 430 are continuously connected to each other to apply a single delay locked loop (DLL). Therefore, it is possible to greatly increase the amount of the delay amount applicable to the delay fixing operation, while the area of the delay locked loop (DLL) hardly increases - only the area occupied by some control circuits increases.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art.

10, 310, 410: clock input buffer
320, 420: first delay locked loop
330, 430: second delay locked loop
380, 480: clock output multiplexing unit 390, 490: clock output buffer
20, 322, 332:
30, 332 and 432:
40, 324, 424: a first variable delay line
50, 334, 434: a second variable delay line
60, 326, and 426:
70, 336, 436: the second delayed replica model unit
360: Clock input multiplexing unit 460: Operation control unit
362, 462: Input control signal output units 364, 464:
366, 428:

Claims (20)

A first delay locked loop for variably delaying a first internal clock corresponding to a first edge of a source clock to output a first internal fixed clock as a first delay fixed clock for achieving delay fixing;
A second delay locked loop for variably delaying a second internal clock corresponding to a second edge of the source clock to output a second delay locked clock as a second delay fixed clock for achieving delay lock; And
After initializing the first delay locked loop in response to the activation of an input control signal indicating that both the first and second delay locked loops do not achieve delay locked. A clock input multiplexer for inputting the second delay locked clock instead of the first internal clock to the first delay locked loop,
And a delay locked loop circuit.
The method according to claim 1,
Wherein the clock input multiplexer comprises:
In response to both a first fixed failure signal indicating that the first delay locked loop is not delay locked and a second fixed failure signal indicating that the second delay locked loop is not delay locked, An input control signal output unit for activating an input signal;
A reset pulse generating unit for generating a reset pulse toggling for a set time in response to the activation of the input control signal; And
Selecting the first internal clock in an interval in which the input control signal is inactive and transferring the selected first internal clock to the first delay locked loop, selecting the second delay locked clock in the active interval, and transmitting the selected second delay locked clock to the first delay locked loop A delay lock loop circuit comprising a transfer section.
3. The method of claim 2,
The first delay locked loop includes:
A first phase comparator for comparing a phase of the source clock with a phase of a first feedback clock;
The first internal clock is delayed by a delay amount corresponding to the output signal of the first phase comparison unit and is output as the first delay locked clock, and the first fixed failure signal is activated in response to reaching the limit delay amount A first variable delay line whose delay amount is initialized in response to the reset pulse; And
And a first delay replica model unit for reflecting the delay amount corresponding to the delay path of the source clock to the first delay locked clock and outputting it as the first feedback clock.
The method of claim 3,
The second delay locked loop comprising:
A second phase comparison unit for comparing phases of the source clock and the second feedback clock;
And outputs the second internal clock as the second delay locked clock by a delay amount corresponding to the output signal of the second phase comparing unit and activates the second fixed failure signal in response to reaching the limit delay amount A second variable delay line; And
And a second delay replica model unit for reflecting the delay amount corresponding to the delay path of the source clock to the second delay locked clock and outputting it as the second feedback clock.
5. The method of claim 4,
Wherein the first fixed failure signal is activated in response to the first variable delay line reaching a threshold delay amount and is deactivated in response to the toggling of the reset pulse,
And a fixed failure determination unit for activating a final fixed failure signal in response to activation of the first fixed failure signal in an active period of the input control signal.
The method according to claim 1,
And outputting the first delay locked clock as a final delay locked clock in response to the delay locked in the operation of the first delay locked loop, And a clock output multiplexer for outputting the second delay locked clock as the final delay locked clock.
The method of claim 3,
The rising edge of the first internal clock is synchronized to the rising edge of the source clock, the rising edge of the second internal clock is synchronized to the falling edge of the source clock,
Wherein a delay fixing operation is performed to synchronize rising edges of the first and second feedback clocks with reference to rising edges of the source clocks.
The method of claim 3,
The rising edge of the first internal clock is synchronized to the falling edge of the source clock, the rising edge of the second internal clock is synchronized to the rising edge of the source clock,
And a delay fixing operation is performed to synchronize rising edges of the first and second feedback clocks based on a falling edge of the source clock.
And outputs a first delay locked clock signal by variable delaying the source clock signal or the second delay locked clock signal according to whether the input control signal is activated in order to establish a delay lock between the source clock and the first feedback clock signal, A first delay locked loop for generating the first feedback clock by reflecting a delay path of the source clock;
And a variable delay circuit for variably delaying the phase-inverted source clock to output a delayed path between the source clock and the second feedback clock as the second delay locked clock, A second delay locked loop for generating a second feedback clock; And
And an operation control section for activating the input control signal in response to the first and second delay locked loops reaching a limit delay amount,
And a delay locked loop circuit.
10. The method of claim 9,
The operation control unit,
And to toggle a reset pulse for initiating the first delay locked loop in response to the activation of the input control signal. 11. The method of claim 10,
The first delay locked loop includes:
A first phase comparator for comparing the phase of the source clock with the phase of the first feedback clock;
A selection and delivery unit for selecting and outputting the source clock in an inactive period of the input control signal and selecting and outputting the second delay locked clock in an active period of the input control signal;
And outputs the delayed output clock as the first delayed fixed clock by activating the first fixed failure signal in response to reaching the limit delay amount by delaying the output clock of the selective transfer unit by a delay amount corresponding to the output signal of the first phase comparing unit A first variable delay line whose delay amount is initialized in response to the reset pulse; And
And a first delay replica model unit for reflecting the delay amount corresponding to the delay path of the source clock to the first delay locked clock and outputting it as the first feedback clock.
12. The method of claim 11,
The second delay locked loop comprising:
A second phase comparison unit for comparing phases of the source clock and the second feedback clock;
And outputs the second delay locked clock as the second delay locked clock by delaying the source clock whose phase is inverted by a delay amount corresponding to the output signal of the second phase comparing unit, A second variable delay line; And
And a second delay replica model unit for reflecting the delay amount corresponding to the delay path of the source clock to the second delay locked clock and outputting it as the second feedback clock.
13. The method of claim 12,
The operation control unit,
An input control signal output unit for activating the input control signal in response to activation of both the first fixing failure signal and the second fixing failure signal; And
And a reset pulse generator for toggling the reset pulse for a predetermined time in response to activation of the input control signal.
14. The method of claim 13,
Wherein the first fixed failure signal is activated in response to the first variable delay line reaching a threshold delay amount and is deactivated in response to the toggling of the reset pulse,
And a fixed failure determination unit for activating a final fixed failure signal in response to activation of the first fixed failure signal in an active period of the input control signal.
10. The method of claim 9,
And outputting the first delay locked clock as a final delay locked clock in response to the delay locked in the operation of the first delay locked loop, And a clock output multiplexer for outputting the second delay locked clock as the final delay locked clock.
A first delay fixing step of variably delaying the source clock to output a first delay locked clock as a delay locked state;
A second delay fixing step of variably delaying the source clock whose phase has been inverted to output a second delay locked clock as a delay locked state; And
When the delay fixing is not performed in the second delay fixing step following the first delay fixing step, the first delay fixing step is initialized and then the second delay fixing clock is applied to the first delay fixing step instead of the source clock A third delay fixing step of outputting the first delay locked clock
/ RTI > wherein the delay locked loop circuit comprises:
17. The method of claim 16,
Wherein the first delay fixing step includes:
A first comparing step of comparing a phase of the source clock with a phase of a first feedback clock;
A first delay amount adjusting step of adjusting a variable delay amount of the source clock according to a result of the operation of the first comparing step and outputting the variable delay amount as the first delay fixed clock;
A first fixed failure detection step of activating a first fixed failure signal in response to the variable delay amount adjustable in the first delay amount adjustment step being '0';
A first delay locked determination step of outputting the first delay locked clock as a final delay locked clock in response to the fact that a variable delay amount adjustable in the first delay amount adjusting step remains and delay lock is achieved in the first comparison step ; And
And a first delay modeling step of reflecting the delay path of the source clock to the first delay locked clock and outputting it as the first feedback clock.
18. The method of claim 17,
Wherein the second delay fixing step comprises:
A second comparison step of comparing the phase of the source clock with the phase of the second feedback clock;
A second delay amount adjustment step of adjusting the variable delay amount of the clock in which the phase of the source clock is inverted according to a result of the operation of the second comparison step and outputting the adjusted variable delay amount as the second delay fixed clock;
A second fixed failure detection step of activating a second fixed failure signal in response to the variable delay amount adjustable in the second delay amount adjustment step being '0';
A second delay locked determination step of outputting the second delay locked clock as a final delay locked clock in response to the fact that a variable delay amount adjustable in the second delay amount adjusting step remains and delay lock is achieved in the second comparison step ; And
And a second delay modeling step of reflecting the delay path of the source clock to the second delay locked clock and outputting it as the second feedback clock.
19. The method of claim 18,
Wherein the third delay fixing step comprises:
Activating an input control signal in response to both the first fixed failure signal and the second fixed failure signal being activated;
Initializing the variable delay amount adjusted in the first delay amount adjustment step to '0' in response to the activation of the input control signal; And
And applying the second delay locked clock instead of the source clock to the first delay amount adjusting step after the initializing step is completed to operate the first delay amount adjusting step again Way.
20. The method of claim 19,
Further comprising the step of activating a final fixed failure signal in response to the variable delay amount being adjustable in the first delay amount adjusting step as a result of the operation of operating the first delay amount adjusting step again, Loop circuit.

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