KR20140067878A - Memory devices and memory systems having the same - Google Patents

Abstract

A memory device includes a cell array and a storage unit. The cell array receives data at an address in response to a write command. The storage unit receives the address and data in response to the write command and outputs the data to the address of the cell array in response to a rewrite command. Therefore, the reliability of the memory device can be improved.

Description

[0001] MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME [0002] BACKGROUND OF THE INVENTION [0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory field, and more particularly, to a memory device and a memory system.

As the manufacturing process of a memory device such as a DRAM (Dynamic Random Access Memory) is gradually scaled-down, it becomes increasingly difficult to satisfy the specifications regarding the write recovery time (tWR) of the DRAM.

If the scaling-down continues in the future, the value of the contact resistance connecting between the storage capacitor of the DRAM cell and the access transistor increases, and the on-current of the access transistor also decreases. Thus, the total resistance from the bit line to the storage cell gradually increases, making it more and more difficult to fully charge the storage cell during a given write recovery time tWR.

In addition, the storage capacitance is further reduced as compared with the bit line capacitance, and the level of the charge sharing voltage is lowered, thereby reducing the sensing margin. Therefore, there is a problem that the failures of the memory cells due to the write recovery time tWR gradually increase. As a result, the reliability of the memory device is reduced.

An object of the present invention is to provide a memory device capable of increasing the reliability of a memory device while keeping the specification of a write recovery time.

It is another object of the present invention to provide a memory system including the memory device.

In order to accomplish one aspect of the present invention, a memory device according to an embodiment of the present invention includes a cell array and a storage unit. The cell array receives data at an address in response to a write command. The storage unit receives the address and the data in response to the write command and outputs the data to the address of the cell array in response to a rewrite command.

In one embodiment of the present invention, when the storage time of the data written to the storage unit is less than the write recovery time (tWR) of the cell array, the memory device stores the data whose storage time is less than the write recovery time (tWR) And a violation judgment unit for judging the violation data and counting the number of violation data.

In one embodiment of the present invention, the violation determining unit may output a warning signal (ALERT) when the number of violation data is equal to or greater than the threshold value.

In an embodiment of the present invention, the threshold value may be equal to the size of the storage unit.

In one embodiment of the present invention, the storage unit may rewrite all of the violation data in the cell array.

In one embodiment of the present invention, the storage unit may rewrite some data among the violation data in the cell array.

In one embodiment of the present invention, the memory device may output the data stored in the storage unit upon receiving the read command for the address of the violation data. The memory device may output the data stored in the cell array upon receiving a read command for an address other than the violation data.

In an embodiment of the present invention, the size of the storage unit may be smaller than the size of the cell array.

In one embodiment of the present invention, the size of the storage unit may be a maximum integer smaller than a value obtained by dividing the write recovery time (tWR) of the cell array by a minimum cycle of the write command.

In one embodiment of the present invention, the data recording rate of the storage unit may be faster than the data recording rate of the cell array.

In order to accomplish one aspect of the present invention, a memory system according to an embodiment of the present invention includes a memory device and a memory controller. The memory device comprising: a cell array for receiving data in an address in response to a write command; and a memory array for receiving the address and the data in response to the write command and outputting the data to the address of the cell array in response to a rewrite command And a storage unit. The memory controller outputs the write command and the rewrite command to the memory device, and provides the address and the data to the cell array and the storage unit.

In one embodiment of the present invention, when the storage time of the data written to the storage unit is less than the write recovery time (tWR) of the cell array, the memory system stores the data whose storage time is less than the write recovery time (tWR) And a violation judgment unit for judging the violation data and counting the number of violation data.

In one embodiment of the present invention, the memory device may include the violation determining unit.

In one embodiment of the present invention, the memory controller may include the violation determining unit.

In one embodiment of the present invention, the memory device may output the data stored in the storage unit upon receiving the read command for the address of the violation data. The memory device may output the data stored in the cell array upon receiving a read command for an address other than the violation data.

A memory device according to embodiments of the present invention includes a cell array and a storage unit for writing data. The storage unit stores data that violates the write recovery time (tWR) and its address. Reads data from the storage unit without reading data from the cell array when a read command for an address violating the write recovery time (tWR) arrives. Therefore, even if the cell array of the memory device does not satisfy the specification of the write recovery time tWR, the memory device can output correct data. Therefore, the reliability of the memory device can be improved.

1 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.
2 is a detailed block diagram illustrating the memory device of FIG.
3 is a timing chart showing the operation of the violation judgment unit.
4 is a timing chart showing the operation of the violation determination unit according to another embodiment of the present invention.
5 is a timing chart showing an operation for a read command of the memory device of FIG.
6 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.
7 is a block diagram illustrating a memory module including a memory device in accordance with embodiments of the present invention.
8 is a diagram illustrating an example in which a memory module according to embodiments of the present invention is applied to a mobile system.
9 is a diagram illustrating an example in which a memory module according to embodiments of the present invention is applied to a computing system.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.

Referring to FIG. 1, a memory system includes a memory controller 100 and a memory device 200.

The memory controller 100 controls the operation of the memory device 200. The memory controller 100 generates a command signal CMD and outputs the command signal CMD to the memory device 200. For example, the command signal CMD includes a write command, a read command, a precharge command, a rewrite command, and the like.

The memory controller 100 outputs an address ADDR and data DATA to the memory device 200. [ The address ADDR indicates an address in the cell array 220 in which the data DATA is stored. The address ADDR may include a bank address, a row address, and a column address.

According to an embodiment, the memory device 200 may be a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), a LPDDR SDRAM, a GDDR (Graphics Double Data Rate) SDRAM, a Rambus Dynamic Random Access (DRAM), such as a memory, or the like.

The memory device 200 includes a cell array 220, a storage unit 240, and a violation determination unit 260.

The cell array 220 includes a plurality of word lines extending in a first direction and a plurality of bit lines in a second direction intersecting the first direction. The cell array 220 includes a plurality of cells connected to the word lines and the bit lines.

The cell includes a switching device coupled to the word line and the bit line, and a storage capacitor coupled to the switching device. For example, the switching element may be an access transistor. Specifically, the word line may be connected to the gate electrode of the access transistor. The bit line may be connected to a source electrode of the access transistor. A drain electrode of the access transistor may be coupled to a first electrode of the storage capacitor.

The cell array 220 receives the address ADDR and the data DATA from the memory controller 100. The cell array 220 stores the data (DATA) in the address ADDR. Although not shown, the memory device 200 may further include a bank decoder for analyzing a bank address adjacent to the cell array 220, a row decoder for analyzing a row address, and a column decoder for analyzing a column address.

The storage unit 240 receives the address ADDR and the data DATA from the memory controller 100. The storage unit 240 stores the address ADDR and the data DATA. For example, the storage unit 240 may be a write buffer.

The storage unit 240 stores the address ADDR and the data DATA in violation of the write recovery time tWR of the cell array 220. The word line can be disabled by the precharge command before the data to be written according to the write command is sufficiently written into the memory cell. In this case, the data to be written becomes violation data that violates the write recovery time (tWR).

The violation determining unit 260 may set the data within the write recovery time tWR as violation data when the data written in the storage unit 240 is within the write recovery time tWR of the cell array 220 .

The violation determination unit 260 may count the number of violation data. The violation determination unit 260 may output a warning signal (ALERT) when the number of violation data is equal to or greater than the threshold value.

The configuration and operation of the memory device will be described later in detail with reference to FIG.

The memory controller 100 and the memory device 200 may be connected to each other via corresponding command pins, address pins, and data pins. The command pins transmit the command signal CMD through the command transmission line, the address pins transmit the address ADDR through the address transmission line, and the data pins can exchange the data DATA via the data transmission line. The memory controller 100 and the memory device 200 may further include a separate pin and a transmission line for transmitting an alert signal ALERT.

2 is a detailed block diagram illustrating the memory device of FIG.

Referring to FIGS. 1 and 2, the memory device includes the cell array 220, the storage unit 240, and the violation determination unit 260. The memory device may further include a counter indicating a current time.

The cell array 220 receives the data (DATA) from the memory controller 100 at the address ADDR in response to a write command. The cell array 220 outputs the data DATA stored in the address ADDR to the memory controller 100 in response to a read command.

The storage unit 240 receives the address ADDR and the data DATA from the memory controller 100 in response to a write command. The storage unit 240 may further receive the storage point (CO) of the data (DATA) from the counter. The storage unit 240 stores the address ADDR and the data DATA. The storage unit 240 may store a storage point (CO) of the data (DATA). The storage unit 240 outputs the data DATA to the address ADDR of the cell array 220 in response to a rewrite signal. The storage unit 240 may output the storage time point (CO) of the data DATA to the violation determining unit 260.

The storage unit 240 may output the data DATA corresponding to the address ADDR to the memory controller 100 in response to a read command.

The operation according to the rewrite command of the storage unit 240 will be described in detail with reference to FIG.

The operation according to the read command of the storage unit 240 will be described in detail with reference to FIG.

The size of the storage unit 240 is smaller than the size of the cell array 220. For example, the size of the storage unit 240 may be determined as a maximum integer less than a value obtained by dividing the write recovery time tWR of the cell array 220 by the minimum period of the write command.

For example, if the write recovery time tWR of the cell array 220 is 50 ns and the minimum repetition period of the write command according to the specification of the memory device 200 is 6 ns, then the write recovery time tWR The value divided by the minimum period of the write command is 8.3333, and the size of the storage unit 240 may be 8. The data corresponding to the eight adjacent write commands from the current time all become violation data that violates the write recovery time tWR and the data corresponding to the ninth write command from the current time is Normal data is obtained. Therefore, it may be appropriate to set the size of the storage unit 240 to 8.

Alternatively, the size of the storage unit 240 may be smaller than the write recovery time tWR of the cell array 220 divided by the minimum cycle of the write command. In the case where the write recovery time tWR of the cell array 220 is 50 ns and the minimum repetition period of the write command according to the specification of the memory device 200 is 6 ns, the write command is often repeated continuously The size of the storage unit 240 may be set to an integer less than eight.

The data recording speed of the storage unit 240 is faster than the data recording speed of the cell array 220. The data recording speed of the storage unit 240 is faster than the write recovery time tWR of the cell array 220. The write latency of the cell array 220 can be compensated by using the storage unit 240 since the data recording speed of the storage unit 240 is relatively faster than that of the cell array 220.

The violation determining unit 260 determines whether the write recovery time tWR of the data (DATA) written in the storage unit 240 is violated.

For example, when the storage time of the data (DATA) written in the storage unit 240 is less than the write recovery time (tWR) of the cell array 220, the violation determination unit 260 determines that the storage time Data less than the recovery time (tWR) is judged as violation data.

When the write recovery time tWR of the cell array 220 has not passed from the time when the data DATA is written in the storage unit 240, the data DATA is completely stored in the cell array 220 It can not be seen as a state. Therefore, the data (DATA) written in the storage unit 240 whose storage time is less than the write recovery time tWR of the cell array 220 becomes violation data.

On the other hand, when the write recovery time tWR of the cell array 220 has elapsed since the data DATA is written in the storage unit 240, the data DATA is completely charged to the cell array 220 . Therefore, the data (DATA) written in the storage unit 240 whose storage time is equal to or greater than the write recovery time tWR of the cell array 220 is not violation data.

For example, when the write recovery time tWR of the cell array 220 is 50 ns and the storage time of the data DATA written in the storage unit 240 is less than 50 ns, the data DATA is It can not be considered that the cell array 220 is fully charged yet, and thus corresponds to the violation data. On the other hand, when the storage time of the data (DATA) written in the storage unit 240 is 50 ns or more, the data (DATA) can be considered to be completely charged in the cell array 220, Do not.

The violation judging unit 260 judges whether the data (DATA) received from the storage unit 240 has been stored in the storage unit 240 using the storage time (CO) written in the storage unit 240 and the current time received by the counter It is possible to determine the storage time of the data (DATA). (CO) of the data (DATA) is less than the write recovery time (tWR) based on the current time corresponds to the violation data, and the storage time (CO) of the data (DATA) It can be determined that the data having the write recovery time tWR or more is not violation data.

For example, the violation determination unit 260 may determine the violation data every clock. Alternatively, the violation determining unit 260 may determine the violation data corresponding to several clocks.

The violation determination unit 260 counts the number of violation data. The violation determining unit 260 may output an alert signal (ALERT) to the memory controller 100 when the number of the violation data is equal to or greater than the threshold value.

For example, the threshold value may be equal to the size of the storage unit 240. That is, the violation determining unit 260 may output the alert signal (ALERT) to the memory controller 100 when the storage unit 240 is full.

The violation determining unit 260 can use the flag FL to manage whether or not the data (DATA) stored in the storage unit 260 is violation data.

For example, the data (DATA) determined as the violation data has a flag (FL) of 1 and the data (DATA) determined to be not the violation data may have a flag (FL) of 0.

When the storage time of the data DATA becomes equal to or greater than the write recovery time tWR at the time of the violation data determination, the flag FL of the data DATA is changed from 1 to 0.

When the new data DATA is input to the storage unit 260, the new data DATA is overwritten with the storage space of the flag FL. On the other hand, the new data (DATA) is not overwritten in the storage space of the flag FL.

The violation determining unit 260 may count the number of data in which the flag FL of the data DATA is 1 when counting the number of violation data.

3 is a timing chart showing the operation of the violation determining unit of Fig.

1 to 3, the first write command WR0, the first write command WR1, the second write command WR2, and the Nth write command WRN are transferred from the memory controller 100 to the memory Is continuously input to the device 200. [ The precharge command Pre is then input from the memory controller 100 to the memory device 200.

The data stored in the storage unit 240 by the first write command WR0 has a storage time longer than the write recovery time tWR when the precharge command Pre is input. Therefore, the data stored in the storage unit 240 by the first write command WR0 is not violation data.

On the other hand, when the precharge command Pre is inputted, the data stored in the storage unit 240 by the first to Nth write commands WR1 to WRN is smaller than the write recovery time tWR It has a short storage time. Therefore, the data stored in the storage unit 240 by the first to Nth write commands WR1 to WRN corresponds to violation data.

Assuming that the threshold value of the violation data is N, the alert signal ALERT is output from the memory device 200 to the memory controller 100 at the time when the precharge command Pre is input.

The memory controller 100 outputs the rewrite command REWRITE to the memory device 200 in response to the alert signal ALERT.

The storage unit 240 responds to the rewrite signal to write the data DATA stored in the storage unit 240 to the cell array 220 based on the address ADDR stored in the storage unit 240. [ To the above-mentioned address.

In the present embodiment, the storage unit 240 may rewrite all of the violation data in the cell array 220. [

For example, the memory controller 100 may output N rewrite commands corresponding to a threshold value of the violation data to the memory device 200. [ Accordingly, the storage unit 240 responds to the first through N-th rewrite commands REWR1 through REWRN with the data stored in the storage unit 240 by the first through Nth write commands WR1 through WRN The cell array 220 is rewritten.

4 is a timing chart showing the operation of the violation determination unit according to another embodiment of the present invention.

The operation of the violation determining unit according to the present embodiment is the same as that of the first embodiment except that K rewrite commands are received in response to the alert signal ALERT when the threshold value of the violation data is N, The same reference numerals are used for the same or similar components, and redundant explanations are omitted.

Referring to FIGS. 1, 2 and 4, when viewed from the point in time when the precharge command Pre is inputted, the first to Nth write commands WR1 to WRN are stored in the storage unit 240 The data has a storage time shorter than the write recovery time (tWR). Therefore, the data stored in the storage unit 240 by the first to Nth write commands WR1 to WRN corresponds to violation data.

Assuming that the threshold value of the violation data is N, the alert signal ALERT is output from the memory device 200 to the memory controller 100 at the time when the precharge command Pre is input.

The memory controller 100 outputs the rewrite command REWRITE to the memory device 200 in response to the alert signal ALERT.

The storage unit 240 responds to the rewrite signal to write the data DATA stored in the storage unit 240 to the cell array 220 based on the address ADDR stored in the storage unit 240. [ To the above-mentioned address.

In this embodiment, the storage unit 240 may rewrite some data of the violation data in the cell array 220. [

For example, the memory controller 100 may output K rewrite commands, which are smaller than N corresponding to the threshold value of the violation data, to the memory device 200. Accordingly, the storage unit 240 responds to the first to K-th rewrite commands REWR1 to REWRK with the data stored in the storage unit 240 by the first to Kth write commands WR1 to WRK And rewrites the data into the cell array 220.

Thus, the time for stopping the write and read operations by the rewrite operation can be reduced, and the performance of the memory device can be relatively improved.

Unlike the above, the storage unit 240 stores data stored in the storage unit 240 by the K write commands WRN to WR (N-K + 1) close to the precharge command Pre, To the cell array 220 in response to the first to K-th write commands REWR1 to REWRK.

5 is a timing chart showing the operation of the read command of the memory device 200 of FIG.

Referring to FIGS. 1 to 3 and 5, when the memory device 200 receives a read command, it determines whether the address ADDR of the read command corresponds to the violation data of the storage unit 240.

If the address ADDR of the read command corresponds to the violation data, the data stored in the storage unit 240 is output to the memory controller 100. On the other hand, if the address ADDR of the read command does not correspond to the violation data, the data stored in the cell array 220 is output to the memory controller 100.

When the data is read from the cell array 220, the incorrect data is read and the reliability of the memory device 200 is reduced. do.

When the read command for the address of the violation data is received, accurate data of the storage unit 240, which is an auxiliary storage space faster than the cell array 220, can be read out. Therefore, the reliability of the memory device 200 can be improved.

In FIG. 5, when the first read command RD1 indicates the address ADDR of the violation data, the data stored in the storage unit 240 is output.

According to the present embodiment, the storage unit 240 stores data that violates the write recovery time tWR and its address. Reads data from the storage unit 240 without reading data from the cell array 220 when a read command for an address violating the write recovery time tWR arrives. Therefore, even if the cell array 220 of the memory device 200 does not satisfy the write recovery time tWR specification, the memory device 200 can output accurate data. Therefore, the reliability of the memory device can be improved.

6 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.

The memory system according to the present embodiment is substantially the same as the memory system of FIGS. 1 to 5 except that the violation determining unit is included in the memory controller, so that the same reference numerals are used for the same or similar components, Duplicate description is omitted.

Referring to FIG. 6, the memory system includes a memory controller 300 and a memory device 400.

The memory controller 300 controls the operation of the memory device 400. The memory controller 300 generates a command signal CMD and outputs the command signal CMD to the memory device 400.

The memory controller 300 outputs the address ADDR and data DATA to the memory device 400. [ The address ADDR indicates an address in the cell array 420 in which the data DATA is stored.

The memory device 400 includes a cell array 420 and a storage unit 440.

The cell array 420 receives the address ADDR and the data DATA from the memory controller 300. The cell array 420 stores the data (DATA) in the address ADDR.

The storage unit 440 receives the address ADDR and the data DATA from the memory controller 300. The storage unit 440 stores the address ADDR and the data DATA.

The storage unit 440 stores the address ADDR and the data DATA in violation of the write recovery time tWR of the cell array 420.

In this embodiment, the violation determining unit 320 is included in the memory controller 300. [ The violation determining unit 320 may set the data within the write recovery time tWR as violation data when the data written in the storage unit 440 is within the write recovery time tWR of the cell array 420 .

The violation determination unit 320 may count the number of violation data. The violation determining unit 320 outputs the rewrite command to the memory device 400 when the number of the violation data is equal to or greater than the threshold value.

According to the present embodiment, the storage unit 240 stores data that violates the write recovery time tWR and its address. Reads data from the storage unit 240 without reading data from the cell array 220 when a read command for an address violating the write recovery time tWR arrives. Therefore, even if the cell array 220 of the memory device 200 does not satisfy the write recovery time tWR specification, the memory device 200 can output accurate data. Therefore, the reliability of the memory device can be improved.

7 is a block diagram illustrating a memory module including a memory device in accordance with embodiments of the present invention.

Referring to FIG. 7, the memory module 700 may include a plurality of memory devices 720. In accordance with an embodiment, the memory module 700 may be implemented as a single or dual inline memory module (UDIMM), a registered dual in-line memory module (RDIMM), a fully buffered dual in-line memory module (FBDIMM) In-line Memory Module) or other memory module.

The memory module 700 further includes a buffer 710 that receives commands, addresses, and data from the memory controller via a plurality of signal lines and buffers and provides the commands, addresses, and data to the memory devices 720 can do.

The data transmission lines between the buffer 710 and the memory devices 720 may be connected in a point-to-point manner. Also, the command / address transmission lines between the buffer 710 and the memory devices 720 may be connected in a multi-drop scheme, a daisy-chain scheme, or a fly-by-daisy-chain scheme. Because the buffer 710 buffers all of the commands, addresses, and data, the memory controller can interface with the memory module 700 by driving only the load of the buffer 710. Accordingly, the memory module 700 may include a greater number of memory devices 720 and memory ranks, and the memory system may include a greater number of memory modules 700.

The memory device 720 previously generates a refresh candidate address corresponding to a page scheduled to be refreshed after a monitoring interval corresponding to a plurality of refresh intervals and monitors whether or not an active command is performed for the refresh candidate address during the monitoring interval And if the active command is performed more than once for the refresh candidate address during the monitoring interval, the active command is never performed for the refresh candidate address during the monitoring interval without refreshing the page corresponding to the refresh candidate address The page corresponding to the refresh candidate address can be refreshed. Therefore, the memory device 720 can selectively reduce refresh operation only for pages requiring refreshing, thereby reducing power consumption associated with performing the refresh operation. The memory device 720 may be implemented as the memory device 200 or 400 shown in FIG. 1 or 6. Since the configuration and operation of the memory device 200 or 400 of FIG. 1 or 6 has been described in detail with reference to FIGS. 1 to 6, a detailed description of the memory device 720 is omitted here.

8 is a diagram illustrating an example in which a memory system according to embodiments of the present invention is applied to a mobile system.

8, the mobile system 800 includes an application processor 810, a communication unit 820, a user interface 830, a nonvolatile memory device (NVM) 840, a volatile memory device (VM) (850) and a power supply (860). According to an embodiment, the mobile system 800 may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera Camera, a music player, a portable game console, a navigation system, and the like.

The application processor 810 may execute applications that provide Internet browsers, games, animations, and the like. According to an embodiment, the application processor 810 may include a single processor core or a plurality of processor cores (Multi-Core). For example, the application processor 810 may include a multi-core such as a dual-core, a quad-core, and a hexa-core. Also, according to an embodiment, the application processor 810 may further include a cache memory located internally or externally.

The communication unit 820 can perform wireless communication or wired communication with an external device. For example, the communication unit 820 may be an Ethernet communication, a Near Field Communication (NFC), a Radio Frequency Identification (RFID) communication, a Mobile Telecommunication, a memory card communication, A universal serial bus (USB) communication, and the like. For example, the communication unit 820 may include a baseband chip set, and may support communication such as GSM, GPRS, WCDMA, and HSxPA.

The volatile memory device 850 may store data processed by the application processor 810, or may operate as a working memory. The volatile memory device 850 generates a refresh candidate address corresponding to a page scheduled to be refreshed after a monitoring interval corresponding to a plurality of refresh intervals in advance and determines whether an active command is performed for the refresh candidate address during the monitoring interval Wherein the active command is once again performed for the refresh candidate address during the monitoring interval without refreshing a page corresponding to the refresh candidate address if the active command is performed more than once for the refresh candidate address during the monitoring interval The page corresponding to the refresh candidate address can be refreshed. Therefore, the volatile memory device 850 can selectively reduce refresh operation only for pages requiring refreshing, thereby reducing power consumption associated with the refresh operation. The volatile memory device 850 may be implemented as the memory device 200 or 400 shown in FIG. 1 or 6. The configuration and operation of the memory device 200 or 400 of FIG. 1 or 6 has been described in detail with reference to FIGS. 1 to 6. Therefore, detailed description of the volatile memory device 850 is omitted here.

Non-volatile memory device 840 may store a boot image for booting mobile system 800. For example, the non-volatile memory device 840 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM) A Floating Gate Memory, a Polymer Random Access Memory (PoRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or the like.

The user interface 830 may include one or more input devices such as a keypad, a touch screen, and / or one or more output devices such as speakers, display devices, and the like. The power supply 860 can supply the operating voltage of the mobile system 800.

In addition, according to an embodiment, the mobile system 800 may further include an image processor and may include a memory card, a solid state drive (SSD), a hard disk drive (HDD) , CD-ROM (CD-ROM), and the like.

The components of the mobile system 800 or the mobile system 800 may be implemented using various types of packages such as Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages ), Plastic Leaded Chip Carrier (PLCC), Plastic In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, COB (Chip On Board), CERDIP (Ceramic Dual In- Metric Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Pack (TQFP) System In Package (MCP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (WSP).

9 is a diagram illustrating an example in which a memory system according to embodiments of the present invention is applied to a computing system.

9, the computing system 900 includes a processor 910, an input / output hub (IOH) 920, an input / output controller hub (ICH) 930, at least one memory module 940, and a graphics card 950. [ . According to an embodiment, the computing system 900 may be a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smart phone, A personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, A music player, a portable game console, a navigation system, and the like.

The processor 910 may execute various computing functions, such as executing specific calculations or specific software that executes the tasks. For example, the processor 910 may be a microprocessor or a central processing unit (CPU). In accordance with an embodiment, the processor 910 may comprise one processor core or may comprise a plurality of processor cores. For example, the processor 910 may include a multi-core such as a dual-core, a quad-core, and a hexa-core. Also shown in FIG. 9 is a computing system 900 that includes a single processor 910, but in accordance with an embodiment, the computing system 900 may include a plurality of processors.

The processor 910 may include a memory controller 911 that controls the operation of the memory module 940. The memory controller 911 included in the processor 910 may be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 911 and the memory module 940 may be implemented as a single channel including a plurality of signal lines or a plurality of channels. Also, one or more memory modules 940 may be connected to each channel. According to an embodiment, the memory controller 911 may be located in the input / output hub 920. The input / output hub 920 including the memory controller 911 may be referred to as a memory controller hub (MCH).

The memory module 940 may include a plurality of memory devices (MEM) 941 that store data provided from the memory controller 911. The memory device 941 previously generates a refresh candidate address corresponding to a page scheduled to be refreshed after a monitoring interval corresponding to a plurality of refresh intervals and monitors whether or not an active command is performed for the refresh candidate address during the monitoring interval And if the active command is performed more than once for the refresh candidate address during the monitoring interval, the active command is never performed for the refresh candidate address during the monitoring interval without refreshing the page corresponding to the refresh candidate address The page corresponding to the refresh candidate address can be refreshed. Therefore, the memory device 941 can selectively reduce refresh operation only for pages requiring refreshing, thereby reducing power consumption associated with the refresh operation. The memory device 941 may be implemented as the memory device 200 or 400 shown in FIG. 1 or 6. Since the configuration and operation of the memory device 200 or 400 of FIG. 1 or 6 have been described in detail with reference to FIGS. 1 to 6, a detailed description of the memory device 941 is omitted here.

The input / output hub 920 may manage data transfer between the processor 910 and devices such as the graphics card 950. [ The input / output hub 920 may be coupled to the processor 910 through various types of interfaces. For example, the input / output hub 920 and the processor 910 may be connected to a front side bus (FSB), a system bus, a HyperTransport, a Lightning Data Transport LDT), QuickPath Interconnect (QPI), and Common System Interface (CSI). The input / output hub 920 may provide various interfaces with the devices. For example, the input / output hub 920 may include an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe), a Communications Streaming Architecture (CSA) Can be provided. Although FIG. 9 illustrates a computing system 900 including one input / output hub 920, according to an embodiment, the computing system 900 may include a plurality of input / output hubs.

Graphics card 950 may be coupled to input / output hub 920 via AGP or PCIe. The graphics card 950 may control a display device for displaying images. Graphics card 950 may include an internal processor and an internal memory device for image data processing. Depending on the embodiment, the graphics card 950 may be external to the input / output hub 920 or may be located inside the input / output hub 920. The graphics device included in the input / output hub 920 may be referred to as Integrated Graphics. In addition, the input / output hub 920, which includes a memory controller and a graphics device, may be referred to as a Graphics and Memory Controller Hub (GMCH).

The input / output controller hub 930 may perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input / output controller hub 930 may be connected to the input / output hub 920 through an internal bus. For example, the input / output hub 920 and the input / output controller hub 930 may be connected through a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), a PCIe .

The I / O controller hub 930 may provide various interfaces with peripheral devices. For example, the input / output controller hub 930 may include a universal serial bus (USB) port, a Serial Advanced Technology Attachment (SATA) port, a general purpose input / output (GPIO) (LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, and the like.

The processor 910, the input / output hub 920 and the input / output controller hub 930 may be implemented as discrete chipsets or integrated circuits, respectively, and may include a processor 910, an input / output hub 920, Two or more components among the controller hub 930 may be implemented as one chipset.

The present invention can be usefully used in any electronic device having a memory device. For example, the present invention may be applied to a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, A personal computer (PC), a server computer, a workstation, a laptop, a digital television, a set-top box, a music player, , A portable game console (Portable Game Console), a navigation system, and the like.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It will be understood that the invention may be modified and varied without departing from the scope of the invention.

Claims (10)

A cell array for receiving data in an address in response to a write command; And
A storage unit which receives the address and the data in response to the write command and outputs the data to the address of the cell array in response to a rewrite command; And
(TWR) when the storage time of the data written to the storage unit is less than the write recovery time (tWR) of the cell array, and counts the number of violation data The violation judgment unit. The memory device according to claim 1, wherein the violation determining unit outputs a warning signal (ALERT) when the number of violation data is equal to or greater than a threshold value. 3. The memory device of claim 2, wherein the threshold value is equal to the size of the storage unit. The memory device according to claim 1, wherein the storage unit rewrites all of the violation data into the cell array. The memory device according to claim 1, wherein the storage unit rewrites some of the violation data to the cell array. The apparatus according to claim 1, further comprising: a storage unit for storing data stored in said storage unit upon receiving a read command for an address of said violation data;
And outputs the data stored in the cell array upon receiving a read command for an address other than the violation data. The memory device of claim 1, wherein the size of the storage unit is smaller than the size of the cell array. The memory device according to claim 7, wherein the size of the storage unit is a maximum integer smaller than a value obtained by dividing the write recovery time (tWR) of the cell array by a minimum cycle of the write command. The memory device according to claim 1, wherein the data recording speed of the storage unit is faster than the data recording speed of the cell array. A storage unit for receiving the address and the data in response to the write command and outputting the data to the address of the cell array in response to the rewrite command, A memory device including; And
A memory controller for outputting the write command and the rewrite command to the memory device and providing the address and the data to the cell array and the storage unit; And
(TWR) when the storage time of the data written in the storage unit is less than the write recovery time (tWR) of the cell array, and counts the number of violation data And a violation judgment unit for detecting a violation of the violation.

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