KR20140064375A - Multi-core processor device in the mission computer and controlling method for the same - Google Patents

Multi-core processor device in the mission computer and controlling method for the same Download PDF

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KR20140064375A
KR20140064375A KR1020120131648A KR20120131648A KR20140064375A KR 20140064375 A KR20140064375 A KR 20140064375A KR 1020120131648 A KR1020120131648 A KR 1020120131648A KR 20120131648 A KR20120131648 A KR 20120131648A KR 20140064375 A KR20140064375 A KR 20140064375A
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South Korea
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core
data
processor
task
overload
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KR1020120131648A
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Korean (ko)
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원현권
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한국항공우주산업 주식회사
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Priority to KR1020120131648A priority Critical patent/KR20140064375A/en
Publication of KR20140064375A publication Critical patent/KR20140064375A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Hardware Redundancy (AREA)

Abstract

The present invention provides a multi-core processor device of IUFC included in a mission computer and a control method for the same. the multi-core processor device of the IUFC includes a multi-core processor forming an inner structure as a plurality of multi-cores and separating and processing multiple tasks in an openMP parallel program method; a UART communication task inputted by the multi-core processor; and an IUFC module processing data processing tasks including the communication and the data task with avionic equipment and displaying the same through a forward upward display. The present invention forms a processor structure of the IUFC included in the mission computer based on a dual core and performing parallel processing by separating a UART communication task area and a data processing task area. Therefore, the present invention rapidly processes the requested task of the IUFC by removing an overtime phenomenon generated in the processor based on a single core and maximizes performances of the mission computer.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-core processor apparatus and a control method thereof. More particularly,

The present invention relates to a multi-core processor device and a control method thereof mounted on a mission computer. More particularly, the present invention relates to a multi-core processor device and a control method thereof. More particularly, the processor architecture of IUFC, MFD, Core processor apparatus mounted on a mission computer for maximizing the performance of a mission computer by dividing task areas into parallel processing, and a control method thereof.

Generally, an aircraft using an FBW (fly-by-wire) method is equipped with an operational flight program (hereinafter referred to as OFP), which is separately manufactured for each type of aircraft, and is responsible for various mission visibility and control Mission computers are installed and widely used. Here, the mission computer performs the navigation system and armed computer control functions through an interface such as 1553B with various components (Line Replacement Unit, LRU) mounted on the aircraft. The mission computer includes an MFD (Multi Function Display), a HUD Display) and IUFC (Integrated Up-Front Control). At this time, the OFP (Flight Operation Program) includes the FC (Emergency Control Fire Control) and the HUD (forward upward visibility) OFP in the processor module MPM and the HPM, respectively, and the MFD and the IUFC OFP in the GPM. The FC OFP performs navigation, identification, communication, air-to-air and air-to-air mission functions, failure manifestation and recording, and communication between the respective processes. The HUD OFP provides the aircraft speed, altitude, various flight information symbols, It plays a role of visualizing related information. In addition, the IUFC OFP performs data input of avionics mode, function selection, and target information for mission planning and execution.

Referring to FIG. 1, the multifunctional vision apparatus provided in the conventional mission computer as described above includes, for example, a UART communication task transmitted and received according to a forward uplink control flight operation program (hereinafter referred to as IUFC OFP) A single-core processor 70 for processing communications and data tasks on a single-core basis in priority order;

And an IUFC module 72 for processing UART communication tasks and data processing tasks inputted from the single core processor 70 and displaying them through a forward upward viewer 71.

The IUFC module 72 provides functions for an aircraft pilot to control data such as avionics mode, function selection, and target information for a mission. In addition, the IUFC OFP is an application for controlling the IUFC, which displays flight information such as communication, navigation, and peer identification, and provides a function by which an aircraft pilot can control data.

The operation of the multifunctional vision apparatus provided in the conventional mission computer as described above may be performed by first executing a process in which the flight information such as communication, navigation, and peer identification, processed by the IUFC OFP in the mission computer 73, . The single-core processor 70 processes the input tasks in a single-core manner according to a priority order. For example, the UART communication task, the communication with the avionics equipment, and the data task are classified into a single-core And inputs it to the IUFC module 72. The IUFC module 72 processes the UART communication task and the data processing task input from the single core processor 70 and displays it through the forward upward viewer 71.

However, since the single-core processor mounted on the mission computer processes the input multiple data in a single-core structure according to priority, the overhead phenomenon occurs frequently during multi-task processing. The ability to quickly process IUFC, MFD, FC, and HUD tasks, thereby significantly reducing the performance of mission computers. In addition, the processor communicating with IUFC modules (including MFD, FC, and HUD) Therefore, if it is necessary to expand and install a large amount of high-tech avionics equipment on an aircraft, it can not be processed normally, thereby causing a problem of significantly lowering the operational reliability of the mission computer.

Accordingly, the present invention has been made to solve the above-mentioned problems of the conventional art, and it is an object of the present invention to provide an IUFC, a MFD, a FC, and a HUD, A multi-core processor device mounted on a mission computer, and a control method thereof.

Another object of the present invention is to provide a method and system for processing a given task quickly within a given time due to a dual-core based IUFC, MFD, FC, and HUD processors, even though a large amount of data is operated by a large number of advanced avionics devices mounted on an aircraft And a method of controlling the same.

According to an aspect of the present invention, there is provided a multi-core processor including: a multi-core processor including an internal structure including a plurality of multi-cores and a plurality of tasks separated in an OpenMP parallel programming manner;

A UART communication task input from the multicore processor, and an IUFC module (including MFD, FC and HUD modules) for processing data processing tasks including data communication tasks and communication with avionics devices and displaying them through a forward upward viewer A multi-core processor device mounted on a mission computer is provided.

Another feature of the present invention is that when the data processed by the IUFC OFP (MFD, FC and HUD OFP) of the mission computer provided in the aircraft is input to the multicore processor, these data are transmitted to the UART communication task A first process of separating the input signal into a first signal;

A second step of independently processing only a UART communication task in which one core of the multicore processor is transferred to and received from the IUFC module (including the MFD, the FC, and the HUD module) during the first process;

And a third step of independently processing the remaining data except for the UART communication task and transmitting / receiving the IUFC module (including the MFD, the FC and the HUD module) on one core of the multicore processor during the first process A method of controlling a multicore processor device is provided.

According to the present invention, the processor structure of the IUFC (including the MFD, the FC and the HUD) provided in the mission computer is configured based on the dual core so that the UART communication task area and the data processing task area are separated and processed in parallel, Based processor, it is possible to quickly process the requested IUFC, MFD, FC, and HUD tasks, thereby maximizing the performance of the mission computer.

In addition, since the present invention as described above includes processors of IUFC, MFD, FC, and HUD based on a dual core, even if a large amount of high-tech avionics are mounted on an aircraft, a given task is quickly performed within a given time So that the operation reliability of the mission computer can be significantly improved.

1 is an explanatory view schematically explaining a multifunctional vision apparatus provided in a mission computer in the past;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a multi-
3 is a flowchart of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of a multicore processor apparatus mounted on a mission computer according to the present invention will be described with reference to the accompanying drawings.

However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals designate like elements throughout the specification. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The term " comprises " And / or "comprising" does not exclude the presence or addition of one or more other elements, steps, operations, and / or elements.

Example

FIG. 2 is an explanatory diagram schematically illustrating a multicore processor apparatus mounted on a mission computer, and FIG. 3 is a flowchart of the present invention.

Referring to FIG. 2, a multi-core processor apparatus mounted on a mission computer according to an embodiment of the present invention includes:

A multi-core processor 1 for constructing an internal structure of a plurality of multicore cores and for separating and processing multiple tasks in a parallel programming manner of an OpenMP Architecture Review Board;

A function module 3 for processing a data processing task including a communication task of the UART communication task inputted from the multicore processor 1 and the avionics equipment and a data task and displaying the data task through the forward upward viewer 2 .

Here, the functional module 3 may be configured as any one of an IUFC, an MFD, an FC, and a HUD.

The function module 3 functions to allow an aircraft pilot to control data such as avionics mode, function selection, and target information for a mission. In addition, the MFD, FC and HUD are driven by the OFP. For example, the IUFC OFP displays flight information such as communication, navigation, and peer identification, and controls an IUFC providing a function by which an aircraft pilot can control data Application.

The multicore processor 1 includes a first core 4 for transmitting / receiving a UART communication task to / from the functional module 3;

And a second core 5 for transmitting / receiving data other than the UART communication task of the first core 4 to / from the functional module 3 only.

Furthermore, the multicore processor 1 may be configured in a quad core form. In addition, the multicore processor 1 designates the tasks of the UART communication task for transmitting and receiving with the function module 3 as a core that independently controls the reception area and a core that independently controls the reception area, and is configured to be processed in parallel can do.

Here, the UART communication is an RS-485 serial interface, and transmits and receives data at a communication speed of, for example, 115200 bps. The UART communication is divided into a time for transmitting data to the function module 3 in the multicore processor 1 and a time for receiving data from the function module 3.

In another embodiment of the present invention, as shown in FIG. 2, the overload state of a plurality of cores connected to the multicore processor 1 and provided in the multicore processor 1 is detected, and acceleration processing An overload detection module (6) for outputting a control signal;

(4, 5 or quad-core) of the multi-core processor (1) in which the overload is generated according to the acceleration process control signal of the overload detection module (6) Processing module (7).

Next, a control method of the apparatus of the present invention having the above-described configuration will be described.

The method of the present invention is characterized in that when data to be processed by an IUFC (including MFD, FC and HUD) OFP of a mission computer in an initial state S1 is input to a multicore processor as shown in FIG. 3, (S2) for separating the remaining data tasks into the remaining data tasks;

A second step S3 of independently processing only a UART communication task in which one core of the multicore processor is transmitted and received to the functional module during the first step S2;

During the first step S2, the core of the multicore processor independently processes only the remaining data except for the UART communication task, and transmits / processes the data to / from the functional module.

During the second process (S2) or the third process (S3), the overload detection module detects an overload state of each of a plurality of cores provided in the multicore processor, and outputs an acceleration process control signal according to the overload. .

Further, after the fourth process, the data acceleration processing module processes the data in the corresponding core (4, 5 or quad core) of the multicore processor 1 in which the overload is generated according to the acceleration process control signal of the overload detection module 6 To thereby overcome the overload of the core.

In other words, the multi-core processor device 10 of the IUFC (including the MFD, FC and HUD) of the present invention also operates when the mission computer 8 of the aircraft is operated to perform the set task. At this time, the IUFC, MFD, FC of the mission computer 8, and OFP of the HUD, for example, IUFC OFP are driven to display flight information such as communication, navigation, and peer identification, and the pilot controls the data.

Herein, although the above process is limited to the IUFC OFP, the remaining MFD, FC, and HUD OFP are also operated in the same process according to the set contents.

During the operation of the IUFC OFP (including MFD, FC and HUD OFP), the multicore processor 1 independently separates the multiple tasks inputted from the mission computer 8 in the parallel program method of the OpenMP Architecture Review Board And outputs it to the function module 3.

At this time, the first core 4 of the multicore processor 1 independently processes only the UART communication task transmitted and received among the inputted multiple tasks to the functional module 3, and transmits / receives the UART communication task to / from the functional module 3. On the other hand, the second core 5 of the multicore processor 1 processes only the remaining data except for the UART communication task of the first core 4 with the functional module 3.

Therefore, when the multiple tasks are processed in the off-amp parallel program system, only the UART communication task is performed by the first core 4 and only the remaining data except the UART communication task is executed by the second core 5 The task is processed in real time in the multi-core processor 1 without overtime, thereby improving the performance of the mission computer 8.

At this time, when the multicore processor 1 is configured as a quad core type during the above process, the efficiency of processing data is further increased when each core independently performs data. During the above process, the UART communication task for transmitting / receiving the multicore processor 1 to / from the functional module 3 is designated as a core independent of the reception area and a core independent of the reception area, When configured, the processing efficiency of the mission computer can be further maximized because the processor does not have overtime.

During the above process, the overload detection module 6 of the inventive device 10 is connected to the multicore processor 1 and is connected to a plurality of cores 4, 5 or quad core ), And when the data is processed at the normal speed, the current state is maintained. On the other hand, if the overload occurs, the acceleration processing control signal according to the overload is outputted to the data acceleration processing module 7. Then, the data acceleration processing module 7 accelerates the data processing in the corresponding core (4, 5 or quad-core) of the multicore processor 1 in which the overload is generated according to the acceleration processing control signal of the overload detection module 6 To overcome the overload of the core.

1: multicore processor 2: forward upward view generator
3: Function module 4: First core
5: second core 6: overload detection module
7: Data Acceleration Processing Module 8: Mission Computer
9: Mission Computer 10: Multicore Processor Unit

Claims (10)

A multi-core processor for constructing an internal structure of a plurality of multicore cores and for separating and processing multiple tasks in an OpenMP parallel programming manner;
A function module for processing a data processing task including a UART communication task input from the multicore processor and communication with avionics equipment and a data task and displaying the task through a forward upward viewer, . The method according to claim 1,
The multi-core processor includes a first core for transmitting / receiving a UART communication task to / from a functional module only;
And a second core that transmits / receives data other than the UART communication task of the first core to / from the functional module exclusively. The method according to claim 1,
Wherein the multi-core processor is configured as a quad-core type. 4. The method according to any one of claims 1 to 3,
Wherein the multicore processor is configured to process a task of a UART communication task for transmitting and receiving a function module independently of a receiving area by designating a core independent of a receiving area, Mounted multicore processor device. The method according to claim 1,
The multi-core processor includes an overload detection module for detecting an overload state of a plurality of cores provided in the multi-core processor and outputting an acceleration process control signal according to the overload. Device. The method according to claim 1,
Wherein the function module comprises one of an IUFC, an MFD, an FC, and a HUD. The method according to claim 1,
Wherein the multicore processor is provided with a data acceleration processing module for accelerating data processing in a corresponding core of a multicore processor in which an overload is generated according to an acceleration processing control signal of an overload detection module to eliminate an overload of the core. A multicore processor device mounted on a computer. A first step of separating the data processed by the IUFC, the MFD, the FC and the HUD OFP of the mission computer provided in the aircraft into the UART communication task and the rest of the data task when the data is input to the multicore processor;
A second step of independently processing only a UART communication task in which one core of the multicore processor is transferred to and received from the functional module during the first process;
Core processor of the multi-core processor independently processes only the remaining data except for the UART communication task and transmits / receives the data to / from the functional module. 9. The method of claim 8,
The overload detection module may further include a fourth step of detecting an overload state of a plurality of cores provided in the multicore processor and outputting an acceleration process control signal according to the overload during the second process or the third process, Core processor device mounted on a computer. 10. The method of claim 9,
After the fourth process, the data acceleration process module further accelerates data processing in the corresponding core of the multicore processor in which the overload is generated according to the acceleration process control signal of the overload detection module to thereby overcome the overload of the core Core processor device to be mounted on a mission computer.
KR1020120131648A 2012-11-20 2012-11-20 Multi-core processor device in the mission computer and controlling method for the same KR20140064375A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190089590A (en) * 2018-01-23 2019-07-31 한국항공우주산업 주식회사 Mission Computer and the duplication method
CN113485953A (en) * 2021-05-26 2021-10-08 加弘科技咨询(上海)有限公司 Multi-core embedded system and method for realizing communication based on serial port virtualization

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190089590A (en) * 2018-01-23 2019-07-31 한국항공우주산업 주식회사 Mission Computer and the duplication method
CN113485953A (en) * 2021-05-26 2021-10-08 加弘科技咨询(上海)有限公司 Multi-core embedded system and method for realizing communication based on serial port virtualization

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