KR20140062770A - Memory controller and memroy system including ecc encoder for generating new parity - Google Patents

Memory controller and memroy system including ecc encoder for generating new parity Download PDF

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KR20140062770A
KR20140062770A KR1020120129548A KR20120129548A KR20140062770A KR 20140062770 A KR20140062770 A KR 20140062770A KR 1020120129548 A KR1020120129548 A KR 1020120129548A KR 20120129548 A KR20120129548 A KR 20120129548A KR 20140062770 A KR20140062770 A KR 20140062770A
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data
parity
memory device
new
memory
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KR1020120129548A
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Korean (ko)
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KR102002044B1 (en
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이기준
공준진
임세진
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삼성전자주식회사
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Priority to KR1020120129548A priority Critical patent/KR102002044B1/en
Priority to US14/071,771 priority patent/US9311181B2/en
Priority to DE102013112195.0A priority patent/DE102013112195A1/en
Priority to TW102140195A priority patent/TWI627535B/en
Priority to JP2013235041A priority patent/JP2014099174A/en
Priority to CN201310575217.0A priority patent/CN103824599B/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

The present invention relates to a memory controller that generates a new parity when some data in the memory device changes. A memory controller according to an embodiment of the present invention includes a data location identifier for identifying a location of the data to be changed; And a data difference calculator for calculating a data difference (Ddif) between the new data (Dnew) input from the host and the existing data (Dold) input from the memory device, ; And a parity calculator for calculating a new parity Pnew using the existing parity Pold and the data difference Ddif stored in the memory device. According to the present invention, since the new parity is obtained using only the changed data, the data read time, parity generation time, and power consumption can be reduced.

Description

[0001] MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING ECC ENCODER FOR GENERATING NEW PARITY [0002] BACKGROUND OF THE INVENTION [0003]

The present invention relates to semiconductor memory systems, and more particularly to an error correction code encoder and a memory controller and memory system including the same.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. The semiconductor memory device includes volatile memory devices such as DRAM and SRAM, and nonvolatile memory devices such as flash memory and MRAM (Magnetic RAM).

An error may occur in the process of storing data in the memory device and reading the stored data. In order to detect and correct such errors, various error correction codes have been used. The error correction codes include a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Low Density Parity Check (LDPC) code, and the like.

When storing data in a memory device, parity is also stored in the memory device together with the data for error correction. When some data stored in the memory device is changed, all data stored with the parity must be read in order to create a new parity. This may cause data read time, parity generation time, and power consumption to increase.

SUMMARY OF THE INVENTION The present invention is directed to a memory controller and memory system capable of reducing data read time, parity generation time, and power consumption when some data stored in a memory device is changed to generate a new parity. .

The present invention relates to a memory controller that generates a new parity when some data in the memory device changes. A memory controller according to an embodiment of the present invention includes a data location identifier for identifying a location of the data to be changed; And a data difference calculator for calculating a data difference (Ddif) between the new data (Dnew) input from the host and the existing data (Dold) input from the memory device, ; And a parity calculator for calculating a new parity Pnew using the existing parity Pold and the data difference Ddif stored in the memory device.

As an embodiment, the data location identifier, the data difference calculator, and the parity calculator may be included in a new parity generator. Here, the new parity generator may be located in or outside the ECC encoder.

In another embodiment, the data difference calculator may process all unchanged data in the data stored in the memory device as 0, and calculate a data difference (Ddif) between the new data (Dnew) and the existing data (Dold) have. Meanwhile, the data difference calculator may divide the changed partial data into a plurality of areas, and calculate a difference between new data and existing data in each area. The data difference calculator may calculate a data difference between the new data and the existing data through an XOR operation.

A memory system according to an embodiment of the present invention includes a memory device for storing data and a parity; A host providing new data (Dnew) and location information for modifying some data stored in the memory device; And a controller for receiving new data and position information from the host, calculating a data difference (Ddif) between new data provided from the host and existing data input from the memory device, and storing the existing parity And a memory controller for generating a new parity Pnew using the data difference Ddif.

In an embodiment, the memory controller further comprises: a data location identifier that identifies the location of some of the data being changed; (Dnif) for calculating a data difference (Ddif) between the new data (Dnew) input from the host and the existing data (Dold) input from the memory device A calculator; And a parity calculator for calculating a new parity Pnew using the existing parity Pold and the data difference Ddif.

As an embodiment, the data difference calculator may process all unchanged data in the data stored in the memory device as 0, and calculate a data difference (Ddif) between the new data (Dnew) and the existing data (Dold) . The data difference calculator may divide the changed partial data into a plurality of areas and calculate a difference between new data and existing data in each area.

In another embodiment, the memory controller may have the data location identifier, the data difference calculator, and the parity calculator in an ECC encoder. The ECC encoder may be used for binary, non-binary linear or non-linear codes.

In the present invention, when a part of data stored in a memory device is changed, a new parity is generated using some changed data without reading unchanged data. According to the present invention, since the new parity is obtained using only the changed data, the data read time, parity generation time, and power consumption can be reduced.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
2 is a block diagram illustrating the memory device 1100 shown in FIG.
FIGS. 3 and 4 are circuit diagrams showing an embodiment of the memory cell array shown in FIG. 2. FIG.
5 is a block diagram showing the memory controller shown in FIG.
6 is a block diagram illustrating an exemplary new parity generator shown in FIG.
FIGS. 7 to 11 are diagrams or block diagrams for illustrating the operation of the new parity generator shown in FIG. 6 by way of example.
12 is a flowchart showing a new parity generation method of the memory system according to the embodiment of the present invention.
13 is a chart showing an example of a parity check matrix.
14 is a diagram showing a case where the first 1-byte data is changed in the parity check matrix shown in FIG.
FIG. 15 is a diagram showing an example of performing a new parity generation operation for each area in the parity check matrix shown in FIG.
16 is a block diagram showing an application example of the memory system shown in Fig.
17 shows an example in which the memory system according to the embodiment of the present invention is implemented as a memory card.
FIG. 18 shows an example in which the memory system according to the embodiment of the present invention is implemented as a solid state drive (SSD).
19 is a block diagram illustrating an example in which a memory system according to an embodiment of the present invention is applied to a computing system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

Ⅰ. A memory system comprising an ECC encoder

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention. Referring to Figure 1, a memory system 1000 includes a memory device 1100, a memory controller 1200, and a host 1300.

The memory device 1100 includes a volatile memory device and a nonvolatile memory device. A volatile memory device is a memory device that loses stored data when power is interrupted. Volatile memory devices include SRAMs and DRAMs. A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). The memory device 1100 may experience a bit error during use, and various methods for correcting errors are used.

The memory controller 1200 is connected between the memory device 1100 and the host 1300. The memory controller 1200 accesses the memory device 1100 in response to a request from the host 1300. The memory controller 1200 receives data (DATA) from the host 1300 and generates coded data (DATA_C). The memory controller 1200 can provide the command CMD, the address ADDR, the encoded data DATA_C, and the control signal CTRL to the memory device 1100. [

Meanwhile, the memory controller 1200 receives the encoded data (DATA_C) from the memory device 1100 and decodes the encoded data (DATA_C) to recover original data (DATA). The memory controller 1200 can transmit the restored data (DATA) to the host 1300. [

Continuing to refer to FIG. 1, memory controller 1200 includes an ECC encoder 1270. The ECC encoder 1270 performs ECC encoding on data to be provided to the memory device 1100 and generates encoded data DTAT_C to which parity is added. The ECC encoder 1270 can correct errors using parity.

The ECC encoder 1270 may be a low density parity check (LDPC) code, a BCH code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis- It is possible to correct an error using coded modulation such as BCM (Block Coded Modulation).

On the other hand, when a part of the data stored in the memory device 1100 is changed, the ECC encoder 1270 generates a new parity using some changed data. Since the memory system 1000 according to the embodiment of the present invention does not use unaltered data when a new parity is obtained, data read time and power consumption can be reduced.

2 is a block diagram illustrating the memory device 1100 shown in FIG. 2, a memory device 1100 includes a memory cell array 1110, an address decoder 1120, a data input / output circuit 1130, and control logic 1140.

The memory cell array 1110 is connected to the address decoder 1120 through the word lines WL and to the data input / output circuit 1130 via the bit lines BL. The memory cell array 1110 includes a plurality of memory cells. The memory cells arranged in the row direction are connected to the word lines WL. The memory cells arranged in the column direction are connected to the bit lines BL. One or more data may be stored in one memory cell.

The address decoder 1120 is connected to the memory cell array 1110 via the word line WL. The address decoder 1120 receives the address ADDR from the memory controller (see FIG. 1) 1200. The address ADDR may include a row address and a column address. The address decoder 1120 selects one or more word lines WL using the row address and transfers the column address (CA) to the data input / output circuit 1130.

The data input / output circuit 1130 is connected to the memory cell array 1110 through the bit lines BL and exchanges the encoded data (DATA_C) with the memory controller 1200. The data input / output circuit 1130 operates in response to control of the control logic 1140. The data input / output circuit 1130 receives the column address CA from the address decoder 1120 and selects one or more bit lines BL.

The data input / output circuit 1130 receives the encoded data (DATA_C) from the outside and provides the received data (DATA_C) to the memory cell array 1110. The data input / output circuit 1130 reads the encoded data (DATA_C) from the memory cell array 1110 and outputs the read data (DATA_C) to the memory controller 1200.

Control logic 1140 is coupled to address decoder 1120 and data input / output circuitry 1130. The control logic 1140 receives the command CMD and the control signal CTRL from the memory controller 1200 and can control all operations of the memory device 1100 such as reading and writing operations .

FIGS. 3 and 4 are circuit diagrams showing an embodiment of the memory cell array shown in FIG. 2. FIG. FIG. 3 shows an example of a NAND flash memory, and FIG. 4 shows an example of a STT-MRAM (spin transfer torque magneto resistive random access memory).

Referring to FIG. 3, the memory cell array 1110a includes a plurality of flash memory cells. The memory cells MC1 to MCm provided along the row direction are connected to the word lines WL1 to WLm. The memory cells MC in the same row are connected to the same word line WL. The memory cells MC1 to MCm provided along the column direction correspond to the bit lines BL1 to BLn. The memory cells MC1 to MCm in the same column are connected to the same bit line BL.

String selection transistors SST are connected between the bit lines BL1 to BLn and the memory cells MC1 to MCm. The string selection transistors (SST) are connected to a string selection line (SSL). And the ground selection transistors GST are connected between the common source line CSL and the memory cells MC1 to MCm. The ground selection transistors GST may be connected to the ground selection line GSL.

4, the memory cell array 1110b includes a plurality of word lines WL1 to WLm, a plurality of bit lines BL1 to BLn, and word lines WL1 to WLm and bit lines BL1 to BLn ) Intersect with each other.

When the memory cell is implemented as a STT-MRAM (spin transfer torque magneto resistive random access memory) cell, a magnetic tunnel junction (hereinafter referred to as an MTJ element) having a cell transistor and a magnetic material may be included. The MTJ elements may be replaced by resistive elements such as a phase change random access memory (PRAM) using a phase change material, a resistive random access memory (RRAM) using a variable resistance material such as a complex metal oxide.

Referring again to FIG. 1, a memory system 1000 in accordance with an embodiment of the present invention includes an ECC encoder 1270 in a memory controller 1200. The ECC encoder 1270 according to the embodiment of the present invention can generate a new parity using some changed data when some data stored in the memory device 1100 is changed. According to the present invention, since a new parity is obtained using only a part of the changed data, the data read time and power consumption can be reduced.

Ⅱ. How to create a new parity if some data changes

5 is a block diagram showing the memory controller shown in FIG. 5, memory controller 1200 includes a system bus 1210, a control unit 1220, a RAM 1230, a host interface 1240, a memory interface 1250, and an ECC encoder 1270 .

The system bus 1210 provides a channel between the control unit 1220, the RAM 1230, the host interface 1240, the memory interface 1250, and the ECC encoder 1270. The control unit 1220 controls all operations of the memory controller 1200. The RAM 1230 may be used as at least one of an operation memory of the control unit 1220, a cache memory, and a buffer memory.

Host interface 1240 can communicate with host 1300 in accordance with a particular communication standard. Illustratively, memory controller 1200 may be any of a variety of devices, including, but not limited to, a Universal Serial Bus (USB), a peripheral component interconnection (PCI), a PCI-Express (PCI-E), an Advanced Technology Attachment (ATA), a Serial ATA, (see FIG. 1) via at least one of various communication standards such as a small computer small interface (ESDI), an integrated drive electronics (IDE), and a firewire have.

Memory interface 1250 interfaces with memory device 1100 (see Figure 1). For example, the memory interface 1250 includes a NAND flash interface or an MRAM interface.

The ECC encoder 1270 ECC encodes the data received from the host 1300. This data is called coded data (DATA_C). The data and parity received from the host 1300 are provided to the memory device 1100. Assuming that the data to be stored in the memory device 1100 is D1, D2, D3, and D4, the parity P can be calculated by Equation (1).

Figure pat00001

In the above equation (1), the addition operation is an XOR operation or a mod2 operation. Non-binary code, and non-linear code.

Continuing with reference to FIG. 5, the ECC encoder 1270 includes a new parity generator 1260. The ECC encoder 1270 can use the new parity generator 1260 to generate a new parity using some of the changed data when some of the data stored in the memory device 1100 is changed. In FIG. 5, the new parity generator 1260 may be located outside the ECC encoder 1270.

6 is a block diagram illustrating an exemplary new parity generator shown in FIG. Referring to FIG. 6, the new parity generator 1260 includes a data location identifier 1261, a data difference calculator 1262, and a parity calculator 1263.

The data location identifier 1261 identifies the location of the new data Dnew input from the host 1300 and provides the location difference signal LOC to the data difference calculator 1262 and the parity calculator 1263. [ Here, the location of the new data means the location of the data to be changed to new data among the data stored in the memory device 1100.

For example, assume that a parity (P) is generated through four pieces of data D1, D2, D3, and D4. At this time, the data D1 to D4 are located at positions d1 to d4, respectively. When D1 and D2 are changed to new data, the new data positions are d1 and d2. Hereinafter, the old data at the d1 position is denoted by D1old, and the new data is denoted by D1new. When the existing data D2old at the d1 position is changed to the new data D2new, the data position identifier 1261 provides the position signal LOC indicating d1.

The data difference calculator 1262 receives the position signal LOC of the new data from the data location identifier 1261 and receives the new data Dnew input from the host 1300 and the existing data Dold ) Is calculated. The data difference calculator 1262 provides the parity calculator 1263 with the data difference Ddif between the new data Dnew and the existing data Dold. The operation of the data difference calculator 1262 will be described in more detail with reference to FIGS. 8 and 9. FIG.

The parity calculator 1263 receives the position signal LOC of the new data and uses the data difference Ddif input from the data difference calculator 1262 and the existing parity Pold stored in the memory device 1100 to calculate a new parity (Pnew). The operation of the parity calculator 1263 will be described in more detail with reference to FIGS. 10 and 11. FIG.

On the other hand, the construction and operation principle of the new parity generator shown in FIG. 6 is based on the following mathematical principle. Assume that the data D1old, D2old, D3old, D4old, and the parity Pold are stored in the memory device 1100. [

The existing parity Pold can be calculated by Equation (1) as follows.

Pold = D1old + D2old + D3old + D4old ----- Equation (1)

Here, when D1old and D2old are changed to D1new and D2new, the Pold is also changed. When some of the data stored in the memory device 1100 is changed, the conventional memory system reads all the data (D1old, D2old, D3old, D4old) from the memory device 1100, changes the data and then outputs a new parity Pnew You must ask.

The new parity Pnew can be calculated by Equation (1) as follows.

Pnew = D1new + D2new + D3old + D4old ----- (2)

Subtracting equation (1) from equation (2) above is as follows.

Pnew-Pold = (D1old + D2old + D3old + D4old) - (D1new + D2new + D3old + D4old)

Pnew can be calculated as follows.

Pnew = Pold + (D1new + D2new + D3old + D4old) - (D1old + D2old + D3old + D4old)

Pnew = Pold + (D1new + D2new) - (D1old + D2old)

Pnew = Pold + (D1new-D1old) + (D2new-D2old)

In the process of obtaining the above equation (3), it can be seen that unchanged data (D3old, D4old) is eliminated in the calculation process. This means that if some of the data stored in the memory device 1100 is changed, unchanged data is unnecessary.

The conventional memory system reads all data including unchanged data (D3old, D4old) and calculates a new parity. In the conventional memory system, even if the size of the ECC data is large and the size of the changed data is small, all the data must be read in order to generate a new parity, so that a large amount of data is read and consumes a lot of power .

The memory system 1000 according to the embodiment of the present invention uses the new parity generator 1260 shown in Fig. 6 to perform a read operation without reading all the data when some of the data stored in the memory device 1100 is changed A new parity can be created using only some of the changed data. Since the memory system according to the embodiment of the present invention obtains the new parity using only the changed data, the data read time and power consumption can be reduced.

FIGS. 7 to 11 are diagrams or block diagrams for illustrating the operation of the new parity generator shown in FIG. 6 by way of example.

7, it is assumed that four existing data Dold and one existing parity P are stored in the memory device 1100. FIG. The existing data (Dold) at positions d1 to d4 are 0, 0, 1, and 1, respectively. That is, D1old is 0, D2old is 0, D3old is 1, and D4old is 1. If D1old to D4old are substituted into equation (1), Pold is 0 by XOR operation.

Suppose that the existing data D1old and D2old are changed to new data D1new and D2new. As shown in FIG. 7, D1new is 0, and D2new is 1. The data (D1new, D2new) to be changed in Fig. 7 are indicated by hatching. The new parity generator 1260 shown in Fig. 6 can generate a new parity Pnew without the unaltered data D3old, D4old. Hereinafter, a method of obtaining a new parity (Pnew) without D3old and D4old will be described.

8 is a block diagram showing the data difference calculator shown in FIG. Referring to FIG. 8, the data difference calculator 1262 receives a position signal (LOC) of new data and calculates a difference between the new data Dnew and the existing data Dold. The data difference Ddif is calculated by Equation (2).

Figure pat00002

In the above equation (2), the subtraction operation is an XOR operation or a mod2 operation. Non-binary code, and non-linear code. That is, the data difference calculator 1262 can calculate the data difference between the new data and the existing data by using the XOR operation in case of the binary linear code, and can calculate the difference between the non-binary code and the non- -linear code), it can be calculated through a corresponding operation.

In the equation (3), the data difference calculator 1262 receives the position signal d1 and calculates the difference D1dif between the new data D1new and the existing data D1old, And calculates the difference D2dif between the new data D2new and the existing data D2old. Here, D1dif denotes a difference between the data of the new data D1new at the d1 position and the data D1old. The data difference calculator 1262 receives the position signals d1 and d2 and may calculate the data differences D1dif and D2dif at the same time. The data differences D1dif and D2dif are provided to the parity calculator 1263. [

FIG. 9 is a diagram for illustrating an operation of the data difference calculator shown in FIG. 8 by way of example. As described above, when the existing data D1old and D2old are changed to the new data D1new and D2new, since D1new and D1old are both 0, D1dif will be 0 according to Equation (2). And since D2old is 0 and D2new is 1, D2dif will be 1.

10 is a block diagram showing the parity calculator shown in FIG. 10, the parity calculator 1263 receives a position signal (LOC) of a new data, calculates a difference between a data difference Ddif input from the data difference calculator 1262 and an existing parity Pold stored in the memory device 1100 ) To calculate a new parity Pnew. The new parity Pnew is calculated by Equation (3).

Figure pat00003

In the above example, Ddif is the sum of D1dif and D2dif. D1dif is the difference between D1new and D1old, and D2dif is the difference between D2new and D2old. That is, Equation (3) can be expressed as Equation (3) described above.

Pnew = Pold + D1dif + D2dif = Pold + (D1new-D1old) + (D2new-D2old)

 11 is a diagram for illustrating an operation of the parity calculator shown in FIG. 10 by way of example. As calculated in the example of Fig. 9, if D1dif is 0 and D2dif is 1, then the total data difference Ddif will be one. Since Pold is 0 and Ddif is 1, the new parity (Pnew) will be 1.

Referring to Equation (3), it can be seen that the new parity Pnew is expressed as a function of the existing parity Pold and the changed data difference Ddif. Here, it can be seen that the function for obtaining the new parity Pnew is irrelevant to the unchanged data (for example, D3old, D4old). It can also be extended to generic ECC, nonlinear code, or non-binary code.

Since the memory system according to the embodiment of the present invention obtains the new parity using only the changed data, the data read time and power consumption can be reduced. Particularly, the memory system according to the embodiment of the present invention can be usefully used when changing small units of data.

12 is a flowchart showing a new parity generation method of the memory system according to the embodiment of the present invention.

In step S110, the memory controller (see FIG. 1) 1200 reads the existing data Dold and the existing parity (Pold) from the memory device (see FIG. 1, 1100). In step S120, the memory controller 1200 receives the new data Dnew from the host (see FIG. 1) 1300. In step S130, the memory controller 1200 calculates the difference Ddif between the new data Dnew and the existing data Dold. In step S140, the memory controller 1200 calculates a new parity Pnew using the existing parity Pold and the data difference Ddif.

13 is a chart showing an example of a parity check matrix. Referring to FIG. 13, the code length of data stored in the memory device (see FIG. 1, 1100) is 72 and the data length is 64. Figure 13 is an example of a parity check matrix of (72, 64) Single Error Correction (SEC) and Double Error Detection (DED). Here, the single error correction (SEC) and the double error detection (DED) mean that one error can be corrected and two errors are detected.

 In FIG. 13, one row may be expressed by one parity check equation. The parity is created by adding the sign bits at positions corresponding to 1 in one row. For example, the parity P0 in the first row R1 can be obtained by the equation (4).

P0 = d0 + d1 + d2 + d3 + + d53 + d56 + d57 + d58 ----- (4)

The parities P1 to P7 in the second to eighth rows R2 to R8 can also be obtained in the same manner as in the above equation (4). Table 1 below shows the equation for obtaining the parity in each row.

P0 d0 + d1 + d2 + d3 + + d53 + d56 + d57 + d58 P1 d0 + d1 + d2 + d8 + + d58 + d59 + d60 + d61 P2 d3 + d4 + d5 + d8 + + d51 + d59 + d62 + d63 P3 d3 + d6 + d7 + d11 + + d47 + d48 + d51 + d59 P4 d3 + d11 + d14 + d15 + + d52 + d55 + d56 + d59 P5 d0 + d3 + d11 + d19 + + d54 + d57 + d60 + d63 P6 d1 + d4 + d7 + d8 + + d55 + d57 + d57 + d60 + d61 P7 d2 + d5 + d6 + d9 + + d60 + d61 + d62 + d63

A memory system (see FIG. 1, 1000) according to an embodiment of the present invention may generate a new parity for a plurality of rows. As shown in FIG. 13, a new parity can be generated for each of the first to eighth rows in units of a predetermined size. In this case as well, as described above, when only a part of data is changed, a new parity can be generated by using some changed data without reading all the data.

14 is a diagram showing a case where the first 1-byte data is changed in the parity check matrix shown in FIG. In Fig. 14, unchanged data, that is, data not used for obtaining the new parity Pnew is indicated by X. Fig.

When the first 1-byte data among the data stored in the memory device 1100 is changed, the existing memory system reads all the data shown in FIG. 13 and generates a new parity. However, the memory system according to the embodiment of the present invention (see FIG. 1, 1000) can only read the first 1-byte data and the 1-byte parity and generate a new parity. As shown in Equation (3), the memory system 1000 according to the embodiment of the present invention obtains the difference between the 1-byte new data Dnew and the 1-byte existing data Dold and calculates the difference between the data difference Ddif and the existing parity Pold) can be used to generate a new parity Pnew. According to the present invention, since the new parity is obtained using only the changed data, the data read time, parity generation time, and power consumption can be reduced.

On the other hand, when a new parity is obtained using only some data (for example, the first 1-byte data) of the memory device as shown in FIG. 14, ECC encoding can be performed by various methods. For example, the data to be unchanged can be regarded as all zeros, and ECC encoding can be performed. That is, all the X-marked data in FIG. 14 are regarded as 0, and the new parity Pnew can be obtained by using the difference Ddif of the changed data and the existing parity Pold. Alternatively, the data stored in the memory device (see FIG. 1) 1100 may be divided into sections of a predetermined size, and a new parity generation operation may be performed for each area.

FIG. 15 is a diagram showing an example of performing a new parity generation operation for each area in the parity check matrix shown in FIG. In order to perform a new parity generation operation for each area, an ECC encoder (see FIG. 5, 1270) may have a new parity generator for each area.

When the data of the first area (section 1) is changed, the new parity Pnew can be calculated by the following equation (3).

P0new = P0old + D0dif + D1dif + D2dif + D3dif + D4dif + D5dif + D6dif + D7dif -

Here, D1dif = D1new-D1old. The new parity generator for each region can be designed by the above equation (4). When the area-by-area parity generation operation is performed on a byte-by-byte basis as shown in FIG. 15, the ECC encoder 1270 can perform a byte-masking operation.

As described above, since the new parity is obtained using only the changed data, the present invention can reduce data read time and power consumption. Also, the present invention can be performed by dividing the new parity generation operation into different areas. Particularly, the memory system according to the embodiment of the present invention can be usefully used when changing small units of data.

Ⅲ. Application examples of the present invention

16 is a block diagram showing an application example of the memory system shown in Fig. 16, the memory system 2000 includes a memory device 2100 and a controller 2200. [ The memory device 2100 includes a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups. Each group of the plurality of memory chips may be configured to communicate with the controller 2200 via one common channel. Illustratively, the plurality of memory chips may communicate with the controller 2200 through the first through k-th channels CH1-CHk.

17 shows an example in which the memory system according to the embodiment of the present invention is implemented as a memory card. 17, memory card 3000 includes a memory device 3100, a controller 3200, and a connector 3300.

The connector 3300 can electrically connect the memory card 3000 and the host. The memory card 3000 may be a personal computer memory card (PCMCIA), a compact flash card CF, a smart media card SM, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro) SD cards (SD, miniSD, microSD, SDHC), universal flash memory (UFS), and the like.

FIG. 18 shows an example in which the memory system according to the embodiment of the present invention is implemented as a solid state drive (SSD). Referring to FIG. 18, solid state drive 4000 includes a plurality of memory devices 4100, a controller 4200, and a connector 4300. The connector 4300 can electrically connect the solid state drive 5000 and the host.

19 is a block diagram illustrating an example in which a memory system according to an embodiment of the present invention is applied to a computing system. Referring to FIG. 19, a computing system 5000 includes a bus 5100, a processor 5200, a memory system 5300, a modem 5400, and a user interface 5500.

Bus 5100 provides a channel between components of computing system 5000. The processor 5200 may control all operations of the computing system 5000 and may perform logical operations. Memory system 5300 may include a memory system 1000 or 2000 in accordance with an embodiment of the present invention.

The memory system 5300 may be provided as an operational memory or storage of the computing system 5000. The operational memory may be a storage space used by the processor 5200 to control the computing system 5000. Storage may be a storage space used by the computing system 5000 for long-term preservation of data.

When the memory system 5300 is provided in operational memory, the computing system 5000 may further include separate storage. When the memory system 5300 is provided as storage, the computing system 5000 may further include a separate working memory. The modem 5400 can perform wired or wireless communication with the outside.

The user interface 5500 may include a user output interface such as a user input interface such as a camera, a keyboard, a mouse, a microphone, a touch pad, a touch panel, a button, a sensor, etc., a display, a speaker, a lamp,

The computing system 5000 may form a mobile multimedia device such as a smart phone, a smart pad, or the like, or a multimedia device such as a smart television, a smart monitor, a computer, a notebook computer, and the like.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

1000, 2000; Memory system
1100, 2100; Memory devices 1200, 2200; controller
1110; A memory cell array 1120; The address decoder
1130; A read and write circuit 1140; Control logic
1210; System bus 1220; The control unit
1230; Random access memory 1240; Host interface
1250; Memory interface 1260; ECC encoder

Claims (20)

CLAIMS What is claimed is: 1. A memory controller for generating a new parity when some data in a memory device changes, comprising:
A data location identifier for identifying a location of some of the data to be changed;
And a data difference calculator for calculating a data difference (Ddif) between the new data (Dnew) input from the host and the existing data (Dold) input from the memory device, ; And
And a parity calculator for calculating a new parity (Pnew) using the existing parity (Pold) stored in the memory device and the data difference (Ddif). The method according to claim 1,
Wherein the data location identifier, the data difference calculator, and the parity calculator are included in a new parity generator. 3. The method of claim 2,
The new parity generator is within the ECC encoder. 3. The method of claim 2,
Wherein the new parity generator is outside the ECC encoder. The method according to claim 1,
Wherein the data difference calculator processes all unchanged data in the data stored in the memory device as 0 and calculates a data difference Ddif between the new data Dnew and the existing data Dold. The method according to claim 1,
Wherein the data difference calculator divides the part of the data to be changed into a plurality of areas and calculates data difference between new data and existing data in each area. The method according to claim 1,
Wherein the data difference calculator calculates a data difference between the new data and the existing data through an XOR operation. The method according to claim 1,
Wherein the parity calculator computes the existing parity and the data difference through an XOR operation. The method according to claim 1,
Wherein the memory device is a volatile memory device. The method according to claim 1,
Wherein the memory device is a non-volatile memory device. A memory device for storing data and a parity (Pold);
A host providing new data (Dnew) and location information for modifying some data stored in the memory device; And
(Ddif) between the new data provided from the host and existing data input from the memory device, and storing the existing parity stored in the memory device, And a memory controller for generating a new parity Pnew using the data difference Ddif. 12. The method of claim 11,
The memory controller
A data location identifier for identifying a location of some of the data to be changed;
(Dnif) for calculating a data difference (Ddif) between the new data (Dnew) input from the host and the existing data (Dold) input from the memory device A calculator; And
And a parity calculator for calculating a new parity (Pnew) using the existing parity (Pold) and the data difference (Ddif). 12. The method of claim 11,
Wherein the data difference calculator processes all unchanged data in the data stored in the memory device as 0 and calculates a data difference Ddif between the new data Dnew and the existing data Dold. 12. The method of claim 11,
Wherein the data difference calculator divides the part of the data to be changed into a plurality of areas and calculates data difference between new data and existing data in each area. 12. The method of claim 11,
The memory controller having the data location identifier, the data difference calculator, and the parity calculator in an ECC encoder. 16. The method of claim 15,
The ECC encoder is used for binary, non-binary linear or non-linear codes. 12. The method of claim 11,
Wherein the memory device and the memory controller are implemented as a memory card. 12. The method of claim 11,
Wherein the memory device and the memory controller are implemented as an SSD. 12. The method of claim 11,
Wherein the memory device is a flash memory device. 12. The method of claim 11,
Wherein the memory device is an MRAM.
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US14/071,771 US9311181B2 (en) 2012-11-15 2013-11-05 Memory controller changing partial data in memory device and method for changing partial data thereof
DE102013112195.0A DE102013112195A1 (en) 2012-11-15 2013-11-06 A memory controller that changes part data in a memory device, and a method of changing part data thereof
TW102140195A TWI627535B (en) 2012-11-15 2013-11-06 Memory controller changing partial data in memory device and method for changing partial data thereof
JP2013235041A JP2014099174A (en) 2012-11-15 2013-11-13 Memory controller for partial data stored in memory device and method for changing the same partial data
CN201310575217.0A CN103824599B (en) 2012-11-15 2013-11-15 Change the Memory Controller and its method of the partial data in memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160091080A (en) * 2015-01-23 2016-08-02 삼성전자주식회사 Memory system and method of operating the memory system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011198272A (en) * 2010-03-23 2011-10-06 Toshiba Corp Semiconductor storage device and control method thereof
JP2012507104A (en) * 2008-10-28 2012-03-22 マイクロン テクノロジー， インク． Error correction in multiple semiconductor memory units

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012507104A (en) * 2008-10-28 2012-03-22 マイクロン テクノロジー， インク． Error correction in multiple semiconductor memory units
JP2011198272A (en) * 2010-03-23 2011-10-06 Toshiba Corp Semiconductor storage device and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160091080A (en) * 2015-01-23 2016-08-02 삼성전자주식회사 Memory system and method of operating the memory system

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